Display panel and display equipment

Abstract

The embodiment of the invention discloses a display panel and a display device, scanning lines and data line groups are arranged in a crossed mode to form a plurality of pixel areas, one pixel electrode group is correspondingly arranged in one pixel area, each data line group comprises a first data line and a second data line, and the first data line and the second data line are arranged in a staggered mode. Each pixel electrode group comprises a first pixel electrode and a second pixel electrode, in the first direction, the first pixel electrodes and the second pixel electrodes are alternately arranged, the first data lines and the second data lines are alternately arranged, the first data lines are connected with the second pixel electrodes of the first pixel rows and the first pixel electrodes of the second pixel rows, and the second data lines are connected with the second pixel electrodes of the second pixel rows. The second data line connects the first pixel electrode of the first pixel row and the second pixel electrode of the second pixel row. According to the display panel and the display equipment, a data line group layout mode is adopted, the wiring area in the first direction is reduced, and the effect of improving the aperture ratio is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Based on the patent document disclosed in CN108628049B, there is an indentation between adjacent rows of sub-pixel regions, and the rows are arranged in an aligned manner at intervals, so that the data line is designed in a rectangular wave shape. In addition, since a data line is arranged between each two adjacent sub-pixel regions, a distance needs to be set between both sides of each data line and the adjacent pixel electrodes, which increases the wiring area of ​​the data line, thereby reducing the aperture ratio. Summary of the invention

[0003] Embodiments of the present application provide a display panel and a display device, which can improve the aperture ratio.

[0004] An embodiment of the present application provides a display panel, including an array substrate and an opposing substrate arranged opposite to the array substrate, wherein the array substrate includes:

[0005] A plurality of scan lines and a plurality of data line groups, wherein the plurality of data line groups are arranged along a first direction, the scan lines extend along the first direction, and the plurality of scan lines are arranged along a second direction intersecting the first direction; the plurality of scan lines and the plurality of data line groups are intersected to form a plurality of pixel regions; and

[0006] A plurality of pixel electrode groups, one of the pixel electrode groups is correspondingly arranged in one of the pixel regions, the plurality of pixel electrode groups are arranged along the first direction to form pixel rows, the pixel rows include a first pixel row and a second pixel row, the first pixel row and the second pixel row are arranged along the second direction; in the second direction, one pixel electrode group of the first pixel row is correspondingly arranged between two adjacent pixel electrode groups of the second pixel row;

[0007] Among them, each of the data line groups includes a first data line and a second data line, each of the pixel electrode groups includes a first pixel electrode and a second pixel electrode, in the first direction, the first pixel electrodes and the second pixel electrodes are arranged alternately, the first data lines and the second data lines are arranged alternately, the first data line connects the second pixel electrode of the first pixel row and the first pixel electrode of the second pixel row, and the second data line connects the first pixel electrode of the first pixel row and the second pixel electrode of the second pixel row.

[0008] Optionally, in some embodiments of the present application, the first data line includes a first routing portion, a second routing portion, and a third routing portion, the first routing portion is correspondingly arranged at the first pixel row, the third routing portion is correspondingly arranged at the second pixel row, the second routing portion is correspondingly arranged between the first pixel row and the second pixel row and connected to the first routing portion and the third routing portion, the second data line includes a fourth routing portion, a fifth routing portion, and a sixth routing portion, the fourth routing portion is correspondingly arranged at the first pixel row, the sixth routing portion is correspondingly arranged at the second pixel row, the fifth routing portion is correspondingly arranged between the first pixel row and the second pixel row and connected to the fourth routing portion and the sixth routing portion;

[0009] The first wiring portion is connected to the second pixel electrode of the first pixel row, the third wiring portion is connected to the first pixel electrode of the second pixel row, the fourth wiring portion is connected to the first pixel electrode of the first pixel row, and the sixth wiring portion is connected to the second pixel electrode of the second pixel row;

[0010] In the first direction, the second routing portion is located at one side of the fifth routing portion, and in the second direction, the second routing portion and the fifth routing portion are arranged non-overlappingly.

[0011] Optionally, in some embodiments of the present application, the first routing portion, the third routing portion, the fourth routing portion and the sixth routing portion all extend along the second direction, and the second routing portion and the fifth routing portion all extend along the first direction;

[0012] In the first direction, the second routing portion and the fifth routing portion are aligned.

[0013] Optionally, in some embodiments of the present application, the counter substrate includes a black matrix layer, the black matrix layer includes a first light shielding strip and a second light shielding strip, the first light shielding strip extends along the first direction, the second light shielding strip extends along the second direction, a plurality of the first light shielding strips and a plurality of the second light shielding strips are cross-connected to form a plurality of openings, some of the openings are facing the first pixel electrode, and another part of the openings are facing the second pixel electrode;

[0014] The second light shielding strip includes a first light shielding portion and a second light shielding portion. In the first direction, the width of the first light shielding portion is greater than the width of the second light shielding portion. In the first direction, the first light shielding portion and the second light shielding portion are alternately arranged. In the second direction, the first light shielding portion and the second light shielding portion are alternately connected.

[0015] In the display panel viewed from a top-down perspective, the first shading strip covers the scan line, the second routing portion and the fifth routing portion, the first shading portion covers a portion of the data line group between two adjacent groups of pixel electrode groups in the first direction, and the second shading portion covers an area between the first pixel electrode and the second pixel electrode in the pixel electrode group.

[0016] Optionally, in some embodiments of the present application, the array substrate further includes a plurality of thin film transistor groups, the thin film transistor groups are arranged between two adjacent pixel electrode groups and located in a corner area of ​​the pixel electrode groups, each of the thin film transistor groups includes a first thin film transistor and a second thin film transistor, a control end of the first thin film transistor and a control end of the second thin film transistor are connected to the scan line, an input end of the first thin film transistor is connected to the first data line, an input end of the second thin film transistor is connected to the second data line, in the first pixel row, an output end of the first thin film transistor is connected to the second pixel electrode, and an output end of the second thin film transistor is connected to the first pixel electrode; in the second pixel row, an output end of the first thin film transistor is connected to the first pixel electrode, and an output end of the second thin film transistor is connected to the second pixel electrode;

[0017] Among them, the first thin film transistors and the second thin film transistors are alternately arranged in rows along the first direction; in each of the thin film transistor groups, the first thin film transistor is arranged on a side of the first data line away from the second data line, and the second thin film transistor is arranged on a side of the second data line away from the first data line.

[0018] Optionally, in some embodiments of the present application, the display panel further includes a plurality of spacers, the array substrate includes a common wiring extending along the first direction, and the common wiring and the spacers are arranged between the first pixel row and the second pixel row;

[0019] In the display panel viewed from a top view, at least one of the common wiring, the scan line and the data line group is partially overlapped with the spacer, and the spacer is arranged at the intersection of the first light shielding strip and the second light shielding strip.

[0020] Optionally, in some embodiments of the present application, a third shading portion is connected to both sides of the intersection of the first shading strip and the second shading strip; in the display panel viewed from a top-down perspective, the third shading portion and the portions of the first shading strip and the second shading strip respectively connected to the third shading portion cover the spacer as a whole.

[0021] Optionally, in some embodiments of the present application, each of the pixel regions is a dual-pixel domain region, and the first pixel electrode and the second pixel electrode correspond to one pixel domain region respectively.

[0022] Optionally, in some embodiments of the present application, the display panel further includes a plurality of spacers, the spacers are adjacent to the scan lines, and in the display panel viewed from a top perspective, in the first direction, the first data line and the second data line in the same data line group respectively overlap with a portion of the same spacer;

[0023] Each of the pixel regions is a four-pixel domain region, and the four pixel domain regions are arranged in a matrix along the first direction and the second direction, and in the second direction, the liquid crystals of two of the pixel domain regions have different tilt directions;

[0024] The array substrate further includes a common wiring, which is extended along the first direction. In the display panel viewed from a top view, the common wiring is arranged between two adjacent pixel domains in the second direction.

[0025] Optionally, in some embodiments of the present application, in the first direction, third light shading portions are connected to both sides of the first light shading portion, and in the display panel viewed from a top view, the first light shading portion and the third light shading portions on both sides thereof cover the spacer as a whole.

[0026] Optionally, in some embodiments of the present application, the spacer is formed on the opposing substrate, and in the display panel viewed from a top perspective, the spacer is located outside the thin film transistor group.

[0027] Optionally, in some embodiments of the present application, the spacer is formed on the opposing substrate, the array substrate includes an alignment film, and an alignment direction of the alignment film is parallel to the first direction.

[0028] Optionally, in some embodiments of the present application, a plurality of the pixel electrode groups are arranged in the same layer to form a pixel electrode layer, the array substrate further comprises a common electrode layer, the pixel electrode layer and the common electrode layer are arranged in different layers, the common electrode layer comprises a plurality of common electrodes, and one of the common electrodes is correspondingly arranged in one of the pixel regions; in the display panel in a top-down perspective, one of the common electrodes overlaps with a first pixel electrode and a second pixel electrode of the same pixel electrode group at the same time;

[0029] The pixel electrode group and the common electrode that is closer to the opposing substrate are provided with slits; in the pixel electrode group of the display panel viewed from a top view, a pattern composed of all the slits in the first pixel electrodes and a pattern composed of all the slits in the second pixel electrodes are axially symmetrical patterns to each other.

[0030] Correspondingly, an embodiment of the present application further provides a display device, which includes the display panel described in any one of the above embodiments.

[0031] The display panel and display device of the embodiments of the present application adopt a data line group layout method, so that there is no data line between the first pixel electrode and the second pixel electrode in the pixel electrode group, which greatly reduces the distance between the first pixel electrode and the second pixel electrode in the pixel electrode group. Although a data line is added between the pixel electrode groups, the smaller distance between the first data line and the second data line reduces the wiring area in the first direction to improve the aperture ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic top plan view of a display panel provided in an embodiment of the present application;

[0033] Figure 2 is a schematic cross-sectional structural diagram of a display panel provided in an embodiment of the present application;

[0034] Figure 3 yes Figure 1 An enlarged schematic view of the M portion in FIG.

[0035] Figure 4 yes Figure 3 A schematic diagram of the structure of the common electrode;

[0036] Figure 5 is a schematic diagram of a picture frame of a display panel provided in an embodiment of the present application;

[0037] Figure 6 is based on Figure 3 A schematic diagram of the structure of a black matrix layer;

[0038] Figure 7 yes Figure 1 Another enlarged schematic view of the M portion in FIG.

[0039] Figure 8 is based on Figure 7 A schematic diagram of the structure of a black matrix layer;

[0040] Fig. 9 yes Figure 1 Another enlarged schematic view of the M portion in FIG.

[0041] Fig.10 is based on Fig. 9 A schematic diagram of the structure of a black matrix layer;

[0042] Fig.11 yes Figure 1 Another enlarged schematic view of the M portion in FIG.

[0043] Fig.12 yes Fig.11 A schematic diagram of the structure of the common electrode;

[0044] Fig.13 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the various embodiments can be combined with each other but will not be repeated one by one, and in the absence of contrary instructions, the directional words used, such as "upper" and "lower", usually refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements are imposed or order is established.

[0046] The embodiments of the present application provide a display panel and a display device, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0047] exist Figure 1 and Figure 2 In the embodiment, the first direction F1 may be a direction parallel to one side of the display panel 100 in a plan view, and may be, for example, a transverse direction of the display panel 100. The second direction F2 may be a direction parallel to the other side of the display panel 100 in a plan view, and may be a longitudinal direction of the display panel 100. The third direction F3 may be a thickness direction of the display panel 100. Optionally, in some embodiments, the first direction F1 and the second direction F2 may also intersect non-perpendicularly.

[0048] The display panel 100 may have a rectangular shape in a plan view, but the embodiment is not limited thereto. In some embodiments, the display panel 100 may have a rectangular shape with vertical corners or rounded corners in a plan view. The display panel 100 may include two short sides arranged in the first direction F1 and two long sides arranged in the second direction F2 in a plan view.

[0049] It should be noted that, according to the display panel 100 of the embodiment, the display panel 100 is a liquid crystal display panel, which includes an array substrate 10, an opposing substrate 20, and a liquid crystal disposed between the array substrate 10 and the opposing substrate 20. Optionally, the array substrate 10 may be based on a Fringe Field Switching (FFS) technology drive architecture, or may be based on an In-Plane Switching (IPS) technology drive architecture, or may be based on a Vertical Alignment (VA) technology or a Twisted Nematic (TN) drive architecture, etc. Optionally, the opposing substrate 20 may be formed with a color filter layer, or may not have a color filter layer, for example, the color filter layer is formed in the array substrate 10.

[0050] Please refer to Figure 2 , the display panel 100 of the embodiment of the present application will be described below based on the array substrate 10 as a fringe field switching technology driving architecture.

[0051] In some embodiments, the array substrate 10 and the counter substrate 20 are arranged opposite to each other. The array substrate 10 includes a first substrate 11, a thin film transistor structure layer 12, a pixel electrode layer 13, a common electrode layer 14 and an alignment film 15. The counter substrate 20 includes a second substrate 21 and a black matrix layer 22, and the black matrix layer 22 is arranged on a side of the second substrate 21 close to the array substrate 10.

[0052] It should be noted that the pixel electrode layer 13 and the common electrode layer 14 are arranged in different layers, and the pixel electrode layer 13 can be arranged in the same layer as a film layer in the thin film transistor structure layer 12, or can be arranged in a different layer from the thin film transistor structure layer 12. In the embodiments of the present application, there is no restriction on the film layer position relationship between the pixel electrode layer 13, the common electrode layer 14 and the thin film transistor structure layer 12, as long as the fringe field switching technology can be satisfied.

[0053] Hereinafter, the embodiments corresponding to the drawings will be described in detail, but are not limited thereto.

[0054] exist Figure 2In the embodiment, a thin film transistor structure layer 12 is arranged on a first substrate 11, a pixel electrode layer 13 is arranged on the same layer as a data line (12a and 12b) in the thin film transistor structure layer 12, an insulating layer 16 covers the pixel electrode layer 13 and the thin film transistor structure layer 12, a common electrode layer 14 is arranged on a side of the insulating layer 16 away from the first substrate 11, and an alignment film 15 is arranged on a side of the common electrode layer 14 away from the first substrate 11.

[0055] It should be noted that the thin film transistor structure layer 12 includes a plurality of thin film transistors ( t1 and t2 ), and the plurality of thin film transistors may be at least one of a top gate type, a bottom gate type, a double gate type, and a vertical channel type.

[0056] exist Figure 2 In the embodiment, the source and drain of the thin film transistor are directly formed on the active layer. The pixel electrode layer 13 is directly connected to the drain. A slit 14a is formed on the common electrode layer 14, and the slit 14a is configured to assist in adjusting the tilt angle of the liquid crystal molecules.

[0057] In some embodiments of the present application, the pixel electrode layer 13 is disposed on a side of the common electrode layer 14 away from the first substrate 11 , and a slit 14 a is formed on the pixel electrode layer 13 .

[0058] Please refer to Figure 3 , Figure 3 It is shown that Figure 1 An enlarged schematic view of portion M in FIG.

[0059] The array substrate 10 includes a plurality of scan lines 121 , a plurality of data line groups 122 and a plurality of pixel electrode groups 131 .

[0060] The plurality of data line groups 122 are arranged along a first direction F1, the scan lines 121 extend along the first direction F1, and the plurality of scan lines 121 are arranged along a second direction F2 intersecting the first direction F1. The plurality of scan lines 121 and the plurality of data line groups 122 are intersected to form a plurality of pixel regions 1a.

[0061] A pixel electrode group 131 is correspondingly arranged in a pixel area 1a. A plurality of pixel electrode groups 131 are arranged along a first direction F1 to form a pixel row, and the pixel row includes a first pixel row p1 and a second pixel row p2. The first pixel row p1 and the second pixel row p2 are arranged along a second direction F2. In the second direction F2, a pixel electrode group 131 of the first pixel row p1 is correspondingly arranged between two adjacent pixel electrode groups 131 of the second pixel row p2.

[0062] Each data line group 122 includes a first data line 12a and a second data line 12b. Each pixel electrode group 131 includes a first pixel electrode 13a and a second pixel electrode 13b. In the first direction F1, the first pixel electrodes 13a and the second pixel electrodes 13b are alternately arranged, and the first data lines 12a and the second data lines 12b are alternately arranged. The first data line 12a connects the second pixel electrode 13b of the first pixel row p1 and the first pixel electrode 13a of the second pixel row p2, and the second data line 12b connects the first pixel electrode 13a of the first pixel row p1 and the second pixel electrode 13b of the second pixel row p2.

[0063] The display panel 100 of the embodiment of the present application adopts a data line group 122 layout, so that there is no data line between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131, which greatly reduces the distance between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131. Although a data line is added between the pixel electrode groups 131, in the first direction F1, the distance between the two data lines (12a and 12b) in the same data line group 122 is smaller than the distance from the data line to the nearest pixel electrode, that is, the distance between the first data line 12a and the second data line 12b is smaller, thereby reducing the wiring area in the first direction F1 to improve the aperture ratio.

[0064] In some embodiments, the first data line 12a and the second data line 12b may also be arranged in different layers. In the first direction F1, the first data line 12a and the second data line 12b may be smaller, and even the first data line 12a and the second data line 12b may at least partially overlap, so as to further reduce the distance between the first data line 12a and the second data line 12b in the first direction F1 and improve the aperture ratio.

[0065] In some embodiments of the present application, the array substrate 10 further includes a plurality of thin film transistor groups 12c, which are arranged between two adjacent pixel electrode groups 131 and located in the corner area of ​​the pixel electrode group 131. Each thin film transistor group 12c includes a first thin film transistor t1 and a second thin film transistor t2. The control end of the first thin film transistor t1 and the control end of the second thin film transistor t2 are connected to the scan line 121, the input end of the first thin film transistor t1 is connected to the first data line 12a, and the input end of the second thin film transistor t2 is connected to the second data line 12b. In the first pixel row p1, the output end of the first thin film transistor t1 is connected to the second pixel electrode 13b, and the output end of the second thin film transistor t2 is connected to the first pixel electrode 13a. In the second pixel row p2, the output end of the first thin film transistor t1 is connected to the first pixel electrode 13a, and the output end of the second thin film transistor t2 is connected to the second pixel electrode 13b.

[0066] The first thin film transistors t1 and the second thin film transistors t2 are alternately arranged in rows along the first direction F1.

[0067] It can be understood that in the same thin film transistor group 12c, a first thin film transistor t1 and a second thin film transistor t2 share a gate, that is, a first thin film transistor t1 and a second thin film transistor t2 are gathered side by side by sharing a gate to form the thin film transistor group 12c, which reduces the total layout area of ​​the entire thin film transistor and thereby improves the aperture ratio.

[0068] Secondly, in the first direction F1 , the first thin film transistor t1 and the second thin film transistor t2 are arranged side by side, which further reduces the layout area in the second direction F2 and improves the aperture ratio.

[0069] Optionally, in some embodiments of the present application, in each thin film transistor group 12c, the first thin film transistor t1 is arranged on a side of the first data line 12a away from the second data line 12b, and the second thin film transistor t2 is arranged on a side of the second data line 12b away from the first data line 12a.

[0070] It can be understood that by arranging the data line group 122 between two thin film transistors in the thin film transistor group 12c, the distance between the first data line 12a and the second data line 12b in the data line group 122 is shortened, thereby improving the aperture ratio.

[0071] Optionally, in some embodiments of the present application, the first data line 12a includes a first routing portion a1, a second routing portion a2, and a third routing portion a3, the first routing portion a1 is correspondingly arranged at the first pixel row p1, the third routing portion a3 is correspondingly arranged at the second pixel row p2, the second routing portion a2 is correspondingly arranged between the first pixel row p1 and the second pixel row p2 and connected to the first routing portion a1 and the third routing portion a3. The second data line 12b includes a fourth routing portion b1, a fifth routing portion b2, and a sixth routing portion b3, the fourth routing portion b1 is correspondingly arranged at the first pixel row p1, the sixth routing portion b3 is correspondingly arranged at the second pixel row p2, and the fifth routing portion b2 is correspondingly arranged between the first pixel row p1 and the second pixel row p2 and connected to the fourth routing portion b1 and the sixth routing portion b3.

[0072] The first routing portion a1 is connected to the second pixel electrode of the first pixel row p1, the third routing portion a3 is connected to the first pixel electrode of the second pixel row p2, the fourth routing portion b1 is connected to the first pixel electrode of the first pixel row p1, and the sixth routing portion b3 is connected to the second pixel electrode of the second pixel row p2.

[0073] In the first direction F1, the second routing portion a2 is located at one side of the fifth routing portion b2. In the second direction F2, the second routing portion a2 and the fifth routing portion b2 are arranged non-overlappingly.

[0074] It can be understood that by arranging the second wiring portion a2 and the fifth wiring portion b2 along the first direction F1 , the layout area of ​​the second wiring portion a2 and the fifth wiring portion b2 in the second direction F2 can be reduced, thereby increasing the aperture ratio.

[0075] Optionally, in some embodiments of the present application, the first routing portion a1, the third routing portion a3, the fourth routing portion b1 and the sixth routing portion b3 all extend along the second direction F2. The second routing portion a2 and the fifth routing portion b2 all extend along the first direction F1. In the first direction F1, the second routing portion a2 and the fifth routing portion b2 are aligned.

[0076] It can be understood that the second routing portion a2 and the fifth routing portion b2 are aligned and overlapped in the first direction F1, so that the layout area of ​​the second routing portion a2 and the fifth routing portion b2 in the second direction F2 is further reduced to improve the aperture ratio.

[0077] Optionally, in some embodiments of the present application, the display panel 100 further includes a plurality of spacers 17. The spacers 17 are adjacent to the scan lines 121. In the display panel 100 in a top view, in the first direction F1, the first data line 12a and the second data line 12b in the same data line group 122 overlap with a portion of the same spacer 17 respectively.

[0078] It is understandable that the spacer 17 may be formed on the array substrate 10 or on the counter substrate 20. The spacer 17 is disposed between the first data line 12a and the second data line 12b, and extends to the left and right so that the spacer 17 partially overlaps with the first data line 12a and the second data line 12b of the data line group 122, so as to reduce the light-transmitting area occupied by the spacer 17, thereby improving the aperture ratio.

[0079] Optionally, in the first direction F1, the width of the spacer 17 is less than or equal to the width of the data line group 122, that is, the spacer 17 is completely disposed within the layout area of ​​the data line group 122, avoiding the spacer 17 from occupying additional layout area to improve the aperture ratio.

[0080] Optionally, in some embodiments of the present application, the spacer 17 is formed on the counter substrate 20. In the display panel 100 in a top view, the spacer 17 is located outside the thin film transistor group 12c.

[0081] It is understandable that, since the topography of the thin film transistor group 12c is relatively uneven, if the spacer 17 is disposed at the thin film transistor group 12c, the contact area between the spacer 17 and the array substrate 10 is small, which reduces the support performance of the spacer 17. Therefore, the spacer 17 is disposed outside the thin film transistor group 12c to increase the contact area between the spacer 17 and the array substrate 10, thereby improving the support performance of the spacer 17.

[0082] Optionally, in some embodiments of the present application, the spacers 17 are formed on the counter substrate 20. The array substrate 10 includes an alignment film 15, and the alignment direction of the alignment film 15 is parallel to the first direction F1.

[0083] It should be understood that under the action of external force, the spacer 17 and the array substrate 10 will slide relative to each other. When the spacer 17 slides along the left and right direction (the first direction F1), compared with the sliding direction of the spacer 17 being perpendicular to the alignment direction of the alignment film 15, the sliding direction of the spacer 17 is the same as the alignment direction of the alignment film 15, which can reduce the interference of the spacer 17 on the alignment direction of the alignment film 15, thereby reducing the risk of red and blue spots.

[0084] Optionally, in some embodiments of the present application, each pixel region 1a is composed of four pixel domains, and the four pixel domains are arranged in a matrix along the first direction F1 and the second direction F2. In the second direction F2, the liquid crystals in the two pixel domains have different tilt directions.

[0085] The array substrate 10 further includes a common wiring 124, which is extended along the first direction F1. In the display panel 100 in a top view, in the second direction F2, the common wiring 124 is arranged between two adjacent pixel domains.

[0086] It should be understood that the liquid crystals in the two pixel domains are tilted in different directions, which makes the arrangement of the liquid crystal molecules at the junction between the two pixel domains irregular, so that dark lines are easily formed. Therefore, the common line 124 is set at the junction between the two pixel domains, and the dark lines can be used to cover the common line 124 to achieve the effect of increasing the aperture ratio.

[0087] In some embodiments of the present application, a plurality of pixel electrode groups 131 are arranged in the same layer and formed in the pixel electrode layer 13. The array substrate 10 also includes a common electrode layer 14 connected to the common wiring 124. The pixel electrode layer 13 and the common electrode layer 14 are arranged in different layers. The common electrode layer 14 includes a plurality of common electrodes 141, and a common electrode 141 is correspondingly arranged in a pixel area 1a. In the display panel 100 in a top view, a common electrode 141 overlaps with a first pixel electrode 13a and a second pixel electrode 13b of the same pixel electrode group 131 at the same time.

[0088] The one of the pixel electrode group 131 and the common electrode 141 closer to the counter substrate 20 is provided with a slit 14 a.

[0089] Combination Figure 2 , the common electrode 141 is closer to the counter substrate 20, so the slit 14a is formed on the common electrode 141. In the embodiment of the present application, one common electrode 141 overlaps with two pixel electrodes at the same time, which can reduce the number of vias 14b connecting the common electrode 141 to the common wiring 124.

[0090] Optionally, the via hole 14b is disposed between the first pixel electrode 13a and the second pixel electrode 13b.

[0091] Optional, see Figure 4 , Figure 4 It is shown that Figure 3 Schematic diagram of the structure of the common electrode 141. The four pixel domains include a first domain c1, a second domain c2, a third domain c3 and a fourth domain c4. The first domain c1 and the second domain c2 correspond to the first pixel electrode 13a, and the third domain c3 and the fourth domain c4 correspond to the second pixel electrode 13b.

[0092] The first domain c1 and the second domain c2 are arranged along the second direction F2, the third domain c3 and the fourth domain c4 are arranged along the second direction F2, the first domain c1 and the third domain c3 are arranged along the first direction F1, and the second domain c2 and the fourth domain c4 are arranged along the first direction F1.

[0093] The extending direction of the slits 14a intersects with the alignment direction (first direction F1) of the alignment film 15. In the first domain region c1, the plurality of slits 14a extend along the fourth direction F4. In the second domain region c2, the plurality of slits 14a extend along the fifth direction F5. In the third domain region c3, the plurality of slits 14a extend along the sixth direction F6. In the fourth domain region c4, the plurality of slits 14a extend along the seventh direction F7.

[0094] It can be understood that one pixel region 1 a has four pixel domains, which can expand the viewing angle of the display panel 100 .

[0095] In some embodiments, the positions of the first pixel electrode 13a and the second pixel electrode 13b can be interchanged. For example, the first domain c1 of the corresponding first pixel electrode 13a is interchanged with the third domain c3 of the corresponding second pixel electrode 13b, and the second domain c2 of the corresponding first pixel electrode 13a is interchanged with the fourth domain c4 of the corresponding second pixel electrode 13b; the corresponding slits 14a are also interchanged along with the domains.

[0096] The extension direction of the junction of the first domain c1 and the second domain c2 and the junction of the third domain c3 and the fourth domain c4 overlaps. The common line 124 passes through the junction of the first domain c1 and the second domain c2 and the junction of the third domain c3 and the fourth domain c4.

[0097] Optionally, in some embodiments of the present application, in the pixel electrode group 131 of the display panel 100 in a top view, a pattern composed of all the slits 14a located in the first pixel electrode 13a and a pattern composed of all the slits 14a located in the second pixel electrode 13b are axially symmetric patterns to each other.

[0098] That is, the slit 14a pattern of the first domain area c1 and the slit 14a pattern of the third domain area c3 are arranged axially symmetrically with each other, and the slit 14a pattern of the second domain area c2 and the slit 14a pattern of the fourth domain area c4 are arranged axially symmetrically with each other to improve the brightness uniformity of the horizontal viewing angle.

[0099] Please refer to Figure 5 , Figure 5 What is shown is a driving architecture diagram of the display panel 100 of one or more embodiments of the present application. In some embodiments of the present application, in the second direction F2, the first pixel electrode 13a and the second pixel electrode 13b are alternately arranged in pixel columns. In the same picture frame, the voltage polarity connected to the first data line 12a and the voltage polarity connected to the second data line 12b are opposite. For example, the first data line 12a is connected to a positive polarity voltage, and the second data line 12b is connected to a negative polarity voltage; or, the first data line 12a is connected to a negative polarity voltage, and the second data line 12b is connected to a positive polarity voltage.

[0100] It should be noted that since the first data line 12a connects the second pixel electrode 13b of the first pixel row p1 and the first pixel electrode 13a of the second pixel row p2, and the second data line 12b connects the first pixel electrode 13a of the first pixel row p1 and the second pixel electrode 13b of the second pixel row p2, the voltage polarities of the first pixel electrode 13a and the second pixel electrode 13b in the same pixel column are the same, and the voltage polarities of the first pixel electrode 13a and the second pixel electrode 13b in the same pixel row are opposite, thereby achieving a column flipping effect, reducing horizontal crosstalk and improving the display effect.

[0101] Please refer to Figure 6In some embodiments of the present application, the black matrix layer 22 includes a first light shielding strip 221 and a second light shielding strip 222. The first light shielding strip 221 extends along the first direction F1, and the second light shielding strip 222 extends along the second direction F2. A plurality of first light shielding strips 221 and a plurality of second light shielding strips 222 are cross-connected to form a plurality of openings 223. Some of the openings 223 face the first pixel electrode 13a, and another portion of the openings 223 face the second pixel electrode 13b.

[0102] The second light shielding strip 222 includes a first light shielding portion 22a and a second light shielding portion 22b. In the first direction F1, the width k1 of the first light shielding portion 22a is greater than the width k2 of the second light shielding portion 22b. In the first direction F1, the first light shielding portion 22a and the second light shielding portion 22b are alternately arranged. In the second direction F2, the first light shielding portion 22a and the second light shielding portion 22b are alternately connected.

[0103] Secondly, the wider first light shielding portion 22a and the narrower second light shielding portion 22b are alternately connected in the second direction F2, so that the edge of the second light shielding strip 222 in the second direction F2 is non-linear, reducing the risk of vertical stripes on the display panel 100. Optionally, both side edges of the second light shielding strip 222 in the second direction F2 are non-linear, so as to further reduce the risk of vertical stripes on the display panel 100.

[0104] In addition, the wider first light shielding portions 22 a and the narrower second light shielding portions 22 b are alternately arranged in the first direction F1 and the second direction F2 , thereby improving display uniformity.

[0105] Combination Figure 3 and Figure 6 In the display panel 100 viewed from a top view, the first light shielding strip 221 covers the scan line 121, the second wiring portion a2 and the fifth wiring portion b2. The first light shielding portion 22a covers the portion of the data line group 122 between two adjacent pixel electrode groups 131 in the first direction F1. The second light shielding portion 22b covers the area between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131. The second light shielding portion 22b also covers the via 14b.

[0106] It should be noted that the first light-shielding portion 22a covers the portion of the data line group 122 between two adjacent groups of pixel electrode groups 131 in the first direction F1, which can be: the first light-shielding portion 22a of the odd rows covers the first wiring portion a1 and the fourth wiring portion b1, and the first light-shielding portion 22a of the even rows covers the third wiring portion a3 and the sixth wiring portion b3.

[0107] Secondly, because the data line group 122 is disposed between two adjacent pixel electrode groups 131 in the first direction F1, the distance between adjacent pixel electrode groups 131 is large, while the distance between two pixel electrodes in the same pixel electrode group 131 is small. Therefore, based on the consideration of the maximum aperture ratio, the width k1 of the first light shielding portion 22a is greater than the width k2 of the second light shielding portion 22b. Furthermore, based on the fact that the width k1 of the first light shielding portion 22a is greater than the width k2 of the second light shielding portion 22b, the edge of the second light shielding strip 222 in the second direction F2 is non-linear, thereby reducing the risk of vertical stripes on the display panel 100 and improving the uniformity of display.

[0108] In some embodiments of the present application, in the first direction F1, the first light shielding portion 22a is connected to the third light shielding portion 22c on both sides thereof. In the display panel 100 in a top view, the first light shielding portion 22a and the third light shielding portions 22c on both sides thereof as a whole cover a spacer 17 .

[0109] It can be understood that the first light shielding portion 22a covers the middle area of ​​the spacer 17, and the third light shielding portion 22c covers the two side areas of the spacer 17, so that the first light shielding portion 22a and the third light shielding portion 22c cover the entire spacer 17. Secondly, based on the connection of the third light shielding portion 22c to the two sides of the first light shielding portion 22a, the edge of the second light shielding strip 222 in the second direction F2 is more uneven, reducing the risk of vertical lines on the display panel 100.

[0110] Figure 7 It is shown that Figure 1 Another enlarged schematic view of the M portion in FIG. Figure 8 is based on Figure 7 Schematic diagram of the structure of the black matrix layer 22.

[0111] exist Figure 7 and Figure 8 In the present invention, parts different from those of the above-described embodiment will be described to avoid redundancy.

[0112] Reference Figure 7 and Figure 8 The common wiring 124 and the spacer 17 are arranged between the first pixel row p1 and the second pixel row p2.

[0113] In the display panel 100 viewed from a top view, some of the spacers 17 near the scan line 121 partially overlap with the common wiring 124, and the via 14b at least partially overlaps with the common wiring 124. The first light shielding strip 221 also covers the common wiring 124, and the first light shielding strip 221 also covers at least part of the via 14b.

[0114] It is understandable that the aperture ratio can be improved by placing the common wiring 124 adjacent to the scan line 121. Optionally, in some embodiments, the common wiring 124 can also be placed to at least partially overlap with the second wiring portion a2 and the fifth wiring portion b2 to improve the aperture ratio.

[0115] Fig. 9 It is shown that Figure 1 Another enlarged schematic view of the M portion in FIG. Fig.10 is based on Fig. 9 Schematic diagram of the structure of the black matrix layer 22.

[0116] exist Fig. 9 and Fig.10 In the present invention, parts different from those of the above-described embodiment will be described to avoid redundancy.

[0117] Reference Fig. 9 and Fig.10 In some embodiments of the present application, the common wiring 124 and the spacer 17 are arranged between the first pixel row p1 and the second pixel row p2.

[0118] In the display panel 100 in a top view, at least one of the common wiring 124 , the scan line 121 and the data line group 122 is partially overlapped with the spacer 17 , and the spacer 17 is disposed at the intersection of the first shading strip 221 and the second shading strip 222 .

[0119] It can be understood that the spacer 17 is disposed between the first pixel row p1 and the second pixel row p2 and partially overlaps with the wiring of the array substrate 10 , which reduces the light-transmitting area occupied by the spacer 17 , thereby improving the aperture ratio.

[0120] The spacer 17 is disposed between the second wiring portion a2 and the fifth wiring portion b2 , and partially overlaps the common wiring 124 , and also partially overlaps the data line group 122 .

[0121] In some embodiments, the spacer 17 that is farther away from the thin film transistor group 12c can also be set to partially overlap with the scan line 121, so that the spacer 17 that is farther away from the thin film transistor group 12c is completely set in the layout area between the scan line 121 and the common wiring 124, avoiding the spacer 17 from occupying additional layout area to improve the aperture ratio.

[0122] In some embodiments, the common wiring 124 may also be disposed to at least partially overlap with the second wiring portion a2 and the fifth wiring portion b2 to improve the aperture ratio.

[0123] Optionally, in some embodiments of the present application, a third light shielding portion 22c is connected to both sides of the intersection of the first light shielding strip 221 and the second light shielding strip 222. In the display panel 100 in a top view, the third light shielding portion 22c and the first light shielding strip 221 and the second light shielding strip 222 respectively connected to the third light shielding portion 22c are covered as a whole with a spacer 17.

[0124] The spacers 17 include first spacers 171 and second spacers 172 . The first spacers 171 and the second spacers 172 are alternately arranged along the first direction F1 , and the first spacers 171 and the second spacers 172 are alternately arranged along the second direction F2 .

[0125] The first spacer 171 is close to the thin film transistor group 12c, and the second spacer 172 is far away from the thin film transistor group 12c. Part of the second spacer 172 is arranged between the first wiring part a1 and the fourth wiring part b1 and partially overlaps with the first wiring part a1 and the fourth wiring part b1. Part of the second spacer 172 is arranged between the third wiring part a3 and the sixth wiring part b3 and partially overlaps with the third wiring part a3 and the sixth wiring part b3 to improve the aperture ratio.

[0126] Fig.11 It is shown that Figure 1 Another enlarged schematic view of the M portion in FIG. Fig.12 It is shown that Fig.11 Schematic diagram of the structure of the common electrode 141.

[0127] Fig.11 and Fig.12 The embodiment shown in Fig. 9 and Fig.10 The difference between the embodiment shown in FIG. 1 and FIG. 2 is that each pixel region 1 a is a dual-pixel domain, and the first pixel electrode 13 a and the second pixel electrode 13 b correspond to one pixel domain respectively.

[0128] exist Fig.11 and Fig.12 In the embodiment, the dual pixel domain includes a first domain c1 and a second domain c2. The first domain c1 corresponds to the first pixel electrode 13a, and the second domain c2 corresponds to the second pixel electrode 13b. The first domain c1 and the second domain c2 are arranged along the first direction F1 and the second direction F2.

[0129] The extending direction of the slits 14a intersects with the alignment direction (first direction F1) of the alignment film 15. In the first domain c1, the plurality of slits 14a extend along the fourth direction F4. In the second domain c2, the plurality of slits 14a extend along the fifth direction F5.

[0130] The first pixel electrode 13a and the second pixel electrode 13b are both configured in a single-domain region, and the middle dark lines of the dual-domain pixel electrode are removed, thereby further improving the aperture ratio and light transmittance.

[0131] In some embodiments of the present application, the slit 14a pattern of the first domain c1 and the slit 14a pattern of the second domain c2 are arranged axially symmetrically to each other to improve the brightness uniformity at a horizontal viewing angle.

[0132] Secondly, the first domain c1 and the second domain c2 are arranged along the first direction F1 and the second direction F2, so that four adjacent pixel electrodes are arranged opposite to each other in pairs to form a pixel overlapping unit, so that the pixel repeating unit has four pixel domains, thereby expanding the viewing angle of the display panel 100.

[0133] Please refer to Fig.13 , Fig.13 FIG. 1 is a schematic diagram of the structure of a display device 1000 according to an embodiment of the present application. Accordingly, an embodiment of the present application further provides a display device 1000, which includes the display panel 100 according to any one of the above embodiments.

[0134] It should be noted that the structure of the display panel 100 of the display device 1000 of the embodiment of the present application is similar to or the same as the structure of the display panel 100 of the above-mentioned embodiments. Figures 1 to 12 The relevant explanation will not be repeated here.

[0135] Optionally, the display device 1000 can be applied to and used in various products, including, for example, televisions, notebook computers, monitors, billboards, Internet of Things devices, and portable electronic devices including mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players, navigation and ultra-mobile personal computers.

[0136] In addition, the display device 1000 according to some embodiments may be applied to a wearable device and may be used in a wearable device, including a smart watch, a watch phone, a glasses-type display, and a head-mounted display (HMD). In addition, according to some embodiments, the display device 1000 may be applied to an instrument panel for a car, a display screen in a central dashboard or a central information display (CID) arranged on a dashboard for a car, an interior mirror display replacing a side mirror of a car, and a display of an entertainment system arranged on the back of a front seat for rear seat passengers in a car.

[0137] The display device 1000 of the embodiment of the present application adopts a data line group 122 layout, so that there is no data line between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131, which greatly reduces the distance between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131. Although a data line is added between the pixel electrode groups 131, the smaller distance between the first data line 12a and the second data line 12b reduces the wiring area in the first direction F1 to improve the aperture ratio.

[0138] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, comprising an array substrate and an opposing substrate arranged opposite to the array substrate, characterized in that: The array substrate comprises: A plurality of scan lines and a plurality of data line groups, wherein the plurality of data line groups are arranged along a first direction, the scan lines extend along the first direction, and the plurality of scan lines are arranged along a second direction intersecting the first direction; the plurality of scan lines and the plurality of data line groups are intersected to form a plurality of pixel regions; and A plurality of pixel electrode groups, one of the pixel electrode groups is correspondingly arranged in one of the pixel regions, the plurality of pixel electrode groups are arranged along the first direction to form pixel rows, the pixel rows include a first pixel row and a second pixel row, the first pixel row and the second pixel row are arranged along the second direction; in the second direction, one pixel electrode group of the first pixel row is correspondingly arranged between two adjacent pixel electrode groups of the second pixel row; Among them, each of the data line groups includes a first data line and a second data line, each of the pixel electrode groups includes a first pixel electrode and a second pixel electrode, in the first direction, the first pixel electrodes and the second pixel electrodes are alternately arranged, the first data lines and the second data lines are alternately arranged, the first data line connects the second pixel electrode of the first pixel row and the first pixel electrode of the second pixel row, and the second data line connects the first pixel electrode of the first pixel row and the second pixel electrode of the second pixel row.

2. The display panel according to claim 1, characterized in that: The first data line includes a first routing portion, a second routing portion, and a third routing portion, the first routing portion is correspondingly arranged in the first pixel row, the third routing portion is correspondingly arranged in the second pixel row, the second routing portion is correspondingly arranged between the first pixel row and the second pixel row and connected to the first routing portion and the third routing portion, the second data line includes a fourth routing portion, a fifth routing portion, and a sixth routing portion, the fourth routing portion is correspondingly arranged in the first pixel row, the sixth routing portion is correspondingly arranged in the second pixel row, and the fifth routing portion is correspondingly arranged between the first pixel row and the second pixel row and connected to the fourth routing portion and the sixth routing portion; The first wiring portion is connected to the second pixel electrode of the first pixel row, the third wiring portion is connected to the first pixel electrode of the second pixel row, the fourth wiring portion is connected to the first pixel electrode of the first pixel row, and the sixth wiring portion is connected to the second pixel electrode of the second pixel row; In the first direction, the second routing portion is located at one side of the fifth routing portion, and in the second direction, the second routing portion and the fifth routing portion are arranged non-overlappingly.

3. The display panel according to claim 2, characterized in that: The first routing portion, the third routing portion, the fourth routing portion and the sixth routing portion all extend along the second direction, and the second routing portion and the fifth routing portion all extend along the first direction; In the first direction, the second routing portion and the fifth routing portion are aligned.

4. The display panel according to claim 3, characterized in that: The counter substrate comprises a black matrix layer, the black matrix layer comprises a first light shielding strip and a second light shielding strip, the first light shielding strip extends along the first direction, the second light shielding strip extends along the second direction, a plurality of the first light shielding strips and a plurality of the second light shielding strips are cross-connected to form a plurality of openings, some of the openings are facing the first pixel electrode, and another part of the openings are facing the second pixel electrode; The second light shielding strip includes a first light shielding portion and a second light shielding portion. In the first direction, the width of the first light shielding portion is greater than the width of the second light shielding portion. In the first direction, the first light shielding portion and the second light shielding portion are alternately arranged. In the second direction, the first light shielding portion and the second light shielding portion are alternately connected. In the display panel viewed from a top-down perspective, the first shading strip covers the scan line, the second routing portion and the fifth routing portion, the first shading portion covers a portion of the data line group between two adjacent groups of pixel electrode groups in the first direction, and the second shading portion covers an area between the first pixel electrode and the second pixel electrode in the pixel electrode group.

5. The display panel according to claim 4, characterized in that: The array substrate further comprises a plurality of thin film transistor groups, wherein the thin film transistor groups are arranged between two adjacent pixel electrode groups and located in a corner area of ​​the pixel electrode groups, each of the thin film transistor groups comprises a first thin film transistor and a second thin film transistor, a control end of the first thin film transistor and a control end of the second thin film transistor are connected to the scan line, an input end of the first thin film transistor is connected to the first data line, an input end of the second thin film transistor is connected to the second data line, and in the first pixel row, an output end of the first thin film transistor is connected to the second pixel electrode, and an output end of the second thin film transistor is connected to the first pixel electrode; In the second pixel row, the output end of the first thin film transistor is connected to the first pixel electrode, and the output end of the second thin film transistor is connected to the second pixel electrode; Among them, the first thin film transistors and the second thin film transistors are alternately arranged in rows along the first direction; in each of the thin film transistor groups, the first thin film transistor is arranged on a side of the first data line away from the second data line, and the second thin film transistor is arranged on a side of the second data line away from the first data line.

6. The display panel according to claim 5, characterized in that: The display panel further includes a plurality of spacers, the array substrate includes a common wiring extending along the first direction, and the common wiring and the spacers are arranged between the first pixel row and the second pixel row; In the display panel viewed from a top view, at least one of the common wiring, the scan line and the data line group is partially overlapped with the spacer, and the spacer is arranged at the intersection of the first light shielding strip and the second light shielding strip.

7. The display panel according to claim 6, characterized in that: A third shading portion is connected to both sides of the intersection of the first shading strip and the second shading strip; in the display panel viewed from a top view, the third shading portion and the portions of the first shading strip and the second shading strip respectively connected to the third shading portion cover the spacer as a whole.

8. The display panel according to claim 7, characterized in that: Each of the pixel regions is a dual-pixel domain, and the first pixel electrode and the second pixel electrode correspond to one of the pixel domains respectively.

9. The display panel according to claim 5, characterized in that: The display panel further includes a plurality of spacers, wherein the spacers are adjacent to the scan lines. In the display panel viewed from a top view, in the first direction, the first data line and the second data line in the same data line group respectively overlap with a portion of the same spacer.

10. The display panel according to claim 9, characterized in that: Each of the pixel regions is a four-pixel domain region, and the four pixel domain regions are arranged in a matrix along the first direction and the second direction, and in the second direction, the liquid crystals of two of the pixel domain regions have different tilt directions; The array substrate further includes a common wiring, which is extended along the first direction. In the display panel viewed from a top view, the common wiring is arranged between two adjacent pixel domains in the second direction.

11. The display panel according to claim 10, characterized in that: The array substrate further includes a common wiring, the common wiring is extended along the first direction, and the common wiring and the spacer are arranged between the first pixel row and the second pixel row; In the display panel viewed from a top view, a portion of the spacers close to the scan line among the plurality of spacers partially overlaps with the common wiring, and the first light shielding strip covers the common wiring.

12. The display panel according to claim 9, characterized in that: In the first direction, the third light shielding parts are connected to both sides of the first light shielding part. In the display panel viewed from a top view, the first light shielding part and the third light shielding parts on both sides thereof cover one of the spacers as a whole.

13. The display panel according to any one of claims 6 to 12, characterized in that: The spacer is formed on the opposite substrate, and in the display panel viewed from a top view, the spacer is located outside the thin film transistor group.

14. The display panel according to any one of claims 6 to 12, characterized in that: The spacers are formed on the counter substrate, the array substrate comprises an alignment film, and an alignment direction of the alignment film is parallel to the first direction.

15. The display panel according to claim 14, characterized in that: The plurality of pixel electrode groups are arranged in the same layer to form a pixel electrode layer, the array substrate further comprises a common electrode layer connected to the common wiring, the pixel electrode layer and the common electrode layer are arranged in different layers, the common electrode layer comprises a plurality of common electrodes, and one of the common electrodes is arranged in one of the pixel regions; in the display panel viewed from a top view, one of the common electrodes overlaps with a first pixel electrode and a second pixel electrode of the same pixel electrode group at the same time; The pixel electrode group and the one of the common electrodes that is closer to the opposing substrate are provided with slits, and in the pixel electrode group of the display panel viewed from a top view, a pattern composed of all the slits in the first pixel electrodes and a pattern composed of all the slits in the second pixel electrodes are axially symmetrical patterns to each other.

16. The display panel according to any one of claims 5 to 12, characterized in that: In the second direction, the first pixel electrodes and the second pixel electrodes are alternately arranged in pixel columns, and a plurality of the pixel columns are arranged along the first direction, wherein in the same picture frame, the voltage polarity connected to the first data line is opposite to the voltage polarity connected to the second data line.

17. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-16.

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