LED receiving card data rearrangement method, device and equipment

Abstract

The present application provides a method, device and equipment for rearranging data of an LED receiving card. In one example, the method for rearranging data of an LED receiving card includes: for any data group corresponding to an LED display screen, a cache address mapping table is generated according to the type, physical arrangement and routing of each driver integrated circuit IC in the data group, and the row cache size of the LED receiving card corresponding to the data group, and a mapping unit mapping table and a reordering address mapping table are respectively generated according to the cache address mapping table, and a row and column extraction configuration table, a cache address mapping table, a mapping unit mapping table and a reordering address mapping table are sent to the LED receiving card corresponding to the data group, so that the LED receiving card rearranges the received input data according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table and the reordering address mapping table, which can effectively improve the memory reading and writing efficiency.

Description

Technical Field

[0001] The present application relates to the field of LED display technology, and in particular to a method, device and equipment for rearranging data of an LED receiving card. Background Art

[0002] LED (Light Emitting Diode) receiving card is an electronic device used to receive and process LED display screen signals. It is mainly responsible for transmitting control signals from the transmitter to the LED display screen to ensure the correct display of image and video content.

[0003] The input pixels of the LED receiving card are input in a raster scan order, but when outputting, it is usually necessary to break up the positions or bits of the input pixels.

[0004] For example, a data group of an LED display screen usually includes multiple driver ICs (Integrated Circuits), and multiple driver ICs in the same data group usually need to output pixels synchronously. For example, in the process of pixel / bit output, multiple driver ICs in the same data group need to synchronously output pixels / bits at the same position (such as the upper left corner).

[0005] Therefore, the LED receiving card needs to rearrange the input data to improve the memory efficiency when the data is output.

[0006] How to rearrange data on LED receiving cards has become a technical problem that needs to be solved urgently. Summary of the invention

[0007] In view of this, the present application provides a method, device and equipment for rearranging data of an LED receiving card.

[0008] Specifically, the present application is implemented through the following technical solutions:

[0009] According to a first aspect of an embodiment of the present application, a method for rearranging data of an LED receiving card is provided, comprising:

[0010] For any data group corresponding to the LED display screen, a cache address mapping table is generated according to the type, physical arrangement, and routing of each driver integrated circuit IC in the data group, and the row cache size of the LED receiving card corresponding to the data group; wherein the cache address mapping table is used to record the mapping relationship between the driver IC display coordinates and the cache address;

[0011] Generate a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data; wherein the mapping unit mapping table is used to record the mapping relationship between the cache address and the mapping address, and the input data is written into the memory according to the mapping address;

[0012] Generate a reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data; wherein the reordering address mapping table is used to record the mapping relationship between the mapping address and the reordering address, and the data in the memory is written into the reordering cache according to the reordering address;

[0013] The row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table are sent to the LED receiving card corresponding to the data group, so that the LED receiving card rearranges the received input data according to the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table; wherein the row-column extraction configuration table is used to realize the conversion between the image coordinates of the input pixels and the display coordinates of the driver IC.

[0014] According to a second aspect of an embodiment of the present application, a method for rearranging data of an LED receiving card is provided, comprising:

[0015] Obtaining a row-and-column extraction configuration table, a cache address mapping table, a mapping unit mapping table, and a reordering address mapping table; wherein the row-and-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table are generated according to the method described in the first aspect;

[0016] When an input image is received, data in the input image are output to a corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table.

[0017] According to a third aspect of an embodiment of the present application, there is provided a device for rearranging data of an LED receiving card, comprising:

[0018] A generating unit is used to generate a cache address mapping table for any data group corresponding to the LED display screen according to the type, physical arrangement and routing of each driver integrated circuit IC in the data group, and the row cache size of the LED receiving card corresponding to the data group; wherein the cache address mapping table is used to record the mapping relationship between the display coordinates of the driver IC and the cache address;

[0019] The generating unit is further used to generate a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data; wherein the mapping unit mapping table is used to record the mapping relationship between the cache address and the mapping address, and the input data is written into the memory according to the mapping address;

[0020] The generating unit is further used to generate a reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data; wherein the reordering address mapping table is used to record the mapping relationship between the mapping address and the reordering address, and the data in the memory is written into the reordering cache according to the reordering address;

[0021] A sending unit is used to send the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table to the LED receiving card corresponding to the data group, so that the LED receiving card rearranges the received input data according to the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table; wherein the row-column extraction configuration table is used to realize the conversion between the image coordinates of the input pixels and the display coordinates of the driver IC.

[0022] According to a fourth aspect of an embodiment of the present application, there is provided a device for rearranging data of an LED receiving card, comprising:

[0023] An acquisition unit, used to acquire a row-column extraction configuration table, a cache address mapping table, a mapping unit mapping table, and a reordering address mapping table; wherein the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table are generated according to the method provided in the first aspect;

[0024] The processing unit is used to output each data in the input image to the corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table when receiving the input image.

[0025] According to a fifth aspect of an embodiment of the present application, there is provided an electronic device, including a processor and a memory, wherein:

[0026] Memory, used to store computer programs;

[0027] The processor is used to implement the method provided by the first aspect or the second aspect when executing the program stored in the memory.

[0028] According to a sixth aspect of an embodiment of the present application, a computer program product is provided, wherein a computer program is stored in the computer program product, and when the computer program is executed by a processor, the method provided in the first aspect or the second aspect is implemented.

[0029] The data rearrangement method of the LED receiving card of the embodiment of the present application generates a cache address mapping table for any data group corresponding to the LED display screen according to the type, physical arrangement and routing of each driver IC in the data group, and the row cache size of the LED receiving card corresponding to the data group; generates a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data, and generates a reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data, and then sends the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table to the LED receiving card corresponding to the data group, so that the LED receiving card rearranges the received input data according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table. By introducing the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table, the image data of the entire receiving card can be retrieved from the memory at one time, reducing the number of memory read and write times and improving the memory read and write efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic flow chart of a method for rearranging data of an LED receiving card shown as an exemplary embodiment of the present application;

[0031] Figure 2 A schematic flow chart of a method for rearranging data of an LED receiving card shown as an exemplary embodiment of the present application;

[0032] Figure 3A and Figure 3B A schematic diagram of a scanning sequence of a driver IC is shown as an exemplary embodiment of the present application;

[0033] Figure 4 A schematic diagram of a driver IC displaying coordinates according to an exemplary embodiment of the present application;

[0034] Figure 5A A schematic diagram of MU mapping in a non-transposition scenario in a reordering situation is shown as an exemplary embodiment of the present application;

[0035] Figure 5B A schematic diagram of MU mapping in a transposition scenario in a reordering situation is shown as an exemplary embodiment of the present application;

[0036] Figure 6 This is a schematic diagram of MU mapping in a bit separation situation shown in an exemplary embodiment of the present application;

[0037] Figure 7 A schematic diagram of SU mapping in a transposition case is shown as an exemplary embodiment of the present application;

[0038] Figure 8 A schematic diagram of data arrangement of a mapping unit is shown as an exemplary embodiment of the present application;

[0039] Fig. 9 A schematic diagram of reordering is shown for an exemplary embodiment of the present application;

[0040] Fig.10 A schematic diagram of coordinate conversion in a case of extracting rows and columns is shown as an exemplary embodiment of the present application;

[0041] Fig.11 A schematic diagram of a complete address mapping process is shown for an exemplary embodiment of the present application;

[0042] Fig.12 This is a structural schematic diagram of a data rearrangement device for an LED receiving card shown as an exemplary embodiment of the present application;

[0043] Fig.13 This is a structural schematic diagram of a data rearrangement device for an LED receiving card shown as an exemplary embodiment of the present application;

[0044] Fig.14 The figure is a schematic diagram of the hardware structure of an electronic device shown as an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0047] In order to enable those skilled in the art to better understand the technical solution provided in the embodiments of the present application, the relevant implementation of video encoding in the embodiments of the present application is first described below.

[0048] 1. Technical terms

[0049] 1. Transposition: A PCB (Printed Circuit Board) design scheme where the column driver IC is responsible for the image row and the row driver IC is responsible for the image column display.

[0050] 2. Scanning block: A set of serially connected column driver ICs corresponding to the displayed image.

[0051] Exemplarily, one scanning block may correspond to one data group.

[0052] 3. Row scan: The scanning block opens one row at a time, and each row lights up alternately. The number of rows in each data group is called the row scan.

[0053] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application are further described in detail below with reference to the accompanying drawings.

[0054] It should be noted that the serial numbers of the steps in the embodiments of the present application do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0055] See also Figure 1 , is a flow chart of a method for rearranging data of an LED receiving card provided in an embodiment of the present application, wherein the data rearrangement of the LED receiving card can be applied to a host computer, such as Figure 1 As shown, the LED receiving card data rearrangement method may include the following steps:

[0056] Step S100, for any data group corresponding to the LED display screen, generate a cache address mapping table based on the type, physical arrangement, and routing method of each driver IC in the data group, as well as the row cache size of the LED receiving card corresponding to the data group; wherein the cache address mapping table is used to record the mapping relationship between the driver IC display coordinates and the cache address.

[0057] In an embodiment of the present application, in order to improve the memory efficiency of the LED receiving card in processing LED display screen signals, the host computer can determine the output order of each pixel / bit on each driver IC in the same data group based on the type, physical arrangement, and routing method of each driver IC in the data group corresponding to the LED display screen.

[0058] Exemplarily, the type of driver IC may include reordering or bit separation.

[0059] Among them, for the reordering type of driver ICs, the pixels at the same position (starting from the upper left corner) of each driver IC need to be output synchronously in sequence according to the scanning order of each driver IC.

[0060] For a bit-separated type of driver IC, it is necessary to synchronously output the bits at the same position of each driver IC in sequence according to the scanning order of each driver IC (starting from the first bit of each pixel in the first row).

[0061] For example, assuming that the data group includes two driver ICs in the same row, and the type of the driver ICs is bit separation, the first bit of each pixel in the first row of the two driver ICs can be synchronously output first, and then the first bit of each pixel in the second row of the two driver ICs can be synchronously output, ..., the second bit of each pixel in the first row of the two driver ICs can be synchronously output, the second bit of each pixel in the second row of the two driver ICs can be synchronously output, and so on, and finally the last bit of each pixel in the last row of the two driver ICs can be synchronously output.

[0062] Exemplarily, the physical arrangement of the driver ICs may include the driver ICs including several rows and columns.

[0063] The wiring pattern of the driver ICs may include the connection relationship between the driver ICs, thereby affecting the scanning order of the driver ICs.

[0064] Exemplarily, the routing method of the driver IC includes connecting the driver IC from left to right and from top to bottom based on the physical arrangement, and the corresponding scanning order of the driver IC is from left to right and from top to bottom. This scanning order can be called a reordering method.

[0065] The routing method of the driver IC also includes connecting the driver IC from top to bottom and from left to right based on the physical arrangement. The corresponding scanning order of the driver IC is from top to bottom and from left to right. This scanning order can be called a transposition method (or rotation method).

[0066] For example, the driver IC in the data group includes m rows and n columns (m≥1, n≥1, m and n are not 1 at the same time), then the driver IC in the 1st row and 1st column in the data group is connected to the driver IC in the 1st row and 2nd column,…, the driver IC in the 1st row and n-1th column is connected to the driver IC in the 1st row and nth column, the driver IC in the 1st row and nth column is connected to the driver IC in the 2nd row and 1st column,…, the driver IC in the m-1th row and nth column is connected to the driver IC in the mth column,…, the driver IC in the mth row and n-1th column is connected to the driver IC in the mth row and nth column, and the corresponding scanning order of the driver ICs is the reordering method. In the data group, the driver IC in the 1st row and 1st column is connected to the driver IC in the 2nd row and 1st column,…, the driver IC in the m-1th row and 1st column is connected to the driver IC in the mth row and 1st column, the driver IC in the mth row and 1st column is connected to the driver IC in the 1st row and 2nd column,…, the driver IC in the mth row and n-1th column is connected to the driver IC in the 1st row and nth column,…, the driver IC in the m-1th row and nth column is connected to the driver IC in the mth row and nth column, and the corresponding scanning order of the driver ICs is a transposed method.

[0067] In which, when m and n are both greater than 1, the above scanning order can also be called a zigzag method.

[0068] by Figure 3A and Figure 3B As shown, the scanning order of the driving IC may include from left to right, from top to bottom; and, from top to bottom, from left to right.

[0069] in, Figure 3A The scanning order can be called the reordering method; Figure 3B The scanning order can be called the transposition method (or rotation method).

[0070] In addition, if Figure 3A or Figure 3B As shown, in the case where there are multiple rows / columns of driver ICs, the scanning order of the driver ICs can also be called a broken line.

[0071] In an embodiment of the present application, when there are multiple driver ICs in a data group, the pixels / bits in a single driver IC will not be output in the order in which they are in the driver IC. Instead, the actual output order of the pixels / bits in the driver IC needs to be determined based on the type, physical arrangement and routing method of each driver IC in the data group.

[0072] Taking a reordered type of driver IC as an example, assuming that the data group includes m rows and n columns of driver ICs, then in the actual pixel output process, for any driver IC, the pixels in the driver IC will not be output continuously from left to right and from top to bottom, but need to be output at intervals with the pixels in other driver ICs in the same data group.

[0073] For example, assuming that m and n are both greater than 1, and the scanning order of the driver IC is a reordering method, the actual output order of the pixels in the driver IC is: the pixel in the 1st row and 1st column in the driver IC in the 1st row and 1st column, the pixel in the 1st row and 1st column in the driver IC in the 1st row and 2nd column,… the pixel in the 1st row and 1st column in the driver IC in the 1st row and nth column, the pixel in the 1st row and 1st column in the driver IC in the 2nd row and 1st column,… the pixel in the 1st row and 1st column in the driver IC in the mth row and nth column, the pixel in the 1st row and 2nd column in the driver IC in the 1st row and 1st column…, and so on.

[0074] For example, Figure 4Taking the physical arrangement of the driver IC shown (2 rows and 2 columns) as an example, assuming that driver ICs 1 to 4 are connected in series in sequence, and the type of driver ICs 1 to 4 is the reordering type, the scanning order of driver ICs 1 to 4 is to scan driver ICs 1 to 4 in sequence. For the pixels input to driver ICs 1 to 4, the pixels at the upper left corner of driver ICs 1 to 4 can be input to driver ICs 1 to 4 in sequence, and then the pixels at the 1st row and 2nd column of driver ICs can be input to driver ICs 1 to 4 in sequence, that is, the optimal order of the pixels input to driver ICs 1 to 4 in the cache is: (1, 0, 0) (pixels at the 1st row and 1st column of driver IC1), (2, 0, 0), (3, 0, 0), (4, 0, 0), (1, 0, 1), (2, 0, 1), and so on.

[0075] In addition, consider that the row buffer size of the LED receiving card is usually smaller than the number of pixel rows of a single driver IC.

[0076] For example, the row buffer size of an LED receiving card is usually 4 rows of buffer, while the number of rows of a single driver IC is usually greater than 4 rows.

[0077] Therefore, the pixels to be displayed in each driver IC cannot usually be obtained in the order in which they are actually output.

[0078] Still taking the above example, assuming that the row cache of the LED interface card is k rows, and the number of rows of a single driver IC is i rows, i>k, although the actual output order of the first row of pixels of the driver IC of the second row will be earlier than the second row of pixels of the driver IC of the first row, due to the limitation of the row cache size, during the data reading process, continuous k rows of pixels of the input image are obtained each time, and thus, the first row of pixels of the first row driver and the first row of pixels of the second row driver cannot be obtained at the same time.

[0079] For example, in the process of acquiring the first row of pixels of the first row of driver ICs, the acquired pixels are the first k (k<i) rows of pixels of the first row of driver ICs, and the acquired pixels do not include the first row of pixels of the second row of driver ICs, that is, the second row of pixels of the first row of driver ICs will be acquired before the first row of pixels of the second row of driver ICs, and accordingly, the second row of pixels of the first row of driver ICs will be cached before the first row of pixels of the second row of driver ICs.

[0080] Accordingly, the acquired k consecutive rows of pixels can be cached in the actual output order according to the row cache size of the LED receiving card.

[0081] Taking the driver IC scanning order as the reordering method as an example, for the acquired k consecutive rows of pixels, the actual output order is the pixels of the 1st row and 1st column of the 1st driver IC in the same row, the pixels of the 1st row and 1st column of the 2nd driver IC, … the pixels of the 1st row and 1st column of the nth driver IC (the data group includes m rows and n columns of driver ICs), the pixels of the 1st row and 2nd column of the 1st driver IC, the pixels of the 1st row and 2nd column of the 2nd driver IC, …, the pixels of the 1st row and jth column of the nth driver IC (the number of columns of a single driver IC is j), the pixels of the 2nd row and 1st column of the 1st driver IC… and so on.

[0082] For example, Figure 4 Taking the scenario shown as an example, assuming that the driver IC type is a reordering type and the row cache size is 4 row caches, when processing the 1st to 4th row pixels of the input image, the row cache stores the first 4 rows of pixels of driver IC1 and driver IC2. In this case, the above pixels (3, 0, 0) and (4, 0, 0) cannot be obtained. Therefore, the order of the pixels actually obtained in the row cache can be: (1, 0, 0), (2, 0, 0), (1, 0, 1), (2, 0, 1), (1, 0, 2), (2, 0, 2)... and so on.

[0083] For example, considering that in the process of cache reading and writing, if reading and writing are performed in units of single pixels each time, it will be too cumbersome and inefficient, therefore, in the process of caching input data, multiple consecutive pixels in the driver IC can be cached as a whole for reading and writing to improve processing efficiency.

[0084] Step S110, generating a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data; wherein the mapping unit mapping table is used to record the mapping relationship between the cache address and the mapping address, and the input data is written into the memory according to the mapping address.

[0085] In the embodiment of the present application, based on the relevant description in step S100, it can be known that there may be a difference between the order of pixels in the cache and the actual output order of the pixels. Therefore, for the data in the cache, it is necessary to map it according to the actual output order of the data, determine the mapping address of each data, and write the data into the memory according to the mapping address.

[0086] Exemplarily, in the process of writing data in the cache into the memory, the mapping offset can be determined for the data in the cache based on its actual output order to ensure that when each pixel is written into the memory according to the mapping address, the address order of the pixels in the memory is closer to the actual output order.

[0087] Exemplarily, for any data in the cache, its mapping offset can be determined based on the data and the number of data intervals between the adjacent previous data of the data in the cache in the actual output order.

[0088] For example, assuming that the data group includes m rows and n columns of driver ICs, the type of the driver ICs is a reordering type, the scanning order of the driver ICs is a reordering method, and the pixels in the 1st row and 2nd column of the driver IC in the 1st row and 1st column and the pixels in the 1st row and 1st column of the driver IC in the 1st row and 1st column are stored adjacent to each other in the cache, then relative to the pixels in the 1st row and 1st column of the driver IC in the 1st row and 1st column, the mapping offset of the pixels in the 1st row and 2nd column of the driver IC in the 1st row and 1st column is (m-1)*n.

[0089] Still with the above Figure 4 Taking the scenario shown as an example, assuming that the driver IC type is the reordering type, the pixel in the 1st row and 2nd column of the driver IC (i.e., driver IC1) in the 1st row and 1st column (denoted as (1, 0, 1)) is adjacent to the pixel in the 1st row and 1st column of driver IC2 (denoted as (2, 0, 0)) in the cache, but in the actual output order, this pixel (i.e., (1, 0, 1)) needs to be output after (3, 0, 0) and (4, 0, 0). Therefore, relative to (1, 0, 0), the mapping offset of (1, 0, 1) is 2 ((2-1)*2=2) (i.e., there are 2 pixels between it and (2, 0, 0)).

[0090] Step S120, generating a reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data; wherein the reordering address mapping table is used to record the mapping relationship between the mapping address and the reordering address, and the data in the memory is written into the reordering cache according to the reordering address.

[0091] In the embodiment of the present application, when the mapping address of the input data is determined in the above manner, a reordering address mapping table can be generated according to the actual output order of each data in the memory and the mapping address of each data.

[0092] Exemplarily, the reordering address mapping table is used to sort the input data in the order of driver IC input according to the address of the input data in the memory (ie, the above-mentioned mapping address).

[0093] In addition, considering that in the process of cache / memory reading and writing, if reading and writing are performed in units of single pixels each time, it will be too cumbersome and inefficient, therefore, the number of pixels scanned continuously by the driver IC can be determined based on the scanning order of the driver IC and the row cache size of the LED receiving card.

[0094] by Figure 4Take driver IC1 in the figure as an example, assuming that the scanning order of driver 1 is from left to right and from top to bottom, then when the row cache size is 4 row caches, the maximum number of pixels scanned continuously by the driver IC is 32 (4 rows, 8 pixels per row, 4*8=32).

[0095] Assuming that the scanning order of driver 1 is from top to bottom and from left to right, when the row cache size is 4 row caches, the maximum number of pixels continuously scanned by the driver IC is 4 (ie, the first 4 pixels of the first column).

[0096] Exemplarily, the basic storage unit of the cache may be determined according to the number of pixels continuously scanned by the driver IC and the number of driver ICs in a data group in the horizontal direction.

[0097] Exemplarily, when the input data is written into the memory in the above manner, the data may be reordered according to the actual output order of each data in the memory to determine the address of each data in the reordering cache.

[0098] Exemplarily, the LED receiving card may input each data to the corresponding driver IC in sequence according to the sequence of each data in the reordering buffer (ie, the actual output sequence of each data).

[0099] In some embodiments, the cache address mapping table is generated based on the type, physical arrangement, and routing of each driver IC in the data group, and the row cache size of the LED receiving card corresponding to the data group, including:

[0100] Determine a corresponding basic splicing unit according to the type of each driver IC in the data group and the physical arrangement of each driver IC in the data group; wherein the size of the basic splicing unit is determined according to the number or grouping of driver ICs in the row buffer;

[0101] Determine the scanning order of each driver IC according to the physical arrangement and routing of each driver IC in the data group, and determine the corresponding scanning unit according to the scanning order of each driver IC and the row buffer size of the LED receiving card corresponding to the data group; wherein the size of the scanning unit is determined according to the number of data continuously scanned by a single driver IC;

[0102] Determine a basic storage unit in a cache unit according to the basic splicing unit and the scanning unit;

[0103] According to the scanning sequence of each driver IC and the basic storage unit in the cache unit, the mapping relationship between the driver IC display coordinates and the cache address is determined, and a cache address mapping table is generated.

[0104] Exemplarily, for a bit-separated type driver IC, the size of the basic splicing unit may be the number of data groups in the row buffer.

[0105] For a reordering type of driver IC, the size of the basic splicing unit may be the number of driver ICs in the row buffer.

[0106] For example, assuming that the number of driver ICs in the row cache is 4 (usually the number of driver ICs in the row cache is the number of driver ICs in the horizontal direction), and these driver ICs belong to two data groups, then when the type of the driver IC is a bit separation type, the size of the basic splicing unit is 2; when the type of the driver IC is a reordering type, the size of the basic splicing unit is 4.

[0107] Exemplarily, the size of the scanning unit (SCAN UINT, which may be referred to as SU) may be determined according to the amount of data continuously scanned by a single driver IC.

[0108] Among them, the number of data continuously scanned by a single driver IC is related to the scanning order of the driver IC.

[0109] by Figure 4 Taking the scenario shown as an example, assuming that the driver IC type is reordering, the driver IC is transposed (or rotated), and the driver IC scans from top to bottom and from left to right, then when the row cache is 4 rows, the maximum number of pixels scanned continuously by a single driver IC is 4 (i.e., the first 4 pixels of the first column). In this case, the size of the scanning unit can be any value from 1 to 4.

[0110] Still Figure 4 Taking the scenario shown as an example, assuming that the driver IC type is reordering and the driver IC does not have transposition, the driver IC scans from left to right and from top to bottom. If the row buffer is 4 rows, the maximum number of pixels scanned continuously by a single driver IC is 32 (i.e., the first 4 rows of pixels, 8 pixels per row). In this case, the size of the scanning unit can be any value between 1 and 32.

[0111] The basic storage unit in the cache unit can be determined according to the basic splicing unit and the scanning unit.

[0112] Exemplarily, the size of the basic storage unit may be the product of the size of the basic splicing unit and the size of the scanning unit.

[0113] For example, Figure 5A and Figure 5B For example, assuming that the row cache size is 4 row caches, the number of driver ICs in the row cache is 4, and the type of driver IC is reordering, then:

[0114] like Figure 5A As shown, for the non-transposed scenario, the size of the basic splicing unit (which can be called PU) is 4, and the size of SU can be 1~32 (the maximum value is the number of row cache lines * the width of the driver IC, Figure 5A In the example above, the size of SU is 4, and the size of MU can be 4 to 128.

[0115] like Figure 5B As shown, for the transposition scenario, the size of the PU is 4, and the size of the SU can be 1 to 4 (the maximum value is the number of row cache lines, Figure 5B In the example above, the size of SU is 4, and the size of MU can be 4 to 16.

[0116] For example, Figure 6 Taking the scenario shown as an example, assuming that the physical distribution of the driver IC includes 2 rows and 4 columns with a total of 8 driver ICs, and the driver IC is divided into 2 data groups (the number of data groups in the row cache is 2), and the type of the driver IC is bit separation, then in this example, the basic splicing unit (which can be called PU) size is 2; since the scanning order of the driver IC is from left to right and from top to bottom, in the case of 4-row cache and the driver IC size is 8*8, SU can be any value between 1 and 32. Assuming SU=8, then MU=16.

[0117] Exemplarily, for a scenario where the driver IC type is bit-separated, when the MU is determined in the above manner, the bits of each pixel can be stored separately according to the number of bits of each pixel. For example, the first bit of each pixel in the MU is stored in one area according to the order of the pixels in the MU, and the second bit of the pixel in the MU is stored in another area according to the order of the pixels in the MU, and so on.

[0118] Figure 6 The driver IC is divided into 2 data groups, and the LED receiving card can process the two data groups concurrently, so that the synchronously output data can include the first bit of the 8 pixels in the first row of the first driver IC of the first array (i.e. the first driver IC sorted from left to right), and the first bit of the 8 pixels in the first row of the first driver of the second data group (i.e. the third driver IC sorted from left to right).

[0119] Exemplarily, the mapping relationship between the display coordinates of the driver ICs and the cache addresses may be determined according to the scanning order of each driver IC and the basic storage unit in the cache unit, and a cache address mapping table may be generated.

[0120] Exemplarily, for the same basic storage unit, the data in the basic storage unit are sorted in the cache according to the actual output order, and are arranged continuously in the cache according to the sorting result; wherein, the actual output order of the data in the basic storage unit can be determined according to the scanning order of each driver IC.

[0121] For example, Figure 7 Taking the 4-row 4-column transposed driver IC shown in the figure as an example, assuming that the type of the driver IC is reordering, the size of the driver IC is 4*4, the scanning order is from top to bottom and from left to right, and the row cache size is 4 row caches, then in this example, the basic splicing unit (also known as PU), PU=2, SU size is any value from 1 to 4, assuming SU=4, then MU=8, for the driver IC display coordinates (1,0,0), (2,0,0), (1,1,0), (2,1,0), …, (1,3,0), (2 , 3, 0), the actual output order of each pixel in the MU is (1, 0, 0), (2, 0, 0), (1, 1, 0), (2, 1, 0), …, (1, 3, 0), (2, 3, 0). Therefore, the order of each pixel in the cache in this MU is 0 (the driver IC displays the coordinates of (1, 0, 0)), 1 (the driver IC displays the coordinates of (2, 0, 0)), …, 6 (the driver IC displays the coordinates of (1, 3, 0)), and 7 (the driver IC displays the coordinates of (2, 3, 0)).

[0122] Exemplarily, different basic storage units are sorted in the cache in sequence according to the actual output order of the data in the basic storage units, and are arranged continuously in the cache according to the sorting result.

[0123] For example, assuming that the cache includes data of four MUs (such as Mua, MUb, MUc and MUd), the data in MUa is output first, the data in MUb is output after the data in MUa and before the data in MUc, the data in MUc is output after the data in MUb and before the data in MUd, and the data in MUd is output last, then the four MUs are arranged consecutively in the cache in the order of MUa, MUb, MUc, and MUd.

[0124] Based on the above-mentioned sorting method of data in the same basic splicing unit and the sorting method of different basic splicing units, the sorting method of each data in the cache can be determined, thereby, the cache address of each data can be determined, and then, based on the driver IC display coordinates of each data and the cache address of each data, the mapping relationship between the driver IC display coordinates and the cache address can be determined, and a cache address mapping table can be generated.

[0125] In some embodiments, the above-mentioned generation of the mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data may include:

[0126] Determine the output order of each basic storage unit in the cache according to the actual output order of each data in the cache;

[0127] According to the output sequence of each basic storage unit in the cache, the mapping relationship between the cache address and the mapping address is determined, and a mapping unit mapping table is generated.

[0128] Exemplarily, in the process of determining the mapping address, for the data in the cache unit, the MU (ie, basic storage unit) can be used as the basic unit, and each MU can be mapped and sorted according to the order of the LED screen dots (ie, the actual output order of the MU).

[0129] For example, Figure 8 Take the 8-row 8-column transposed driver IC as an example. The size of the driver IC is 4*4, the scanning order is from top to bottom and from left to right, and the row cache size is 4 row caches. In this example, PU=4, and the SU size is any value from 1 to 4. Assuming SU=4, then MU=16. In the process of writing cache, the order of MU0~MU4 is MU0, MU2, MU1, MU3. In the actual output process, the order of MU0~MU4 is MU0, MU1, MU2, MU3. Therefore, in the process of mapping the data in the cache, for MU2, it is necessary to determine the number of data intervals between it and MU0 according to its actual output order, and determine the mapping offset of MU1 based on the number of data (relative to the mapping offset of MU0, to ensure that its storage position in the memory is after the storage position of MU1).

[0130] In some embodiments, the above-mentioned generation of the reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data may include:

[0131] Reorder the data in the memory according to the actual output order of the data in the memory;

[0132] According to the reordering result of each data in the memory, the mapping relationship between the mapping address and the reordering address is determined, and a reordering address mapping table is generated.

[0133] Exemplarily, when the mapping address of each input data is determined in the above manner, each input data can be written into the memory based on the mapping address of each input data and using MU as a basic storage unit.

[0134] Since the input data in the memory is written in the form of basic storage units, the input data is also sorted in the form of basic storage units in the memory, but in the process of outputting data, the output unit is usually smaller than the write unit (basic storage unit).

[0135] For example, in the process of data output, the output is usually performed in pixels, that is, pixel by pixel, but a basic storage unit includes multiple pixels, and the sorting result in the memory in the form of basic storage units is not consistent with the actual output order of each pixel.

[0136] Accordingly, for each data in the memory, each data in the memory can be reordered according to the actual output order of each data in the memory to determine the reordering result of each data in the memory (the reordering result of each data is consistent with the actual output order of each data), and then, based on the reordering result of each data in the memory, the address of each data in the reordering cache (which can be called the reordering address) is determined, and based on the mapping address of each data and the reordering address of each data, the mapping relationship between the mapping address and the reordering address is determined, and a reordering address mapping table is generated based on the mapping relationship between the mapping address and the reordering address.

[0137] Exemplarily, the data in the memory is reordered according to the reordering mapping table, and the data is reorganized into the actual driver IC input sequence.

[0138] by Figure 8 Take the MU mapping shown in the figure as an example. Figure 8 In the memory, the driver IC is scanned in the order from top to bottom and from left to right. In the memory, each MU is arranged in the order of MU0, MU1, MU2 and MU3. However, in the actual output process, after the first data in MU0 is output, the next data output is not the second data in MU0 (the first data in MU0 and the second data in MU0 are adjacent in the memory), but the first data in MU1. Therefore, the data in the memory needs to be reordered according to the actual output order of each data.

[0139] In the process of reordering the data in the memory, the mapping relationship between the mapping coordinates and the reordering coordinates can be as follows: Fig. 9 shown.

[0140] like Fig. 9 As shown, the first pixel in MU0 (i.e. Fig. 9 The pixel 0 in MU1 (i.e. the pixel in the upper left corner of the driver IC in the upper left corner) is output first, and then the first pixel in MU2 (i.e. Fig. 9 1, which is the pixel in the upper left corner of the driver IC in the lower left corner, and then outputs the second pixel in MU0 (i.e. Fig. 9 2, which is the pixel at the upper left corner of the driver IC in row 1 and column 2), and then outputs the second pixel in MU1 (i.e. Fig. 9 , i.e., the pixel at the upper left corner of the driver IC at the 2nd row and the 2nd column), and so on, to achieve the reordering of the pixels in the memory.

[0141] Step S130, sending the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table to the LED receiving card corresponding to the data group, so that the LED receiving card rearranges the received input data according to the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table; wherein the row-column extraction configuration table is used to record the row-column extraction configuration of the input image relative to the driver IC, and is used to realize the conversion between the image coordinates of the input data and the display coordinates of the driver IC.

[0142] In the embodiment of the present application, due to the reason of row and column extraction, the actual number of output pixels of the driver IC may be greater than the image size in the image coordinate system. Therefore, it is necessary to perform a coordinate system transformation according to the row and column extraction configuration to transform the coordinates of the input image from the original image coordinate system to the driver IC display coordinate system.

[0143] It should be noted that in the row and column extraction configuration, the number of rows and columns can be configured according to actual needs.

[0144] In one example, the entire rows and columns of the driver ICs may be extracted, which may also be referred to as IC extraction (ie, extracting the driver ICs).

[0145] In one example, the row and column extraction configuration table contains row and column extraction flags for each row and column of the entire display area. Each flag is 1 bit in size. Row and column extraction only converts the coordinates of valid pixels and does not supplement invalid pixels.

[0146] Exemplarily, in the process of converting image coordinates to driver IC display coordinates based on the row and column extraction configuration table, in the horizontal direction, the horizontal coordinate of the input data that is located before the extracted column (the horizontal order is from left to right, that is, the position is on the left side of the extracted column) can remain unchanged, and the horizontal coordinate of the input data that is located after the extracted column needs to be adjusted according to the number of extracted columns.

[0147] Similarly, in the vertical direction, the vertical coordinate of the input data that is before the extracted row (the vertical order is from top to bottom, that is, the position is above the extracted row) can remain unchanged, and the vertical coordinate of the input data that is after the extracted row needs to be adjusted according to the number of extracted rows.

[0148] For example, Fig.10 For example, Fig.10 As shown in the figure, when the value of the row / column extraction flag is 1, it is determined that there is a row / column extraction, that is, there is a row extraction in the 4th row and a column extraction in the 3rd column. For a 7*7 input image block, assuming that its pixel coordinates are (0, 0) to (7, 7), and there is a row / column extraction in the 4th row and the 3rd column, when converted to the driver IC display coordinates, it becomes 8*8, where the 4th row and the 3rd column are reinserted rows and columns. In the coordinate conversion process, the pixels before the 4th row and the 3rd column ( Fig.10 The coordinates of the 6 pixels in the upper left corner of the right side remain unchanged), and the remaining pixels need to be transformed. Among them, Fig.10 The horizontal coordinates of the 12 pixels in the upper right corner on the right side need to be increased by 1; the vertical coordinates of the 8 pixels in the lower left corner need to be increased by 1; and the horizontal and vertical coordinates of the 20 pixels in the lower right corner both need to be increased by 1.

[0149] See also Figure 2 , is a flow chart of a method for rearranging data of an LED receiving card provided in an embodiment of the present application, wherein the method for rearranging data of an LED receiving card can be applied to an LED receiving card, such as Figure 2 As shown, the LED receiving card data rearrangement method may include the following steps:

[0150] Step S200, obtaining a row and column extraction configuration table, a cache address mapping table, a mapping unit mapping table, and a reordering address mapping table.

[0151] In the embodiment of the present application, the host computer sends the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the specific implementation of the reordering address mapping table to the LED receiving card. Figure 1 The relevant descriptions in the method flow shown will not be repeated in the embodiments of the present application.

[0152] Step S210: when receiving an input image, output each data in the input image to a corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table.

[0153] In an embodiment of the present application, when the LED obtains the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table, it can complete the transposition, bit separation, reordering, row and column extraction and other functions through a single memory read and write operation based on the obtained row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table, and finally output each data in the input image to the corresponding driver IC.

[0154] In some embodiments, the above-mentioned outputting each pixel in the input image to the corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table may include:

[0155] Determine the display coordinates of the driver IC for each data in the input image according to the row and column extraction configuration table;

[0156] Determine the cache address of each data according to the driver IC display coordinates of each data and the cache address mapping table, and write the corresponding data into the row cache according to the row cache size;

[0157] Determine the mapping address of each data in the row cache according to the cache address of each data in the row cache and the mapping unit mapping table, and write each data into the memory according to the mapping address of each data;

[0158] Reorder the data in the memory according to the mapping address of each data in the memory and the reorder address mapping table, and write the reordered data into the reorder cache;

[0159] Output each data in the reordering buffer to the corresponding driver IC in sequence.

[0160] Exemplarily, the type of driver IC is reordered, and the above data is pixel as an example (the processing in the case of bit separation can be obtained in the same way).

[0161] For any pixel in the input image, the driver IC display coordinates of the pixel can be determined based on the pixel coordinates of the pixel and the row and column extraction configuration table.

[0162] For example, suppose the row and column extraction configuration is as follows Fig.10 As shown, for an input image, the image can be divided into blocks of 7*7 size. For any image block, its corresponding driver IC can be determined according to its position in the image and the distribution of the driver ICs.

[0163] like Fig.10 As shown, for any pixel in any image block, the driver IC display coordinates of the pixel in the corresponding driver IC can be determined according to the pixel coordinates of the pixel in the image block.

[0164] Assuming that the pixel coordinates are (0, 0) to (7, 7), and there is a row and column extraction in the 4th row and 3rd column, when converted to the driver IC display coordinates, it becomes 8*8 in size, where the 4th row and 3rd column are reinserted rows and columns. In the coordinate conversion process, the pixels before the 4th row and 3rd column ( Fig.10 The coordinates of the 6 pixels in the upper left corner of the right side remain unchanged), and the remaining pixels need to be transformed. Among them, Fig.10The horizontal coordinates of the 12 pixels in the upper right corner on the right side need to be increased by 1; the vertical coordinates of the 8 pixels in the lower left corner need to be increased by 1; and the horizontal and vertical coordinates of the 20 pixels in the lower right corner both need to be increased by 1.

[0165] Exemplarily, when the display coordinates of the driver IC of each pixel are determined, the cache address of each pixel may be determined according to the display coordinates of the driver IC of each pixel and the cache address mapping table.

[0166] For example, in the process of caching pixels in an input image, a basic storage unit may be determined based on a basic splicing unit and a scanning unit, and the pixels in the input image may be stored in the cache using the basic storage unit as a basic unit.

[0167] by Figure 7 For example, assuming that the data group includes 2 rows and 2 columns of driver ICs (assuming that the upper left corner is driver IC1, the upper right corner is driver IC2, the lower left corner is driver IC3, and the lower right corner is driver IC4), the driver IC size is 4*4, and there is a transposition (that is, the driver IC is scanned from top to bottom and from left to right), and the row cache size is 4 row caches. PU=2, SU=4, MU=8.

[0168] In this example, the actual output order of the pixels is: the upper left pixel of driver IC1 ( Figure 7 Pixel 0 in the middle, the driver IC displays the coordinates (1, 0, 0)), the upper left pixel of driver IC3 (the driver IC displays the coordinates (3, 0, 0)), the upper left pixel of driver IC2 ( Figure 7 Pixel 1 in the driver IC display coordinates are (2, 0, 0)), the upper left corner pixel of driver IC4 (the driver IC display coordinates are (4, 0, 0)), the pixel in the first column and second row of driver IC1 ( Figure 7 Pixel 2 in the driver IC displays coordinates (1, 0, 1)), pixel 1 in the first column and second row of driver IC3 (driver IC displays coordinates (3, 0, 1)), pixel 1 in the first column and second row of driver IC2 ( Figure 7 For pixel 3 in the image, the driver IC displays the coordinates as (2, 0, 1)), …, and so on.

[0169] Since the row cache size is 4 rows, in the process of caching the first 4 rows of pixels, the pixels corresponding to driver IC3 and driver IC4 cannot be obtained. In this case, the pixels included in the first MU are the first column pixels of driver IC1 and the first column pixels of driver IC2, and their arrangement order in the cache is: 0, 1, 2, 3, 4, 5, 6, 7, and the corresponding cache address is the first row of the row cache.

[0170] When the cache address of each pixel is determined, the mapping address of each pixel in the row cache may be determined according to the cache address of each pixel and the mapping unit mapping table.

[0171] Exemplarily, in the process of mapping pixels in the cache, the mapping may be performed with a basic storage unit (such as MU) as a basic unit.

[0172] For example, Figure 8 For example, due to the limitation of row cache size, in the process of pixel caching, the cache order of each MU is MU0, MU2, MU1, MU3, but because the driver IC is in the order from top to bottom and from left to right, the actual output order of MU1 is before MU2. Therefore, in the process of mapping the pixels in the cache, the offset can be set so that the address of MU1 in the memory is before MU2, that is, in the memory, the actual order of each MU is MU0, MU1, MU2, MU3.

[0173] When the mapping address of each pixel is determined, the pixels may be reordered according to the actual output order of the pixels, and the reordered pixels may be written into the reordering buffer.

[0174] by Figure 8 Take the MU mapping shown in the figure as an example. Figure 8 In the process of reordering the data in the memory, the driver IC is scanned from top to bottom and from left to right. The mapping relationship between the mapping coordinates and the reordering coordinates can be as follows: Fig. 9 shown.

[0175] like Fig. 9 As shown, the first pixel in MU0 (i.e. Fig. 9 The pixel 0 in MU1 (i.e. the pixel in the upper left corner of the driver IC in the upper left corner) is output first, and then the first pixel in MU2 (i.e. Fig. 9 1, which is the pixel in the upper left corner of the driver IC in the lower left corner, and then outputs the second pixel in MU0 (i.e. Fig. 9 2, which is the pixel at the upper left corner of the driver IC in row 1 and column 2), and then outputs the second pixel in MU1 (i.e. Fig. 9 , i.e., the pixel at the upper left corner of the driver IC at the 2nd row and the 2nd column), and so on, to achieve the reordering of the pixels in the memory.

[0176] In the embodiment of the present application, the complete address mapping process can be found in Fig.11 .

[0177] like Fig.11As shown, for the received input image, the row and column extraction information of the driver IC can be determined according to the row and column extraction configuration table, and according to the row and column extraction information of the driver IC, the image coordinates and the driver IC display coordinates of each data in the input image are converted to obtain the driver IC display coordinates of each data in the input image.

[0178] After the driver IC display coordinates of each data in the input image are obtained, the cache address of each data can be determined according to the cache address mapping table, and the corresponding data can be written into the cache according to the row cache size.

[0179] Exemplarily, in order to improve cache reading and writing efficiency, during the process of performing cache reading and writing, cache reading and writing may be performed in units of basic splicing units (such as MU).

[0180] like Fig.11 As shown, assuming that the type of the driver IC is reordering, the driver IC is transposed (that is, the scanning mode of the driver IC is from top to bottom and from left to right), the size of the driver IC is 4*4, the row cache is a 4-row cache, and the maximum number of pixels continuously scanned by a single driver IC is 4 (that is, a column of pixels of the driver IC), then the size of the MU can be 8, and the first MU can include the first column of pixels of driver IC1 (the driver IC in the first row and first column), and the first column of pixels of driver IC2 (the driver IC in the first row and second column). The order of the 8 pixels in the MU is: pixels in the first row and first column of driver IC1, pixels in the first row and first column of driver IC2, pixels in the second row and first column of driver IC1, pixels in the second row and first column of driver IC2, pixels in the third row and first column of driver IC1, pixels in the third row and first column of driver IC2, pixels in the third row and first column of driver IC1, and pixels in the second row and first column of driver IC4.

[0181] For the data in the cache, the mapping address of each data in the cache can be determined according to the cache address of each data in the cache and the mapping table of the mapping unit, and the data can be written into the memory according to the mapping address of each data.

[0182] Exemplarily, for the data in the cache, the mapping address may be mapped in units of MUs to obtain the mapping address of each MU in the cache, and the data may be written into the memory in units of MUs.

[0183] For the data in the memory, the reorder address of each data can be determined according to the reorder address mapping table, the data can be written into the reorder cache according to the reorder address of each data, and each data can be reordered in the reorder cache (the sorting result is consistent with the actual output order of each data), so as to obtain input data whose sorting result is consistent with the actual output order.

[0184] Exemplarily, the data may be output in sequence (to the corresponding driver IC) according to the sorting result of the data in the reordering buffer.

[0185] It can be seen that in the above process, by mapping the image coordinates and the display coordinates of the driver IC based on the row and column extraction configuration, the image display can be realized when the number of output pixels of the driver IC does not match the image size; by realizing the mapping of the display coordinates of the driver IC and the cache address based on the cache address mapping table, in the process of writing data into the cache, the data pre-sorting can be realized for different driver IC types, physical arrangements and routing methods; by realizing the mapping between the cache address and the mapping address based on the mapping address unit mapping table, the data caching method with the basic storage unit as the basic unit can be combined to ensure the data reading and writing efficiency in the cache / memory, so that the sorting of the data in the memory is closer to the actual output order of the data; by reordering the data in the memory based on the reordering address mapping table, the data in the memory is sorted according to the actual output order, thereby improving the data output efficiency. Through four address mapping operations, the image data of the entire receiving card can be taken out from the memory at one time, reducing the number of memory reads and writes, and improving the memory read and write efficiency.

[0186] The method provided by the present application is described above. The device provided by the present application is described below:

[0187] See also Fig.12 , is a schematic diagram of the structure of a data rearrangement device for an LED receiving card provided in an embodiment of the present application, wherein the data rearrangement device for an LED receiving card can be deployed on the above-mentioned host computer, such as Fig.12 As shown, the LED receiving card data rearrangement device may include:

[0188] The generating unit 1210 is used to generate a cache address mapping table for any data group corresponding to the LED display screen according to the type, physical arrangement and routing of each driver integrated circuit IC in the data group, and the row cache size of the LED receiving card corresponding to the data group; wherein the cache address mapping table is used to record the mapping relationship between the display coordinates of the driver IC and the cache address;

[0189] The generating unit 1210 is further used to generate a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data; wherein the mapping unit mapping table is used to record the mapping relationship between the cache address and the mapping address, and the input data is written into the memory according to the mapping address;

[0190] The generating unit 1210 is further used to generate a reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data; wherein the reordering address mapping table is used to record the mapping relationship between the mapping address and the reordering address, and the data in the memory is written into the reordering cache according to the reordering address;

[0191] The sending unit 1220 is used to send the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table to the LED receiving card corresponding to the data group, so that the LED receiving card rearranges the received input data according to the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table; wherein the row-column extraction configuration table is used to realize the conversion between the image coordinates of the input pixels and the display coordinates of the driver IC.

[0192] In some embodiments, the generating unit 1210 generates a cache address mapping table according to the type, physical arrangement, and routing of each driver IC in the data group, and the row cache size of the LED receiving card corresponding to the data group, including:

[0193] Determine a corresponding basic splicing unit according to the type of each driver IC in the data group and the physical arrangement of each driver IC in the data group; wherein the size of the basic splicing unit is determined according to the number or grouping of driver ICs in the row buffer;

[0194] Determine the scanning order of each driver IC according to the physical arrangement and routing of each driver IC in the data group, and determine the corresponding scanning unit according to the scanning order of each driver IC and the row buffer size of the LED receiving card corresponding to the data group; wherein the scanning unit is determined according to the number of data continuously scanned by a single driver IC;

[0195] Determine a basic storage unit in a cache unit according to the basic splicing unit and the scanning unit;

[0196] According to the scanning sequence of each driver IC and the basic storage unit in the cache unit, the mapping relationship between the driver IC display coordinates and the cache address is determined, and a cache address mapping table is generated.

[0197] In some embodiments, the generating unit 1210 generates a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data, including:

[0198] Determine the output order of each basic storage unit in the cache according to the actual output order of each data in the cache;

[0199] According to the output sequence of each basic storage unit in the cache, the mapping relationship between the cache address and the mapping address is determined, and a mapping unit mapping table is generated.

[0200] In some embodiments, the generating unit 1210 generates a reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data, including:

[0201] Reordering the data in the memory according to the actual output order of the data in the memory;

[0202] According to the reordering result of each data in the memory, a mapping relationship between the mapping address and the reordering address is determined, and the reordering address mapping table is generated.

[0203] See also Fig.13 , is a schematic diagram of the structure of a data rearrangement device for an LED receiving card provided in an embodiment of the present application, wherein the data rearrangement device for an LED receiving card can be deployed on the above-mentioned LED receiving card, such as Fig.13 As shown, the LED receiving card data rearrangement device may include:

[0204] The acquisition unit 1310 is used to acquire a row-and-column extraction configuration table, a cache address mapping table, a mapping unit mapping table, and a reordering address mapping table; wherein the row-and-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table are configured according to Figure 1 The LED receiving card data rearrangement method shown is generated;

[0205] The processing unit 1320 is used to output each pixel in the input image to the corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table when receiving the input image.

[0206] In some embodiments, the processing unit 1320 outputs each pixel in the input image to the corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table, including:

[0207] Determine the display coordinates of the driver IC of each data in the input image according to the row and column extraction configuration table;

[0208] Determine the cache address of each data according to the driver IC display coordinates of each data and the cache address mapping table, and write the corresponding pixel into the row cache according to the row cache size;

[0209] Determine the mapping address of each data in the row cache according to the cache address of each data in the row cache and the mapping unit mapping table, and write each data into the memory according to the mapping address of each data;

[0210] Reordering the data in the memory according to the mapping addresses of the data in the memory and the reordering address mapping table, and writing the reordered data into the reordering cache;

[0211] Output each data in the reordering buffer to the corresponding driver IC in sequence.

[0212] An embodiment of the present application also provides an electronic device, including a processor and a memory, wherein the memory is used to store a computer program; and the processor is used to implement the LED receiving card data rearrangement method described above when executing the program stored in the memory.

[0213] See also Fig.14 , is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. The electronic device may include a processor 1401 and a memory 1402 storing machine executable instructions. The processor 1401 and the memory 1402 may communicate via a system bus 1403. Furthermore, by reading and executing the machine executable instructions corresponding to the LED receiving card data rearrangement logic in the memory 1402, the processor 1401 may execute the LED receiving card data rearrangement method described above.

[0214] The memory 1402 mentioned herein may be any electronic, magnetic, optical or other physical storage device that may contain or store information, such as executable instructions, data, etc. For example, the machine-readable storage medium may be: RAM (RadomAccess Memory, random access memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as optical disk, DVD, etc.), or similar storage medium, or a combination thereof.

[0215] In some embodiments, a machine-readable storage medium is also provided. Fig.14 The memory 1402 in the machine readable storage medium stores machine executable instructions, and when the machine executable instructions are executed by the processor, the LED receiving card data rearrangement method described above is implemented. For example, the machine readable storage medium can be ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

[0216] The embodiment of the present application also provides a computer program product, which stores a computer program, and when a processor executes the computer program, it prompts the processor to execute the LED receiving card data rearrangement method described above.

Claims

1. A method for rearranging data of an LED receiving card, characterized in that: include: For any data group corresponding to the LED display screen, a cache address mapping table is generated according to the type, physical arrangement, and routing of each driver integrated circuit IC in the data group, and the row cache size of the LED receiving card corresponding to the data group; wherein the cache address mapping table is used to record the mapping relationship between the driver IC display coordinates and the cache address; Generate a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data; wherein the mapping unit mapping table is used to record the mapping relationship between the cache address and the mapping address, and the input data is written into the memory according to the mapping address; Generate a reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data; wherein the reordering address mapping table is used to record the mapping relationship between the mapping address and the reordering address, and the data in the memory is written into the reordering cache according to the reordering address; The row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table are sent to the LED receiving card corresponding to the data group, so that the LED receiving card rearranges the received input data according to the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table; wherein the row-column extraction configuration table is used to realize the conversion between the image coordinates of the input data and the display coordinates of the driver IC.

2. The method according to claim 1, characterized in that According to the type, physical arrangement, and routing of each driver IC in the data group, and the row cache size of the LED receiving card corresponding to the data group, a cache address mapping table is generated, including: Determine a corresponding basic splicing unit according to the type of each driver IC in the data group and the physical arrangement of each driver IC in the data group; wherein the size of the basic splicing unit is determined according to the number or grouping of driver ICs in the row buffer; Determine the scanning order of each driver IC according to the physical arrangement and routing of each driver IC in the data group, and determine the corresponding scanning unit according to the scanning order of each driver IC and the row buffer size of the LED receiving card corresponding to the data group; wherein the scanning unit is determined according to the number of data continuously scanned by a single driver IC; Determine a basic storage unit in a cache unit according to the basic splicing unit and the scanning unit; According to the scanning sequence of each driver IC and the basic storage unit in the cache unit, the mapping relationship between the driver IC display coordinates and the cache address is determined, and a cache address mapping table is generated.

3. The method according to claim 1, characterized in that: The method generates a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data, including: Determine the output order of each basic storage unit in the cache according to the actual output order of each data in the cache; According to the output sequence of each basic storage unit in the cache, the mapping relationship between the cache address and the mapping address is determined, and a mapping unit mapping table is generated.

4. The method according to claim 1, characterized in that: The generating of the reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data includes: Reordering the data in the memory according to the actual output order of the data in the memory; According to the reordering result of each data in the memory, a mapping relationship between the mapping address and the reordering address is determined, and the reordering address mapping table is generated.

5. A method for rearranging data of an LED receiving card, characterized in that: include: Obtaining a row-and-column extraction configuration table, a cache address mapping table, a mapping unit mapping table, and a reordering address mapping table; wherein the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table are generated according to the method described in any one of claims 1 to 4; the row-and-column extraction configuration table is used to realize the conversion between the image coordinates of the input data and the display coordinates of the driver IC; When an input image is received, data in the input image are output to a corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table.

6. The method according to claim 5, characterized in that Outputting each pixel in the input image to the corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table includes: Determine the display coordinates of the driver IC of each data in the input image according to the row and column extraction configuration table; Determine the cache address of each data according to the driver IC display coordinates of each data and the cache address mapping table, and write the corresponding data into the row cache according to the row cache size; Determine the mapping address of each data in the row cache according to the cache address of each data in the row cache and the mapping unit mapping table, and write each data into the memory according to the mapping address of each data; Reordering the data in the memory according to the mapping addresses of the data in the memory and the reordering address mapping table, and writing the reordered data into the reordering cache; Output each data in the reordering buffer to the corresponding driver IC in sequence.

7. A data rearrangement device for an LED receiving card, characterized in that: include: A generating unit is used to generate a cache address mapping table for any data group corresponding to the LED display screen according to the type, physical arrangement and routing of each driver integrated circuit IC in the data group, and the row cache size of the LED receiving card corresponding to the data group; wherein the cache address mapping table is used to record the mapping relationship between the display coordinates of the driver IC and the cache address; The generating unit is further used to generate a mapping unit mapping table according to the actual output order of each data in the cache and the cache address of each data; wherein the mapping unit mapping table is used to record the mapping relationship between the cache address and the mapping address, and the input data is written into the memory according to the mapping address; The generating unit is further used to generate a reordering address mapping table according to the actual output order of each data in the memory and the mapping address of each data; wherein the reordering address mapping table is used to record the mapping relationship between the mapping address and the reordering address, and the data in the memory is written into the reordering cache according to the reordering address; A sending unit is used to send the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table to the LED receiving card corresponding to the data group, so that the LED receiving card rearranges the received input data according to the row-column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table; wherein the row-column extraction configuration table is used to realize the conversion between the image coordinates of the input pixels and the display coordinates of the driver IC.

8. A data rearrangement device for an LED receiving card, characterized in that: include: an acquisition unit, used for acquiring a row-and-column extraction configuration table, a cache address mapping table, a mapping unit mapping table, and a reordering address mapping table; wherein the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table are generated according to the method described in any one of claims 1 to 4; the row-and-column extraction configuration table is used for realizing the conversion between the image coordinates of the input data and the display coordinates of the driver IC; The processing unit is used to output each pixel in the input image to the corresponding driver IC according to the row and column extraction configuration table, the cache address mapping table, the mapping unit mapping table, and the reordering address mapping table when receiving the input image.

9. An electronic device, characterized in that: comprising a processor and a memory, wherein: Memory, used to store computer programs; A processor, for implementing the method described in any one of claims 1 to 4 or 5 to 6 when executing a program stored in a memory.

10. A computer program product, characterized in that The computer program product stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 4 or 5 to 6 is implemented.

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