Method and system for improving receiving and transmitting efficiency of ARINC717 data
By setting up programmable logic devices between the CPU and the HI3717 chip, the time-consuming task of processing ARINC717 bus data is solved, and the data transmission rate and CPU processing capability are improved.
Patent Information
- Application Number
- CN202411443625.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-16
- Publication Date
- 2025-02-07
AI Technical Summary
The ARINC717 bus data transmission efficiency is low, resulting in excessive CPU bandwidth usage and cannot meet the maximum transmission rate requirements.
The programmable logic device is set up between the CPU and the HI3717 chip, and the time-consuming task of processing ARINC717 bus data is handed over to the programmable logic device to process the ARINC717 bus data. The CPU only needs to read and write data words directly from the programmable logic device.
It effectively improves the ARINC717 data transmission rate, reduces the operating burden of the CPU, and avoids the transmission rate limit caused by insufficient CPU processing capabilities.
Smart Images
Figure CN119396757A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of civil aircraft cabin systems, and in particular to a method and system for improving the efficiency of ARINC717 data reception and transmission. Background Art
[0002] The ARINC717 bus is an aviation bus currently used by most civil transport aircraft to transmit slowly changing data. The aviation bus ARINC717 is developed from ARINC573, which adds more stringent standards for input parameters, improves data transmission speed, and adds a "super frame" transmission method. The aviation bus ARINC717 transmits data through a pair of twisted pair cables, with frames as the basic data transmission unit, and each frame lasts for 4 seconds; each frame of data consists of 4 subframes, each subframe lasts for 1 second, and each subframe can be composed of several words. The specific number of words in each subframe can be set to 64 words, 128 words, 256 words, 512 words or 1024 words; each word has 12 data bits, and flight parameters are filled into words and bits. The first word of each subframe is the synchronization word, which uses the Barker code mode. The ARINC717 bus data structure is as follows: Figure 1 shown.
[0003] The transceiver interface of the ARINC717 bus uses the HI-3717 chip of the American HOLT Integrated Circuit Company. This chip complies with the electrical interface standard of ARINC717, uses the serial SPI bus to connect to the external controller, supports two line-side transceiver interfaces, HBP and BPRZ, and supports up to 32, 64, 128, 256, 512, 1024, 2048, 4096, and 8192 words per subframe exceeding the ARINC717 standard.
[0004] Data transmission on the aviation bus ARINC717 is uninterrupted and has strict time limits. This requires the CPU connected to the ARINC717 bus transceiver chip to continuously read and write data to the HI3717 chip. In addition, the connected data interface is still the low-speed serial SPI, and the transmission efficiency is relatively low. This will result in that if the external controller CPU is directly connected to the HI3717 via SPI, whether it is sampling polling or interrupt access, it will occupy a large amount of CPU bandwidth, squeezing the processing of other CPU tasks, and even unable to meet the maximum transmission rate required by the ARINC717 bus specification. Summary of the invention
[0005] In order to solve the problem of low ARINC717 data transmission efficiency, the present application proposes a method and system for improving the efficiency of ARINC717 data transmission and reception. The present application sets a programmable logic device between the CPU and HI3717, and the time-consuming task of HI3717 chip receiving and transmitting ARINC717 bus data is handed over to the programmable logic device for processing, thereby freeing the CPU from frequent HI3717 chip operations. The CPU only needs to directly read and write ARINC717 bus data words from the programmable logic device, thereby effectively improving the ARINC717 data transmission rate.
[0006] On the one hand, the present application is implemented through the following technical solutions:
[0007] A method for improving ARINC717 data transceiver efficiency, the method comprising:
[0008] A programmable logic device is arranged between the CPU and the HI37117 chip; the programmable logic device includes an A717 control register and a data transceiver buffer register; wherein the A717 control register includes at least: an ARINC717 bus transceiver rate BR, a voltage slew rate SLEW of the line side HBP and BPRZ signals, an interface type RXSEL of the receiving side line, an A717 transceiver module soft reset SRST, a loopback test TEST, a data transmission start TSTART, a data transmission completion indication TFINISH, and a data reception completion indication RFINISH control bit;
[0009] The programmable device configures the HI3717 chip according to the working parameter value in the A717 control register to send and receive data from the ARINC717 bus;
[0010] The CPU only needs to directly read the ARINC717 bus data word from the programmable logic device.
[0011] In some implementations, the programmable logic device and the CPU use an HPI parallel bus or a PCIe bus for data exchange.
[0012] In some implementations, the space of the data transceiver buffer register facing the CPU in the programmable logic device is enlarged and expanded, further reducing the frequency of the CPU reading and writing ARINC717 bus data.
[0013] In some implementations, the process of the CPU receiving data from the programmable logic device includes:
[0014] The programmable logic device provides a data receiving buffer register space for storing received data according to the maximum subframe word number required by the ARINC717 protocol. After the programmable logic device receives a subframe of ARINC717 data, it immediately sets the data receiving completion indication RFINISH of the A717 control register to 1;
[0015] The CPU polls and checks RFINISH in the A717 control register at a frequency not lower than a frequency threshold. If RFINISH is detected to be 1, all data of the entire subframe is immediately read out from the data receiving buffer register of the programmable logic device at one time.
[0016] In some implementations, the process of the CPU sending data to the programmable logic device includes:
[0017] The programmable logic device provides a data transmission buffer register space for storing the transmitted data according to the maximum subframe word number required by the ARINC717 protocol. After the programmable logic device sends a subframe of ARINC717 data, it immediately sets the data transmission completion indication TFINISH of the A717 control register to 1;
[0018] The CPU polls and checks TFINISH in the A717 control register at a frequency not lower than the frequency threshold. If TFINISH is detected to be 1, all data of the entire subframe is immediately written to the data sending buffer register of the programmable logic device at one time, and then TSTART is set to 1.
[0019] In some implementations, the process of the programmable logic device receiving data from the HI3717 chip includes:
[0020] The programmable logic device continuously reads data from the HI3717 chip through the SPI bus, first polls the Receive FIFO Status register of the HI3717 chip to detect whether the receive FIFO has received data, and if the receive FIFO is not empty, writes the word in the receive FIFO of the HI3717 chip into the data receive buffer register of the programmable logic device;
[0021] There are two data receiving buffer registers implemented inside the programmable logic device, which use a ping-pong mechanism to exchange data with the CPU; the two data receiving buffer registers work simultaneously, and the data receiving buffer register A facing the CPU stores the ARINC717 subframe data read last time, and the other data receiving buffer register B stores the ARINC717 subframe data currently being read from the HI3717 chip; after completing the reception of a subframe data from the HI3717 chip and writing it into the data receiving buffer register B, a ping-pong switch is performed, and the data receiving buffer register B and the data receiving buffer register A swap roles, that is, the data receiving buffer register B storing the subframe data received this time becomes the read buffer register of the CPU, and the data receiving buffer register A becomes the read buffer register of the HI3717 chip, and then the RFINISH of the A717 control register is set to 1 to notify the CPU to read the latest received ARINC717 data.
[0022] In some implementations, the process of the programmable logic device sending data to the HI3717 chip includes:
[0023] The programmable logic device continuously sends data to the HI3717 chip through the SPI bus, first polling the Transmit FIFO Status register of the HI3717 chip to detect whether the transmit FIFO is full, and if the transmit FIFO is not full, taking data from the data transmit buffer register of the programmable logic device and writing it into the transmit FIFO of the HI3717 chip;
[0024] There are two data transmission buffer registers implemented inside the programmable logic device, which use a ping-pong mechanism to exchange data with the HI3717 chip. The two data transmission buffer registers work simultaneously. The data transmission buffer register A facing the CPU stores the ARINC717 subframe data written by the CPU this time, and the other data transmission buffer register B stores the ARINC717 subframe data currently sent to the HI3717 chip; when the data stored in the data transmission buffer register B is sent to the HI3717 chip, a ping-pong switch is performed, and the data transmission buffer register A and the data transmission buffer register B swap roles, that is, the data transmission buffer register B storing the currently sent subframe data becomes the transmission buffer register of the CPU, and the data transmission buffer register A becomes the transmission buffer register of the HI3717 chip; then the TFINISH of the A717 control register is set to 1 to notify the CPU to write the next ARINC717 subframe data to be sent.
[0025] On the other hand, the present application also proposes a system for improving the efficiency of ARINC717 data transmission and reception, the system comprising:
[0026] A programmable logic device, wherein the programmable logic device includes an A717 control register and a data transceiver buffer register;
[0027] The A717 control register at least includes the ARINC717 bus transceiver rate BR, the voltage slew rate SLEW of the line side HBP and BPRZ signals, the interface type RXSEL of the receiving side line, the A717 transceiver module soft reset SRST, the loopback test TEST, the start data transmission TSTART, the data transmission completion indication TFINISH, and the data reception completion indication RFINISH control bits;
[0028] The programmable logic device configures the HI3717 chip according to the working parameter value in the A717 control register to send and receive data from the ARINC717 bus;
[0029] The CPU only needs to directly read the ARINC717 bus data word from the programmable logic device.
[0030] In some implementations, the size of the data transceiver buffer register space is determined by the maximum number of subframe words required by the ARINC717 protocol; the CPU checks the parameters in the A717 control register by polling to achieve transceiver control between it and the programmable logic device.
[0031] In some embodiments, the data transceiver buffer register includes two data receive buffer registers and two data send buffer registers, wherein the two data receive buffer registers use a ping-pong mechanism to exchange data with the CPU, and the two data send buffer registers use a ping-pong mechanism to exchange data with the CPU; the programmable logic device checks the parameters in the transceiver FIFO status register in the HI3717 chip by polling to realize its transceiver control with the HI3717 chip.
[0032] The present application proposes a method and system for improving the efficiency of ARINC717 data reception and transmission, which adopts a programmable logic device to replace the CPU to receive and transmit aviation bus ARINC717 data, freeing the CPU from the cumbersome and resource-consuming ARINC717 bus reception and transmission, while also avoiding the actual ARINC717 bus rate failing to reach the protocol upper limit requirement due to insufficient CPU processing power, thereby effectively improving the efficiency of ARINC717 data reception and transmission. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The drawings described herein are used to provide a further understanding of the embodiments of the present application, constitute a part of the present application, and do not constitute a limitation on the embodiments of the present application. In the drawings:
[0034] Figure 1 This is the ARINC717 bus data structure diagram;
[0035] Figure 2 This is a schematic diagram of the method principle proposed in the embodiment of the present application;
[0036] Figure 3 A flow chart for receiving data from a programmable logic device for the CPU;
[0037] Figure 4 Send data flow chart to programmable logic device for CPU;
[0038] Figure 5 receiving a process flow chart for a programmable logic device;
[0039] Figure 6 The architecture diagram for the internal receive buffer of a programmable logic device is shown;
[0040] Figure 7 sending a process flow chart to a programmable logic device;
[0041] Figure 8 The architecture diagram for sending buffer inside the programmable logic device;
[0042] Fig. 9 A schematic diagram of the system architecture proposed in an embodiment of the present application. DETAILED DESCRIPTION
[0043] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with examples and drawings. The illustrative implementation scheme of the present application and its description are only used to explain the present application and are not intended to limit the present application.
[0044] Example:
[0045] In order to improve the data transmission rate of the ARINC717 bus, this embodiment proposes a method for improving the efficiency of ARINC717 data transmission and reception. The method proposed in this embodiment inserts a programmable logic device between the CPU and the HI3717 chip, and combines corresponding interface technology and data transmission and reception method to achieve efficient transmission and reception of ARINC717 bus data.
[0046] like Figure 2As shown, the method proposed in this embodiment is to set a programmable logic device between the CPU and the HI3717 chip; configure the HI3717 chip through the control register in the programmable logic device to receive and send data from the ARINC717 bus; the CPU only needs to directly read and write ARINC717 bus data words from the programmable logic device, thereby freeing the CPU from the tedious and resource-consuming ARINC717 bus receiving and sending work, and also avoiding the actual ARINC717 bus rate failing to meet the protocol upper limit requirement due to insufficient CPU processing power, thereby effectively improving the ARINC717 bus data receiving and sending efficiency.
[0047] It should be noted that the programmable logic devices used in this embodiment include but are not limited to: CPLD, FPGA and other logic devices.
[0048] Furthermore, after adding programmable logic devices, the CPU's ARINC717 bus data transmission and reception efficiency can be further improved in the following ways:
[0049] Use HPI parallel bus or PCIe bus between CPU and programmable logic device to improve the data reading and writing rate on CPU side;
[0050] And / or, the data transceiver buffer of the original HI3717 chip has only 32 words, and the transceiver buffer for the CPU can be enlarged and expanded through a programmable logic device, further reducing the frequency of the CPU reading and writing ARINC717 data.
[0051] In an optional implementation manner, the data transmission and reception process between the CPU and the programmable logic device specifically includes:
[0052] In order for the PLD and HI3717 to work correctly and send and receive data from the ARINC717 bus, it is necessary to add configuration registers in the PLD to set the operating parameters.
[0053] Specifically, an A717 control register can be added to the programmable logic device, the CPU sets the register content during operation, and then the programmable logic device configures the HI3717 chip according to the set register value. The A717 control register should at least contain the ARINC717 bus transceiver rate BR (64 words / sec to 8192 words / sec), the voltage slew rate SLEW of the line side HBP and BPRZ signals, the interface type RXSEL (HBP or BPRZ) of the receiving side line, the A717 transceiver module soft reset SRST, the loopback test TEST, the start of data transmission TSTART, the data transmission completion indication TFINISH, and the data reception completion indication RFINISH control bits.
[0054] Based on the configuration of the programmable logic device, the CPU receives data from the programmable logic device and sends data to the programmable logic device.
[0055] Among them, Figure 3 As shown, the CPU receives data from the programmable logic device specifically including:
[0056] The programmable logic device provides a receiving buffer space for storing received data according to the maximum subframe word number required by the ARINC717 protocol. After the programmable logic device receives a subframe of ARINC717 data, it will immediately set the data reception completion indication RFINISH of the A717 control register to 1.
[0057] The CPU polls and checks the RFINISH of the A717 control register at a frequency of not less than 10 Hz. If RFINISH is detected to be 1, all the data of the entire subframe will be read out from the receiving buffer of the programmable logic device at one time.
[0058] like Figure 4 As shown, the CPU sends data to the programmable logic device specifically including:
[0059] The programmable logic device provides a sending buffer space for storing the transmitted data according to the maximum subframe word number required by the ARINC717 protocol. After the programmable logic device sends a subframe of ARINC717 data, it will immediately set the data transmission completion indication TFINISH of the A717 control register to 1.
[0060] The CPU polls and checks the TFINISH of the A717 control register at a frequency of not less than 10Hz. If it detects that TFINISH is 1, it immediately writes all the data of the entire subframe to the transmit buffer of the programmable logic device at one time, and then sets TSTART to 1.
[0061] In an optional implementation manner, the data transmission and reception process between the programmable logic device and the HI3717 chip specifically includes:
[0062] like Figure 5 As shown in the figure, during the receiving process of the programmable logic device, the programmable logic device continuously reads data from the HI3717 chip through the SPI bus. First, the Receive FIFO Status register of the HI3717 chip is polled to detect whether the Receive FIFO has received data. If the FIFO is not empty, the word in the HI3717 chip receive FIFO is written into the receive buffer of the programmable logic device.
[0063] There are two receiving buffers implemented inside the programmable logic device, which use the ping-pong mechanism to exchange data with the CPU. The two buffers work simultaneously. Buffer 1 is used as a receiving buffer facing the CPU, and stores the ARINC717 subframe data read last time; buffer 2 stores the data of the ARINC717 subframe currently being read from the HI3717 chip; after receiving a subframe data from the HI3717 and writing it into buffer 2, a ping-pong switch is performed, and the roles of buffer 2 and buffer 1 are swapped, that is, buffer 2 storing the subframe data received this time becomes the CPU's read buffer, and buffer 1 becomes the HI3717's read buffer, and then the RFINISH of the A717 control register is set to 1 to notify the CPU to read the latest received ARINC717 data. Figure 6 shown.
[0064] like Figure 7 As shown, during the transmission process of the programmable logic device, the programmable logic device continuously sends data to the HI3717 chip through the SPI bus. First, the Transmit FIFO Status register of the HI3717 chip is polled to detect whether the transmit FIFO is full. If the FIFO is not full, data is taken from the transmit buffer of the programmable logic device and written into the transmit FIFO of the HI3717 chip.
[0065] There are two transmission buffers implemented inside the programmable logic device. The ping-pong mechanism is used to exchange data with the HI3717 chip. The two buffers work simultaneously. Buffer 1 is used as a transmission buffer for the CPU and stores the ARINC717 subframe transmission data written by the CPU this time. Buffer 2 stores the ARINC717 subframe data currently sent to the HI3717 chip. When the data stored in buffer 2 is sent to the HI3717 chip, a ping-pong switch is performed, and the roles of buffer 2 and buffer 1 are swapped, that is, buffer 2 storing the subframe data sent this time becomes the CPU's transmission buffer, and buffer 1 becomes the HI3717 chip's transmission buffer. Then the TFINISH of the A717 control register is set to 1 to notify the CPU to write the next ARINC717 subframe data to be sent. Figure 8 shown.
[0066] The method proposed in this embodiment uses a programmable logic device to replace the CPU to transmit and receive aviation bus ARINC717 data, freeing the CPU from the tedious and resource-consuming ARINC717 bus data transmission and reception work, while also avoiding the actual ARINC717 bus rate failing to meet the protocol upper limit requirement due to insufficient CPU processing power, effectively improving the aviation bus ARINC717 data transmission and reception efficiency.
[0067] Based on the same technical concept as above, this embodiment also proposes a system for improving the efficiency of ARINC717 data transmission and reception, such as Fig. 9 As shown, the system proposed in this embodiment includes:
[0068] A programmable logic device comprises an A717 control register and a data transceiver buffer register.
[0069] Among them, the A7171 control register at least includes the ARINC717 bus transceiver rate BR (64 words / sec to 8192 words / sec), the voltage slew rate SLEW of the line side HBP and BPRZ signals, the interface type RXSEL (HBP or BPRZ) of the receiving side line, the A717 transceiver module soft reset SRST, the loopback test TEST, the start of data transmission TSTART, the data transmission completion indication TFINISH, and the data reception completion indication RFINISH control bits. The CPU sets the working parameters during actual operation.
[0070] The size of the data transceiver buffer register space is determined by the maximum number of subframe words required by the ARINC717 protocol, that is, the data transceiver buffer register can store all the data of the maximum subframe required by the ARINC717 protocol. The CPU checks the parameters in the A717 control register by polling to realize the transceiver control between it and the programmable logic device. The specific transceiver process is described in the above method and will not be repeated here.
[0071] The data transceiver buffer register includes two data receiving buffer registers (i.e., data receiving buffer register 1 and data receiving buffer register 2) and two data sending buffer registers (i.e., data sending buffer register 1 and data sending buffer register 2), and the two data receiving buffer registers use a ping-pong mechanism to interact with the CPU for data, and the two data sending buffer registers use a ping-pong mechanism to interact with the CPU for data; the programmable logic device checks the parameters in the FIFO status register in the HI3717 chip by polling to realize its transceiver control with the HI3717 chip. The specific transceiver process is described in the above method, and will not be repeated here.
[0072] Furthermore, the programmable logic device communicates with the CPU using an HPI parallel bus or a PCIe bus.
[0073] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0074] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0075] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0076] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0077] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation method of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.
Claims
1. A method for improving the efficiency of ARINC717 data transmission and reception, characterized in that: The method comprises: A programmable logic device is arranged between the CPU and the HI37117 chip; the programmable logic device includes an A717 control register and a data transceiver buffer register; wherein the A717 control register includes at least: an ARINC717 bus transceiver rate BR, a voltage slew rate SLEW of the line side HBP and BPRZ signals, an interface type RXSEL of the receiving side line, an A717 transceiver module soft reset SRST, a loopback test TEST, a data transmission start TSTART, a data transmission completion indication TFINISH, and a data reception completion indication RFINISH control bit; The programmable device configures the HI3717 chip according to the working parameter value in the A717 control register to send and receive data from the ARINC717 bus; The CPU only needs to directly read the ARINC717 bus data word from the programmable logic device.
2. A method for improving ARINC717 data transceiver efficiency according to claim 1, characterized in that: The programmable logic device and the CPU use an HPI parallel bus or a PCIe bus for data exchange.
3. A method for improving ARINC717 data transceiver efficiency according to claim 1, characterized in that: The space of the data receiving and sending buffer register facing the CPU in the programmable logic device is enlarged and expanded, further reducing the frequency of the CPU reading and writing ARINC717 bus data.
4. A method for improving ARINC717 data transceiver efficiency according to any one of claims 1 to 3, characterized in that: The process of the CPU receiving data from the programmable logic device includes: The programmable logic device provides a data receiving buffer register space for storing received data according to the maximum subframe word number required by the ARINC717 protocol. After the programmable logic device receives a subframe of ARINC717 data, it immediately sets the data receiving completion indication RFINISH of the A717 control register to 1; The CPU polls and checks RFINISH in the A717 control register at a frequency not lower than a frequency threshold. If RFINISH is detected to be 1, all data of the entire subframe is immediately read out from the data receiving buffer register of the programmable logic device at one time.
5. A method for improving ARINC717 data transceiver efficiency according to any one of claims 1 to 3, characterized in that: The process of the CPU sending data to the programmable logic device includes: The programmable logic device provides a data transmission buffer register space for storing the transmitted data according to the maximum subframe word number required by the ARINC717 protocol. After the programmable logic device sends a subframe of ARINC717 data, it immediately sets the data transmission completion indication TFINISH of the A717 control register to 1; The CPU polls and checks TFINISH in the A717 control register at a frequency not lower than the frequency threshold. If TFINISH is detected to be 1, all data of the entire subframe is immediately written to the data sending buffer register of the programmable logic device at one time, and then TSTART is set to 1.
6. A method for improving ARINC717 data transceiver efficiency according to any one of claims 1 to 3, characterized in that: The process of the programmable logic device receiving data from the HI3717 chip includes: The programmable logic device continuously reads data from the HI3717 chip through the SPI bus, first polls the Receive FIFO Status register of the HI3717 chip to detect whether the receive FIFO has received data, and if the receive FIFO is not empty, writes the word in the receive FIFO of the HI3717 chip into the data receive buffer register of the programmable logic device; There are two data receiving buffer registers implemented inside the programmable logic device, which use a ping-pong mechanism to exchange data with the CPU; the two data receiving buffer registers work simultaneously, and the data receiving buffer register A facing the CPU stores the ARINC717 subframe data read last time, and the other data receiving buffer register B stores the ARINC717 subframe data currently being read from the HI3717 chip; after completing the reception of a subframe data from the HI3717 chip and writing it into the data receiving buffer register B, a ping-pong switch is performed, and the data receiving buffer register B and the data receiving buffer register A swap roles, that is, the data receiving buffer register B storing the subframe data received this time becomes the read buffer register of the CPU, and the data receiving buffer register A becomes the read buffer register of the HI3717 chip, and then the RFINISH of the A717 control register is set to 1 to notify the CPU to read the latest received ARINC717 data.
7. A method for improving ARINC717 data transceiver efficiency according to any one of claims 1 to 3, characterized in that: The process of the programmable logic device sending data to the HI3717 chip includes: The programmable logic device continuously sends data to the HI3717 chip through the SPI bus, first polling the Transmit FIFO Status register of the HI3717 chip to detect whether the transmit FIFO is full, and if the transmit FIFO is not full, taking data from the data transmit buffer register of the programmable logic device and writing it into the transmit FIFO of the HI3717 chip; There are two data transmission buffer registers implemented inside the programmable logic device, which use a ping-pong mechanism to exchange data with the HI3717 chip. The two data transmission buffer registers work simultaneously. The data transmission buffer register A facing the CPU stores the ARINC717 subframe data written by the CPU this time, and the other data transmission buffer register B stores the ARINC717 subframe data currently sent to the HI3717 chip; when the data stored in the data transmission buffer register B is sent to the HI3717 chip, a ping-pong switch is performed, and the data transmission buffer register A and the data transmission buffer register B swap roles, that is, the data transmission buffer register B storing the currently sent subframe data becomes the transmission buffer register of the CPU, and the data transmission buffer register A becomes the transmission buffer register of the HI3717 chip; then the TFINISH of the A717 control register is set to 1 to notify the CPU to write the next ARINC717 subframe data to be sent.
8. A system for improving the efficiency of ARINC717 data transmission and reception, characterized in that: The system comprises: A programmable logic device, wherein the programmable logic device includes an A717 control register and a data transceiver buffer register; The A717 control register at least includes the ARINC717 bus transceiver rate BR, the voltage slew rate SLEW of the line side HBP and BPRZ signals, the interface type RXSEL of the receiving side line, the A717 transceiver module soft reset SRST, the loopback test TEST, the start data transmission TSTART, the data transmission completion indication TFINISH, and the data reception completion indication RFINISH control bits; The programmable logic device configures the HI3717 chip according to the working parameter value in the A717 control register to send and receive data from the ARINC717 bus; The CPU only needs to directly read the ARINC717 bus data word from the programmable logic device.
9. A system for improving ARINC717 data transceiver efficiency according to claim 8, characterized in that: The size of the data transceiver buffer register space is determined by the maximum subframe word number required by the ARINC717 protocol; the CPU checks the parameters in the A717 control register by polling to achieve transceiver control between it and the programmable logic device.
10. A system for improving ARINC717 data transceiver efficiency according to claim 8, characterized in that: The data transceiver buffer register includes two data receiving buffer registers and two data sending buffer registers, wherein the two data receiving buffer registers adopt a ping-pong mechanism to exchange data with the CPU, and the two data sending buffer registers adopt a ping-pong mechanism to exchange data with the CPU; the programmable logic device checks the parameters in the transceiver FIFO status register in the HI3717 chip by polling to realize its transceiver control with the HI3717 chip.