Scanning driving circuit, display device and control method

Abstract

The invention discloses a scanning driving circuit, a display device and a control method, the scanning driving circuit comprises multiple stages of shift registers which are arranged in a cascade mode, the nth stage of shift register in the multiple stages of shift registers comprises an nth stage of shift register unit and an nth stage of control unit, the nth stage of shift register unit is configured to respond to an input signal, and the nth stage of control unit is configured to respond to the input signal. An nth level transmission signal is output at the first output end, an nth level scanning signal is output at the second output end to the first control input end of the nth level control unit, and the second control input end of the nth level control unit is configured to receive a partition control signal; the nth-level control unit is configured to respond to the partition control signal and control the duty ratio on the basis of the nth-level scanning signal, so that the nth-level gate driving signal is output at the first control output end, the switch duty ratio of the pixel driving unit is controlled, the effect of adjusting the refresh rate of each area of the display screen according to the display requirement is achieved, and the display quality is improved. The purpose of reducing display power consumption is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a scan drive circuit, a display device and a control method. Background Art

[0002] Organic Light-Emitting Diode (OLED) display devices have many advantages such as self-luminescence and high contrast, and are a display device with broad application prospects. Currently, active-matrix organic light-emitting diodes or active-matrix organic light-emitting diodes (AMOLED) on the market are used in smart phones, TVs, etc., and continue to develop in the direction of low power consumption, low cost, and large size.

[0003] However, the current AMOLED LTPO 2.0 are all full-screen refresh displays, that is, full-screen 120hz or 60hz or 30hz or 10h or 1hz, etc., which have the problem of single display and are not conducive to reducing the power consumption of the display terminal. Summary of the invention

[0004] In view of the above problems, the present application provides a scan drive circuit, a display device and a control method, aiming to provide a partition refresh solution to solve the problem that the current full-screen refresh display has a single display and is not conducive to reducing power consumption.

[0005] According to a first aspect of an embodiment of the present application, a scan driving circuit is provided, comprising a multi-stage shift register arranged in cascade connection, wherein an n-th stage shift register in the multi-stage shift register comprises:

[0006] An n-th stage shift register unit, comprising a first input terminal, a first output terminal, and a second output terminal, wherein the first input terminal is configured to receive an input signal, and the n-th stage shift register unit is configured to respond to the input signal, output an n-th stage transfer signal at the first output terminal, and output an n-th stage scan signal at the second output terminal, wherein n is an integer greater than zero;

[0007] The n-th level control unit includes a first control input terminal, a second control input terminal and a first control output terminal, the first control input terminal is electrically connected to the second output terminal of the n-th level shift register unit, the second control input terminal is configured to receive a partition control signal, and the n-th level control unit is configured to control the duty cycle based on the n-th level scan signal in response to the partition control signal to output the n-th level gate drive signal at the first control output terminal.

[0008] In some embodiments, the n-th level control unit is configured to output the n-th level gate driving signal having a failure potential in response to a failure potential of at least one of the n-th level scan signal and the partition control signal;

[0009] Preferably, the n-th level control unit is configured to output the n-th level gate driving signal having an effective potential in response to the effective potential of the n-th level scanning signal and the effective potential of the partition control signal;

[0010] Preferably, the effective potential of the n-th level scanning signal, the partition control signal and the n-th level gate driving signal is a high level, and the failure potential of the n-th level scanning signal, the partition control signal and the n-th level gate driving signal is a low level.

[0011] In some embodiments, the multi-stage shift register includes an n+1th stage shift register, and the n+1th stage shift register includes an n+1th stage shift register unit, wherein:

[0012] The first input end of the n+1th shift register unit is electrically connected to the first output end of the nth shift register unit, and the nth stage transmission signal is configured as the input signal of the n+1th shift register unit;

[0013] Preferably, the scan driving circuit is configured with an initial signal, the multi-stage shift register includes a first-stage shift register, the first-stage shift register includes a first-stage shift register unit, wherein the initial signal is configured as the input signal of the first input end of the first-stage shift register unit.

[0014] In some embodiments, the nth level control unit is an nth level AND gate;

[0015] Preferably, the nth level AND gate comprises:

[0016] An n-th level NAND gate, comprising a first logic input terminal, a second logic input terminal and a first logic output terminal, wherein the first logic input terminal of the n-th level NAND gate serves as the second input terminal of the n-th level control unit, and the second logic input terminal of the n-th level NAND gate serves as the third input terminal of the n-th level control unit;

[0017] An n-th stage inverter, comprising a third logic input terminal and a second logic output terminal, the third logic input terminal of the n-th stage inverter is electrically connected to the first logic output terminal of the n-th stage NAND gate, and the second logic output terminal of the n-th stage inverter serves as the third output terminal of the n-th stage control unit;

[0018] Preferably, the n-th level NAND gate and the n-th level inverter are connected in parallel between a first power signal line and a second power signal line, and a first power voltage on the first power signal line and a second power voltage on the second power signal line have different potentials;

[0019] Preferably, the potential of the first power supply voltage is greater than the potential of the second power supply voltage.

[0020] In some embodiments, the n-th stage NAND gate includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor, wherein:

[0021] The first end of the first P-type transistor and the first end of the second P-type transistor are both electrically connected to the first power signal line;

[0022] The second end of the first P-type transistor, the second end of the second P-type transistor and the first end of the first N-type transistor are electrically connected and serve as the first logic output end of the n-th stage NAND gate;

[0023] The second end of the first N-type transistor is electrically connected to the first end of the second N-type transistor, and the second end of the second N-type transistor is electrically connected to the second power signal line;

[0024] The control end of the first P-type transistor is electrically connected to one of the control end of the first N-type transistor and the control end of the second N-type transistor, and serves as the first logic input end of the n-th stage NAND gate; the control end of the second P-type transistor is electrically connected to the other of the control end of the first N-type transistor and the control end of the second N-type transistor, and serves as the second logic input end of the n-th stage NAND gate;

[0025] Preferably, the control end of the first P-type transistor is electrically connected to the control end of the first N-type transistor and serves as the first logic input end of the n-th level NAND gate, and the control end of the second P-type transistor is electrically connected to the control end of the second N-type transistor and serves as the second logic input end of the n-th level NAND gate;

[0026] Preferably, the control end of the first P-type transistor is electrically connected to the control end of the second N-type transistor and serves as the first logic input end of the n-th level NAND gate, and the control end of the second P-type transistor is electrically connected to the control end of the first N-type transistor and serves as the second logic input end of the n-th level NAND gate;

[0027] Preferably, the n-th stage inverter comprises a third P-type transistor and a third N-type transistor, wherein:

[0028] The control end of the third P-type transistor is electrically connected to the control end of the third N-type transistor and serves as the third logic input end of the n-th stage inverter;

[0029] The first end of the third P-type transistor is electrically connected to the first power signal line;

[0030] The second end of the third P-type transistor is electrically connected to the first end of the third N-type transistor and serves as the second logic output end of the n-th stage inverter;

[0031] The second terminal of the third N-type transistor is electrically connected to the second power signal line.

[0032] In some embodiments, the plurality of shift registers are configured with the same partition control signal.

[0033] A second aspect of the embodiments of the present application further provides a display device, including the scan driving circuit as described in any one of the above embodiments, and the display device further includes:

[0034] A plurality of pixel driving units are arranged in a column direction to form a plurality of pixel driving unit rows, and the plurality of pixel driving unit rows correspond to the multi-stage shift registers one by one;

[0035] Wherein, the pixel driving unit includes at least one switching transistor, the multiple rows of pixel driving units include an n-th row of pixel driving units, and the control end of one of the at least one switching transistors of the pixel driving units in the n-th row of pixel driving units is electrically connected to the first control output end of the n-th level control unit of the n-th level shift register and is controlled by the n-th level gate driving signal.

[0036] In some embodiments, the at least one switching transistor includes a data writing transistor, and the pixel driving unit further includes a driving transistor, wherein:

[0037] The first end of the data writing transistor is electrically connected to the control end of the driving transistor, the second end of the data writing transistor is electrically connected to the data signal line, the control end of the data writing transistor is electrically connected to the first control output end of the n-th level control unit of the n-th level shift register, and is controlled by the n-th level gate driving signal.

[0038] A third aspect of the embodiments of the present application further provides a method for controlling a display device, the method being applied to the display device as described in any one of the above embodiments, comprising:

[0039] According to the positions of the plurality of display partitions of the display device in the column direction, the potential jump time of the partition control signal in a display cycle is controlled so that the duty cycles of the gate drive signals received by the pixel drive units located in different display partitions are different.

[0040] In some embodiments, the at least one switch transistor includes a data writing transistor, the pixel driving unit further includes a driving transistor, the data writing transistor is connected between a data signal line and a control terminal of the driving transistor, and the control terminal of the data writing transistor is controlled by the nth level gate driving signal;

[0041] The plurality of display partitions include a first display partition and a second display partition, the first display partition includes a 1st row of pixel driving unit rows to an mth row of pixel driving unit rows, m is less than n, and the one display cycle includes a display frame and at least one holding frame;

[0042] The step of controlling the potential jump time of the partition control signal in one frame display so that the duty cycles of the gate drive signals received by the pixel drive units located in different display partitions are different comprises:

[0043] After the start of at least one holding frame and when the m-th level control unit outputs the m-th level gate drive signal having the same duty cycle as the m-th level scanning signal, the partition control signal is controlled to jump from the effective potential to the failure potential so that the refresh frequency of the multiple pixel driving units located in the first display partition is greater than the refresh frequency of the multiple pixel driving units located in the second display partition.

[0044] The beneficial effects of the embodiments of the present application are as follows: the scan drive circuit includes a multi-stage shift register arranged in cascade, the n-th stage shift register in the multi-stage shift register includes an n-th stage shift register unit and an n-th stage control unit, the first input end of the n-th stage shift register unit is configured to receive an input signal, the n-th stage shift register unit is configured to respond to the input signal, output an n-th stage transmission signal at a first output end, and output an n-th stage scanning signal at a second output end, the second control input end of the n-th stage control unit is configured to receive a partition control signal, the n-th stage control unit is configured to control the duty cycle based on the n-th stage scanning signal in response to the partition control signal, so as to output an n-th stage gate drive signal at the first control output end, thereby controlling the switching duty cycle of the pixel drive unit, achieving the effect of adjusting the refresh rate of each area of ​​the display screen according to display requirements, and achieving the purpose of reducing display power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0046] Figure 1 A schematic diagram of a first structure of a scan driving circuit provided in an embodiment of the present application;

[0047] Figure 2 A second structural schematic diagram of a scan driving circuit provided in an embodiment of the present application;

[0048] Figure 3 A schematic diagram of the first structure of the n-th level control unit provided in an embodiment of the present application;

[0049] Figure 4 A second structural diagram of the n-th level control unit provided in an embodiment of the present application;

[0050] Figure 5 A third structural schematic diagram of the n-th level control unit provided in an embodiment of the present application;

[0051] Figure 6 A schematic diagram of the structure of a pixel driving unit provided in an embodiment of the present application;

[0052] Figure 7 A timing diagram of a scan signal and a gate drive signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0054] In related technologies, AMOLED LTPO 2.0 are all full-screen refresh displays, that is, full-screen 120hz or 60hz or 30hz or 10h or 1hz, etc., which have the problem of single display and are not conducive to reducing the power consumption of the display terminal.

[0055] In order to solve the above technical problems, the embodiment of the present application provides a scanning driving circuit, which is used to control the pixel driving unit 210. Figure 1As shown, the scan driving circuit includes a multi-stage shift register 100 arranged in cascade, and the n-th stage shift register 100 in the multi-stage shift register 100 includes: an n-th stage shift register unit 110 and an n-th stage control unit 120, the n-th stage shift register unit 110 includes a first input terminal, a first output terminal and a second output terminal, the first input terminal is configured to receive an input signal IN, and the n-th stage shift register unit 110 is configured to respond to the input signal IN n, output an n-th stage transmission signal OUT n at its first output terminal, and output an n-th stage scan signal Scan N at its second output terminal, wherein n is an integer greater than zero. The n-th level control unit 120 includes a first control input terminal, a second control input terminal and a first control output terminal. The first control input terminal is electrically connected to the second output terminal of the n-th level shift register unit 110. The second control input terminal is configured to receive a partition control signal SW N. The n-th level control unit 120 is configured to control the duty cycle based on the n-th level scan signal Scan N in response to the partition control signal SW N, so as to output the n-th level gate drive signal Gate N at its first control output terminal.

[0056] In this embodiment, each display pixel includes at least one pixel driving unit 210, the control end of the pixel driving unit 210 is connected to the corresponding shift register 100, the control end of the pixel driving unit 210 is connected to the output end of the corresponding shift register 100, and the switching state of the pixel driving unit 210 is controlled by the corresponding gate driving signal output by the shift register 100, thereby controlling the color or grayscale of the corresponding display pixel.

[0057] A plurality of shift registers 100 are cascaded, and each stage of the shift register 100 includes: a shift register unit 110 and a control unit 120. Each stage of the shift register unit 110 includes a first input terminal, a first output terminal, and a second output terminal. The shift register unit 110 is configured to respond to an input signal input at its first input terminal, and output a corresponding stage transmission signal to the shift register unit 110 in the next stage of the shift register 100 at its first output terminal according to the input signal, and output a corresponding scan signal to the control unit 120 at its second output terminal. The control unit 120 is configured to control the duty cycle based on the received scan signal in response to a partition control signal, for example, the duty cycle of the scan signal is reset by the partition control signal, or the duty cycle of the scan signal is not changed, so that the first control output terminal of the control unit 120 outputs a gate drive signal to the corresponding pixel drive unit 210.

[0058] Combination Figure 1As shown, the n-th stage shift register 100 includes an n-th stage shift register unit 110 and an n-th stage control unit 120, the n-th stage shift register unit 110 includes a first input terminal, a first output terminal and a second output terminal, and the n-th stage control unit 120 includes a first control input terminal, a second control input terminal and a first control output terminal. The first input terminal of the n-th stage shift register unit 110 is configured to receive an input signal IN n, and the n-th stage shift register unit 110 is configured to respond to the input signal IN n, and output the n-th stage transmission signal OUT n from its first output terminal according to the input signal IN n, and output the n-th stage scanning signal Scan N at the second output terminal. The first control input terminal of the n-th stage control unit 120 is electrically connected to the second output terminal of the n-th stage shift register unit 110, and the second control input terminal is configured to receive a partition control signal SW N. The n-th stage control unit 120 is configured to control the duty cycle based on the n-th stage scanning signal Scan N in response to the n-th stage partition control signal SW N, so as to output the n-th stage gate driving signal Gate N at its first control output terminal. By setting the partition control signal SW N of each stage shift register 100, the partition control signal SW N can be controlled according to the partition control signal SW N. N and the scanning signal control the switching duty cycle of the pixel driving unit 210 to achieve the effect of adjusting the refresh rate of each area of ​​the display screen according to the display requirements. In the display area where the display screen does not need to refresh the display image at a high refresh rate, the switching duty cycle of the pixel driving unit 210 in the display area is reduced, so that the display image in the display area can be refreshed at a lower refresh rate, thereby achieving the purpose of reducing display power consumption.

[0059] In some embodiments, in a display area of ​​the display screen that does not need to refresh the display image at a high refresh rate, the refresh rate of the display image in the relevant display area is controlled by the duty cycle of the partition control signal.

[0060] In some embodiments, in a display area of ​​the display screen that does not need to refresh the display image at a high refresh rate, the refresh rate of the display image in the relevant display area is directly proportional to the duty cycle of the partition control signal.

[0061] In some embodiments, the scan drive circuit can be a GIP unit. The GIP (Gate in Panel) technology builds a logic circuit on the glass to control the gate of the pixel drive unit 210, replacing the gate drive IC (integrated circuit) and becoming the main method for narrow frame design, while also reducing IC costs.

[0062] In some embodiments, in combination Figure 1As shown, the nth stage control unit 120 is configured to output the nth stage gate driving signal Gate N having a fail potential in response to a fail potential of at least one of the nth stage scan signal Scan N and the nth stage partition control signal SW N.

[0063] In this embodiment, if any one of the n-th stage scan signal Scan N and the n-th stage partition control signal SW N is configured as a fail potential, then the corresponding n-th stage gate driving signal Gate N is configured as a fail potential.

[0064] Preferably, the nth stage control unit 120 is configured to output the nth stage gate driving signal Gate N having an effective potential in response to the effective potential of the nth stage scan signal Scan N and the effective potential of the nth stage partition control signal SW N.

[0065] In this embodiment, the n-th level scan signal Scan N and the n-th level partition control signal SW N are both configured as effective potentials, and the corresponding n-th level gate driving signal Gate N is configured as an effective potential.

[0066] Preferably, the effective potential of the nth level scan signal Scan N, the nth level partition control signal SW N and the nth level gate drive signal Gate N is a high level, and the failure potential of the nth level scan signal Scan N, the nth level partition control signal SW N and the nth level gate drive signal Gate N is a low level.

[0067] In some embodiments, in combination Figure 2 As shown, the multi-stage shift register 100 includes an n+1-stage shift register 100, and the n+1-stage shift register 100 includes an n+1-stage shift register unit 110, wherein: the first input end of the n+1-stage shift register unit 110 is electrically connected to the first output end of the n-stage shift register unit 110, and the n-stage transfer signal is configured as the input signal of the n+1-stage shift register unit 110.

[0068] Preferably, the scan driving circuit is configured with an initial signal, the multi-stage shift register 100 includes a first-stage shift register 100 , the first-stage shift register 100 includes a first-stage shift register unit 110 , wherein the initial signal is configured as an input signal IN of a first input terminal of the first-stage shift register unit 110 .

[0069] In some embodiments, the 1st-stage shift register 100 further includes a 1st-stage control unit 120. The 1st-stage shift register unit 110 outputs a corresponding 1st-stage transfer signal OUT 1 to the 2nd-stage shift register unit 110 according to the input signal IN 1 at its first input terminal. By analogy, the nth-stage shift register 100 outputs a corresponding nth-stage transfer signal OUT n to the n+1th-stage shift register 100 according to the input signal IN n at its first input terminal. The nth-stage shift register 100 uses the nth-stage transfer signal OUT n outputted from its first output terminal as the n+1th-stage input signal IN n+1 inputted to the first input terminal of the n+1th-stage shift register 100.

[0070] In this embodiment, combined with Figure 2As shown, the n-th stage shift register 100 includes an n-th stage shift register unit 110 and an n-th stage control unit 120, the n-th stage shift register unit 110 includes a first input terminal, a first output terminal and a second output terminal, the n-th stage control unit 120 includes a first control input terminal, a second control input terminal and a first control output terminal, the n+1-th stage shift register 100 includes an n+1-th stage shift register unit 110 and an n+1-th stage control unit 120, the n+1-th stage shift register unit 110 includes a first input terminal, a first output terminal and a second output terminal, the n+1-th stage control unit 120 includes a first control input terminal, a second control input terminal and a first control output terminal, and so on. The first input terminal of the n-th stage shift register unit 110 is configured to receive an input signal, and the n-th stage shift register unit 110 is configured to respond to the input signal, output the n-th stage transmission signal OUT n from its first output terminal according to the input signal, and output the n-th stage scanning signal Scan N at the second output terminal, the first control input terminal of the n-th stage control unit 120 is electrically connected to the second output terminal of the n-th stage shift register unit 110, and the second control input terminal is configured to receive the n-th stage partition control signal SW n, and the n-th stage control unit 120 is configured to control the duty cycle based on the n-th stage scanning signal Scan N in response to the n-th stage partition control signal SW n, so as to output the n-th stage gate driving signal Gate N at its first control output terminal, and the function of the n+1-th stage shift register 100 is the same as that of the n-th stage shift register 100, and the n+1-th stage control unit 120 is configured to respond to the n+1-th stage partition control signal SW N+1, and output the n+1-th stage scanning signal Scan N at the first control output terminal. The duty cycle is controlled on the basis of N+1, so as to output the n+1th level gate driving signal Gate N+1 at its first control output terminal. By setting the partition control signal of each level of the shift register 100, the switching duty cycle of the pixel driving unit 210 can be controlled according to the partition control signal and the scanning signal, so as to achieve the effect of adjusting the refresh rate of each area of ​​the display screen according to the display demand. In the display area where the display screen does not need to be refreshed at a high refresh rate, the switching duty cycle of the pixel driving unit 210 in the display area is reduced, so that the display screen in the display area can be refreshed at a lower refresh rate, thereby achieving the purpose of reducing display power consumption.

[0071] In some embodiments, the n-th stage control unit 120 is an n-th stage AND gate.

[0072] In this embodiment, the first control input terminal and the second control input terminal of the n-th level control unit 120 receive the n-th level scan signal Scan N and the n-th level partition control signal SW N, respectively. The n-th level control unit 120 is an n-th level AND gate, which performs AND logic processing on the n-th level scan signal Scan N and the n-th level partition control signal SW N. If any one of the n-th level scan signal Scan N and the n-th level partition control signal SW N is configured as a low level, the corresponding n-th level gate drive signal Gate N is configured as a low level. If only both the n-th level scan signal Scan N and the n-th level partition control signal SW N are configured as a high level, the corresponding n-th level gate drive signal Gate N is configured as a high level.

[0073] Preferably, combined Figure 3 As shown, the n-th level AND gate includes: an n-th level NAND gate 121n, an n-th level inverter 122n, the n-th level NAND gate 121n includes a first logic input terminal, a second logic input terminal and a first logic output terminal, the first logic input terminal of the n-th level NAND gate 121n serves as a first control input terminal of the n-th level control unit 120, and the second logic input terminal of the n-th level NAND gate 121n serves as a second control input terminal of the n-th level control unit 120; the n-th level inverter 122n includes a third logic input terminal and a second logic output terminal, the third logic input terminal of the n-th level inverter 122n is electrically connected to the first logic output terminal of the n-th level NAND gate 121n, and the second logic output terminal of the n-th level inverter 122n serves as a first control output terminal of the n-th level control unit 120.

[0074] Preferably, the nth NAND gate 121n and the nth inverter 122n are connected in parallel between the first power signal line PVGH and the second power signal line PVGL, and the first power voltage on the first power signal line PVGH and the second power voltage on the second power signal line PVGL have different potentials.

[0075] Preferably, the potential of the first power supply voltage is greater than the potential of the second power supply voltage.

[0076] In some embodiments, in combination Figure 4As shown, the n-th stage NAND gate 121n includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1 and a second N-type transistor N2, wherein: the first end of the first P-type transistor P1 and the first end of the second P-type transistor P2 are both electrically connected to the first power signal line PVGH; the second end of the first P-type transistor P1, the second end of the second P-type transistor P2 and the first end of the first N-type transistor N1 are electrically connected and serve as the first logic output end of the n-th stage NAND gate 121n; the second end of the first N-type transistor N1 is electrically connected to the second N-type transistor P2. A first end of the first N-type transistor N2 is electrically connected, and a second end of the second N-type transistor N2 is electrically connected to the second power signal line PVGL; a control end of the first P-type transistor P1 is electrically connected to one of the control ends of the first N-type transistor N1 and the control ends of the second N-type transistor N2, and serves as a first logic input end of the n-th stage NAND gate 121n, a control end of the second P-type transistor P2 is electrically connected to the other of the control ends of the first N-type transistor N1 and the control ends of the second N-type transistor N2, and serves as a second logic input end of the n-th stage NAND gate 121n.

[0077] In this embodiment, the first P-type transistor P1, the second P-type transistor P2, the first N-type transistor N1 and the second N-type transistor N2 form a NAND gate logic circuit, and perform NAND logic processing on the input scanning signal and the partition control signal. If the level of the scanning signal is low, the second P-type transistor P2 is turned on, the first N-type transistor N1 is turned off, the level of the input end of the n-th stage inverter 122n is high, and the control ends of the first P-type transistor P1 and the second N-type transistor N2 are connected in common, and the switching states of the first P-type transistor P1 and the second N-type transistor N2 are affected by Controlled by the partition control signal, the first P-type transistor P1 is connected to the input end of the n-th inverter 122n, and the second N-type transistor N2 is connected to the input end of the n-th inverter 122n via the first transistor. In this way, the level of the input end of the n-th inverter 122n can be reset by the switching state of the first P-type transistor P1 and the second N-type transistor N2, so as to achieve the purpose of adjusting the level of the gate scanning signal GateN, thereby adjusting the duty cycle of the gate scanning signal GateN and adjusting the refresh rate of the corresponding display area of ​​the display panel.

[0078] In some embodiments, the first P-type transistor P1 and the second P-type transistor P2 may be P-type TFTs, and the first N-type transistor N1 and the second N-type transistor N2 may be N-type TFTs.

[0079] Preferably, combined Figure 4As shown, the control end of the first P-type transistor P1 is electrically connected to the control end of the first N-type transistor N1 and serves as the first logic input end of the n-th stage NAND gate 121n, and the control end of the second P-type transistor P2 is electrically connected to the control end of the second N-type transistor N2 and serves as the second logic input end of the n-th stage NAND gate 121n;

[0080] Preferably, combined Figure 5 As shown, the control end of the first P-type transistor P1 is electrically connected to the control end of the second N-type transistor N2 and serves as the first logic input end of the n-th stage NAND gate 121n, and the control end of the second P-type transistor P2 is electrically connected to the control end of the first N-type transistor N1 and serves as the second logic input end of the n-th stage NAND gate 121n;

[0081] Preferably, combined Figure 4 As shown, the n-th stage inverter 122n includes a third P-type transistor P3 and a third N-type transistor N3, wherein: the control end of the third P-type transistor P3 is electrically connected to the control end of the third N-type transistor N3 and serves as the third logic input end of the n-th stage inverter 122n; the first end of the third P-type transistor P3 is electrically connected to the first power signal line PVGH; the second end of the third P-type transistor P3 is electrically connected to the first end of the third N-type transistor N3 and serves as the second logic output end of the n-th stage inverter 122n; the second end of the third N-type transistor N3 is electrically connected to the second power signal line PVGL.

[0082] In some embodiments, the third P-type transistor P3 may be a P-type TFT, and the third N-type transistor N3 may be an N-type TFT.

[0083] In some embodiments, a plurality of shift registers 100 are configured with the same partition control signal.

[0084] In this embodiment, the plurality of shift registers 100 are configured with the same partition control signal, and the refresh rates of the display pixels corresponding to the plurality of shift registers 100 can be set to the same refresh rate.

[0085] An embodiment of the present application further provides a display device, comprising a scanning driving circuit as in any of the above embodiments, the display device further comprising: a plurality of pixel driving units 210, arranged in a column direction into a plurality of rows of pixel driving units 210, the plurality of rows of pixel driving units 210 corresponding one to one with a multi-stage shift register 100; wherein the pixel driving unit 210 comprises at least one switching transistor, the plurality of rows of pixel driving units 210 comprises an n-th row of pixel driving units 210, a control end of one of the at least one switching transistors of the pixel driving units 210 in the n-th row of pixel driving units 210 is electrically connected to a first control output end of an n-th stage control unit 120 of an n-th stage shift register 100, and is controlled by an n-th stage gate driving signal Gate N.

[0086] In this embodiment, the display device may include a display panel and a scan driving circuit, the display panel includes a plurality of display pixels, each display pixel includes at least one pixel driving unit 210, and the plurality of pixel driving units 210 are arranged in a column direction into a plurality of rows of pixel driving units 210, and the plurality of rows of pixel driving units 210 correspond to the multi-stage shift register 100 one by one. The scan driving circuit receives a scan signal and a partition control signal, and adjusts the duty cycle of the gate scan signal according to the partition control signal, thereby controlling the switch duty cycle of the pixel driving unit 210, achieving the effect of adjusting the refresh rate of each area of ​​the display screen according to the display demand, and achieving the purpose of reducing the display power consumption.

[0087] In some embodiments, in combination Figure 6 As shown, at least one switching transistor includes a data writing transistor 211, and the pixel driving unit 210 also includes a driving transistor 212, wherein: a first end of the data writing transistor 211 is electrically connected to a control end of the driving transistor 212, a second end of the data writing transistor 211 is electrically connected to a data signal line Data N, and a control end of the data writing transistor 211 is electrically connected to a first control output end of an n-th stage control unit 120 of an n-th stage shift register 100, and is controlled by an n-th stage gate driving signal Gate N.

[0088] An embodiment of the present application also provides a control method for a display device, and the control method is applied to a display device as in any of the above embodiments. The control method in this embodiment includes: according to the positions of multiple display partitions of the display device in the column direction, controlling the potential jump time of the partition control signal in a display cycle, so that the duty cycle of the gate drive signal received by the pixel driving unit 210 located in different display partitions is different.

[0089] In this embodiment, the refresh rate of each display partition can be determined by the switching duty cycle of the pixel driving unit 210 of the display partition. The switching duty cycle of the pixel driving unit 210 of different display partitions is determined by the duty cycle of the gate driving signal received by it. Therefore, the refresh rate of the corresponding display partition can be determined by controlling the duty cycle of the scanning signal and the duty cycle of the partition control signal. In addition, the corresponding partition control signal can also be received to selectively reduce the refresh rate of the display screen in the preset low refresh display area.

[0090] In some embodiments, at least one switching transistor includes a data write transistor 211, the pixel driving unit 210 also includes a driving transistor 212, the data write transistor 211 is connected between the data signal line and the control end of the driving transistor 212, and the control end of the data write transistor 211 is controlled by the nth level gate driving signal Gate N; the multiple display partitions include a first display partition and a second display partition, the first display partition includes the 1st row of pixel driving units 210 to the mth row of pixel driving units 210, m is less than n, and a display cycle includes a display frame and at least one holding frame.

[0091] In this embodiment, the refresh rates of the first display partition and the second display partition are determined by the switching duty cycle of the corresponding pixel driving unit 210, and the switching duty cycle of the pixel driving unit 210 is determined by the duty cycle of the gate driving signal. The duty cycle of the gate driving signal can be determined by the switching duty cycle of the partition control signal and the scanning signal. The duty cycles of the gate driving signals received by the pixel driving units 210 in different display partitions are different. In some embodiments, the step of controlling the potential jump time of the partition control signal in a frame display so that the duty cycles of the gate driving signals received by the pixel driving units 210 in different display partitions are different includes:

[0092] After at least one hold frame starts and when the m-th level control unit 120 outputs the m-th level gate drive signal having the same duty cycle as the m-th level scan signal, the control partition control signal jumps from the effective potential to the failure potential so that the refresh frequency of the multiple pixel driving units 210 located in the first display partition is greater than the refresh frequency of the multiple pixel driving units 210 located in the second display partition.

[0093] In this embodiment, the refresh rates of the first display partition and the second display partition can be controlled by corresponding partition control signals. After a frame time starts, and when the m-th level control unit 120 outputs the m-th level gate drive signal having the same duty cycle as the m-th level scanning signal, the control partition control signal jumps from the effective potential to the failure potential, so that the refresh frequency of the multiple pixel driving units 210 located in the first display partition is greater than the refresh frequency of the multiple pixel driving units 210 located in the second display partition, thereby setting the second display partition as a low refresh display area. Figure 7 As shown, when the first-level scan signal Scan1, the second-level scan signal Scan2, the third-level scan signal Scan3, the fourth-level scan signal Scan4, and the fifth-level scan signal Scan5 are scanned step by step and the duty cycle remains unchanged, when the partition scan signal SW jumps to the failure potential (low level), the multiple pixel driving units 210 located in the first display partition are always in the off state. In this way, when the refresh frequency of the first display partition (corresponding to the gate scan signal Gate1, the gate scan signal Gate2, and the gate scan signal Gate3) is greater than the refresh frequency of the multiple pixel driving units 210 located in the second display partition (corresponding to the gate scan signal Gate4, the gate scan signal Gate5, and the gate scan signal Gate6), the area of ​​the gate drive signal is the low refresh rate display area, and the area where the partition scan signal SW is a high level is the high refresh rate display area.

[0094] In some embodiments, the scan drive circuit adjusts the refresh rate of each display area of ​​the display panel according to the corresponding partition control signal. By setting the duty cycle of the partition control signal, the duty cycle of the gate scan signal can be adjusted to adjust the refresh rate of the corresponding display area in the display panel.

[0095] In some embodiments, the main control circuit can provide a corresponding partition control signal to the scan drive circuit according to the content to be displayed on the display panel, so as to adjust the refresh rate of the corresponding display screen. For example, according to the coordinates of the display screen and the refresh rate requirements, by providing the corresponding partition control signal to the scan drive circuit, the refresh rate of the display screen is set according to 60hz-120hz-60hz, 30hz-120hz-30hz, 1hz-120hz-1hz. Specifically, in realizing the function of displaying different refresh rates in multiple areas of the mobile phone, if the mobile phone is watching videos (requiring high refresh rate display) and reading text (low refresh rate display) at the same time, the refresh rate of the text display area in the display screen is set to a low refresh rate (for example, 1Hz, 30Hz, etc.), thereby reducing the power consumption of the display panel without affecting the display effect.

[0096] In some embodiments, the scanning driving circuit can output multiple partition control signals step by step according to the target refresh rate and the refresh rate of the current display screen of the low refresh display area, and gradually reduce the duty cycle of the corresponding partition control signal to the target duty cycle. The target duty cycle of the partition control signal corresponds to the target refresh rate, so that the scanning driving circuit gradually reduces the refresh rate of the current display screen of the low refresh display area to the target refresh rate.

[0097] In some embodiments, the scan drive circuit can also calculate the refresh rate difference between the target refresh rate and the refresh rate of the current display screen of the low refresh display area, and set multiple transition refresh rate values ​​according to the refresh rate difference, and the multiple transition refresh rate values ​​are in an arithmetic progression. In this way, after the scan drive circuit obtains the target gate scanning parameters, it generates multiple continuous partition control signals according to the multiple transition refresh rate values ​​according to the preset scanning cycle, and by adjusting the duty cycle of the partition control signal step by step, the refresh rate of the current display screen of the low refresh display area is gradually reduced to the target refresh rate.

[0098] In some embodiments, a rising edge or a falling edge of the partition control signal is located between a rising edge and a falling edge of the input scan signal.

[0099] In this embodiment, since the switching duty cycle of the pixel driving unit 210 is closely related to the charging time of the corresponding pixel, and the charging time of the pixel is in direct proportion to the grayscale of the pixel, a display pixel can be composed of a red sub-pixel, a green sub-pixel and a blue sub-pixel. If one or more of the sub-pixels have insufficient charging time, the display image will be distorted. In this embodiment, by placing the rising edge or falling edge of the partition control signal between the rising edge and the falling edge of the input scanning signal, the duty cycle of the gate scanning signal can be prevented from causing the display image to be distorted at the moment of switching the refresh rate.

[0100] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A scanning driving circuit, characterized in that: A multi-stage shift register comprising a cascade arrangement, wherein the n-th stage shift register in the multi-stage shift register comprises: An n-th stage shift register unit, comprising a first input terminal, a first output terminal, and a second output terminal, wherein the first input terminal is configured to receive an input signal, and the n-th stage shift register unit is configured to respond to the input signal, output an n-th stage transfer signal at the first output terminal, and output an n-th stage scan signal at the second output terminal, wherein n is an integer greater than zero; The n-th level control unit includes a first control input terminal, a second control input terminal and a first control output terminal, the first control input terminal is electrically connected to the second output terminal of the n-th level shift register unit, the second control input terminal is configured to receive a partition control signal, and the n-th level control unit is configured to control the duty cycle based on the n-th level scan signal in response to the partition control signal to output the n-th level gate drive signal at the first control output terminal.

2. The scanning driving circuit according to claim 1, characterized in that: The n-th level control unit is configured to output the n-th level gate driving signal having a failure potential in response to a failure potential of at least one of the n-th level scan signal and the partition control signal; Preferably, the n-th level control unit is configured to output the n-th level gate driving signal having an effective potential in response to the effective potential of the n-th level scanning signal and the effective potential of the partition control signal; Preferably, the effective potential of the n-th level scanning signal, the partition control signal and the n-th level gate driving signal is a high level, and the failure potential of the n-th level scanning signal, the partition control signal and the n-th level gate driving signal is a low level.

3. The scanning driving circuit according to claim 1, characterized in that: The multi-stage shift register includes an n+1-th stage shift register, and the n+1-th stage shift register includes an n+1-th stage shift register unit, wherein: The first input end of the n+1th shift register unit is electrically connected to the first output end of the nth shift register unit, and the nth stage transmission signal is configured as the input signal of the n+1th shift register unit; Preferably, the scan driving circuit is configured with an initial signal, the multi-stage shift register includes a first-stage shift register, the first-stage shift register includes a first-stage shift register unit, wherein the initial signal is configured as the input signal of the first input terminal of the first-stage shift register unit.

4. The scanning driving circuit according to claim 1, characterized in that: The n-th level control unit is an n-th level AND gate; Preferably, the nth level AND gate comprises: An n-th level NAND gate, comprising a first logic input terminal, a second logic input terminal and a first logic output terminal, wherein the first logic input terminal of the n-th level NAND gate serves as the second input terminal of the n-th level control unit, and the second logic input terminal of the n-th level NAND gate serves as the third input terminal of the n-th level control unit; An n-th stage inverter, comprising a third logic input terminal and a second logic output terminal, the third logic input terminal of the n-th stage inverter is electrically connected to the first logic output terminal of the n-th stage NAND gate, and the second logic output terminal of the n-th stage inverter serves as the third output terminal of the n-th stage control unit; Preferably, the n-th level NAND gate and the n-th level inverter are connected in parallel between a first power signal line and a second power signal line, and a first power voltage on the first power signal line and a second power voltage on the second power signal line have different potentials; Preferably, the potential of the first power supply voltage is greater than the potential of the second power supply voltage.

5. The scanning driving circuit according to claim 4, characterized in that: The n-th level NAND gate includes a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor, wherein: The first end of the first P-type transistor and the first end of the second P-type transistor are both electrically connected to the first power signal line; The second end of the first P-type transistor, the second end of the second P-type transistor and the first end of the first N-type transistor are electrically connected and serve as the first logic output end of the n-th stage NAND gate; The second end of the first N-type transistor is electrically connected to the first end of the second N-type transistor, and the second end of the second N-type transistor is electrically connected to the second power signal line; The control end of the first P-type transistor is electrically connected to one of the control end of the first N-type transistor and the control end of the second N-type transistor, and serves as the first logic input end of the n-th stage NAND gate; the control end of the second P-type transistor is electrically connected to the other of the control end of the first N-type transistor and the control end of the second N-type transistor, and serves as the second logic input end of the n-th stage NAND gate; Preferably, the control end of the first P-type transistor is electrically connected to the control end of the first N-type transistor and serves as the first logic input end of the n-th level NAND gate, and the control end of the second P-type transistor is electrically connected to the control end of the second N-type transistor and serves as the second logic input end of the n-th level NAND gate; Preferably, the control end of the first P-type transistor is electrically connected to the control end of the second N-type transistor and serves as the first logic input end of the n-th level NAND gate, and the control end of the second P-type transistor is electrically connected to the control end of the first N-type transistor and serves as the second logic input end of the n-th level NAND gate; Preferably, the n-th stage inverter comprises a third P-type transistor and a third N-type transistor, wherein: The control end of the third P-type transistor is electrically connected to the control end of the third N-type transistor and serves as the third logic input end of the n-th stage inverter; The first end of the third P-type transistor is electrically connected to the first power signal line; The second end of the third P-type transistor is electrically connected to the first end of the third N-type transistor and serves as the second logic output end of the n-th stage inverter; The second terminal of the third N-type transistor is electrically connected to the second power signal line.

6. The scanning driving circuit according to claim 1, characterized in that: The plurality of shift registers are configured with the same partition control signal.

7. A display device, characterized in that: The display device comprises the scan driving circuit according to any one of claims 1 to 6, and further comprises: A plurality of pixel driving units are arranged in a column direction to form a plurality of pixel driving unit rows, and the plurality of pixel driving unit rows correspond to the multi-stage shift registers one by one; Wherein, the pixel driving unit includes at least one switching transistor, the multiple rows of pixel driving units include an n-th row of pixel driving units, and the control end of one of the at least one switching transistors of the pixel driving units in the n-th row of pixel driving units is electrically connected to the first control output end of the n-th level control unit of the n-th level shift register and is controlled by the n-th level gate driving signal.

8. The display device according to claim 7, characterized in that: The at least one switching transistor includes a data writing transistor, and the pixel driving unit further includes a driving transistor, wherein: The first end of the data writing transistor is electrically connected to the control end of the driving transistor, the second end of the data writing transistor is electrically connected to the data signal line, the control end of the data writing transistor is electrically connected to the first control output end of the n-th level control unit of the n-th level shift register, and is controlled by the n-th level gate driving signal.

9. A method for controlling a display device, characterized in that: The control method is applied to the display device according to any one of claims 7 to 8, comprising: According to the positions of the plurality of display partitions of the display device in the column direction, the potential jump time of the partition control signal in a display cycle is controlled so that the duty cycles of the gate drive signals received by the pixel drive units located in different display partitions are different.

10. The control method according to claim 9, characterized in that: The at least one switch transistor includes a data writing transistor, the pixel driving unit further includes a driving transistor, the data writing transistor is connected between a data signal line and a control terminal of the driving transistor, and the control terminal of the data writing transistor is controlled by the nth level gate driving signal; The plurality of display partitions include a first display partition and a second display partition, the first display partition includes a 1st row of pixel driving unit rows to an mth row of pixel driving unit rows, where m is less than n, and the one display cycle includes a display frame and at least one holding frame, The step of controlling the potential jump time of the partition control signal in one frame display so that the duty cycles of the gate drive signals received by the pixel drive units located in different display partitions are different comprises: After the start of at least one holding frame and when the m-th level control unit outputs the m-th level gate drive signal having the same duty cycle as the m-th level scanning signal, the partition control signal is controlled to jump from the effective potential to the failure potential so that the refresh frequency of the multiple pixel driving units located in the first display partition is greater than the refresh frequency of the multiple pixel driving units located in the second display partition.

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