High-voltage device structure

Abstract

The invention provides a high-voltage device structure, which comprises a substrate and a gate dielectric layer, and is characterized in that the gate dielectric layer is formed in a groove, and the groove is formed in the substrate; the high-voltage P well is formed in the substrate; the first N-type diffusion region is formed in the high-voltage P well at the first side surface of the gate dielectric layer and partially extends to the lower part of the gate dielectric layer; the second N-type diffusion region and the first N-type diffusion region are spaced, and the second N-type diffusion region is formed in the high-voltage P well at the second side surface of the gate dielectric layer and partially extends to the lower part of the gate dielectric layer; the drain end is formed in the surface layer of the first N-type diffusion region; the source end is formed in the surface layer of the second N-type diffusion region; and the gate material layer is formed on the surface of the gate dielectric layer and comprises a first region, a second region and a third region. According to the invention, the problem that the existing parasitic transistor is easy to start in advance is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a high-voltage device structure. Background Art

[0002] OLED (organic light emitting diode) is a current injection composite luminescence type. It has attracted widespread attention due to its advantages such as high brightness, high contrast, wide viewing angle, fast response speed, low operating voltage, strong adaptability, high energy conversion efficiency and simple manufacturing process.

[0003] OLED is current-driven, and its current density depends on the driving voltage at both ends. The higher the voltage, the greater the current density, so it is necessary to introduce high-voltage devices with large reverse bias voltage. However, high-voltage devices are prone to parasitic transistors under high negative voltage, and the parasitic transistors are partially turned on in advance.

[0004] OLED With the advancement of logic device technology nodes, OLED technology combined with advanced technology nodes is being continuously developed. At present, the most advanced mass production technology node is the technology combined with 28nm high dielectric material metal gate (28HV metal Gate), which can take advantage of the high performance and low voltage of advanced nodes. In 28HV MG technology, low-voltage SRAM and high-voltage driver devices need to be integrated, and high voltage requires a thick gate oxide layer as the gate dielectric layer, and a thicker gate oxide layer will affect the subsequent metal gate (Metal gate) subsequent process.

[0005] In order to be compatible with metal gate technology, the high voltage region (HV) will be etched back (Recess) of the active area, and then a thick silicon oxide layer will be grown to make it as consistent as possible with the height of the active area to facilitate subsequent process development. Figure 1 to Figure 3 FIG. 1 is a schematic diagram of a device structure in each step of forming a gate dielectric layer in an existing method for manufacturing a high-voltage device. The steps of forming a gate dielectric layer in an existing method for manufacturing a high-voltage device include:

[0006] like Figure 1 As shown, a substrate 100 is provided, a shallow trench isolation structure 200 is formed in the substrate 100, and the substrate 100 in the area surrounded by the shallow trench isolation structure 200 is an active area 101; a hard mask layer 300 is formed on the surface of the substrate 100, and the material of the hard mask layer 300 is silicon nitride; a photolithography process is performed to form a photoresist pattern 400, and the photoresist pattern is patterned.

[0007] like Figure 2 As shown, the substrate 100 is etched using the patterned photoresist 400 as a mask to form a groove 500 .

[0008] like Figure 3As shown, a dielectric layer 600 is filled in the trench 500 .

[0009] However, since the size of the high-voltage device is large, it needs to be reduced in order to save area. During the reduction process, the thickness of the edge of the gate dielectric layer is larger than the thickness of the central area (such as Figure 3 and Figure 4 As shown in the figure), the problem of premature turning on of the parasitic transistor will be aggravated. Summary of the invention

[0010] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a high-voltage device structure for solving the problem that the prior parasitic transistor is prone to prematurely turn on.

[0011] To achieve the above objectives and other related objectives, the present invention provides a high voltage device structure, comprising:

[0012] Substrate,

[0013] A gate dielectric layer, wherein the gate dielectric layer is formed in a trench, and the trench is formed in the substrate, wherein a thickness of a middle region of the gate dielectric layer is greater than a thickness of an edge region thereof;

[0014] A high-voltage P-well is formed in the substrate;

[0015] a first N-type diffusion region, wherein the first N-type diffusion region is formed in the high-voltage P-well at a first side surface of the gate dielectric layer and partially extends to below the gate dielectric layer;

[0016] a second N-type diffusion region, the second N-type diffusion region being spaced apart from the first N-type diffusion region, formed in the high-voltage P-well at the second side surface of the gate dielectric layer, and partially extending to below the gate dielectric layer;

[0017] A drain terminal, wherein the drain terminal is formed in a surface layer of the first N-type diffusion region;

[0018] A source terminal, the source terminal being formed in a surface layer of the second N-type diffusion region;

[0019] A gate material layer, the gate material layer is formed on the surface of the gate dielectric layer, and includes a first region, a second region and a third region, wherein the second region connects the first region and the third region, and the three are in an I-shape, and the second region is located in a middle region of the gate dielectric layer with a larger thickness, and the length of the second region is smaller than the interval between the first N-type diffusion region and the second N-type diffusion region, and the width of the second region is smaller than the width of the source end or the drain end;

[0020] A P-type diffusion region, the P-type diffusion region is formed in the high-voltage P-well, is annular, and surrounds the first N-type diffusion region and the second N-type diffusion region;

[0021] Wherein, the width of the effective area of ​​the gate material layer is the same as the width of the source end and the drain end.

[0022] Optionally, in the length direction, a distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is greater than a distance b1 between a second edge of the first N-type diffusion region and the P-type diffusion region, wherein the edge of the first region is an edge close to the second region.

[0023] Optionally, in the length direction, a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region is greater than a distance b2 between a second edge of the second N-type diffusion region and the P-type diffusion region, wherein the edge of the third region is an edge close to the second region side.

[0024] Optionally, a distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is equal to a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region.

[0025] Optionally, a distance b1 between the second edge of the first N-type diffusion region and the P-type diffusion region is equal to a distance b2 between the second edge of the second N-type diffusion region and the P-type diffusion region.

[0026] Optionally, a distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is 0.7 um to 1.0 um.

[0027] Optionally, a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region is 0.7 um to 1.0 um.

[0028] Optionally, in the width direction, a distance c between an edge of the second region and an edge of the source terminal / the drain terminal is greater than 1 / 20 of the width of the source terminal / the drain terminal and less than 1 / 10 of the width of the source terminal / the drain terminal.

[0029] Optionally, the structure also includes a shallow trench isolation structure, wherein the shallow trench isolation is formed between the P-type diffusion region and the first N-type diffusion region and the second N-type diffusion region, and is formed within a designated area of ​​the first N-type diffusion region and the second N-type diffusion region and is located between the source terminal / the drain terminal and the gate dielectric layer.

[0030] Optionally, the structure further includes a lead-out region, and the lead-out region is formed in a surface layer of the P-type diffusion region.

[0031] Optionally, the lead-out region is a P+ lead-out region.

[0032] Optionally, the gate material layer is made of polysilicon or metal.

[0033] Optionally, the gate dielectric layer is made of silicon oxide or a material with a high dielectric constant.

[0034] Optionally, the structure further includes sidewall spacers formed on both sides of the gate material layer.

[0035] Optionally, the substrate is a P substrate.

[0036] As described above, the high-voltage device structure of the present invention removes the edge of the gate material layer of the device effective area with the same width as the source and drain, that is, forms a second area with a smaller width, so that the width of the second area is insufficient to form gate coupling, thereby reducing the control of the gate over the edge parasitic transistor, so that the parasitic transistor is not turned on prematurely. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 to Figure 3 The cross-sectional structure schematic diagram of the existing process of forming a gate dielectric layer is shown.

[0038] Figure 4 Shown is an electron microscope image of the existing formed gate dielectric layer.

[0039] Figure 5 Shown is a layout diagram of the high voltage device structure of the present invention.

[0040] Figure 6 Display as Figure 5 The schematic diagram of the cross-sectional structure of the layout shown is taken along A-A'.

[0041] Figure 7 Display as Figure 5 The schematic diagram of the cross-sectional structure of the layout shown is taken along line BB'.

[0042] Description of Figure Numbers

[0043] 10, 100: substrate; 20: gate dielectric layer; 30: high voltage P well; 41: first N-type diffusion region; 41a: first edge of first N-type diffusion region; 41b: second edge of first N-type diffusion region; 42: second N-type diffusion region; 42a: first edge of second N-type diffusion region; 42b: second edge of second N-type diffusion region; 51: drain terminal; 52: source terminal; 60: gate material layer; 61: first region; 62: second region; 63: third region; 70: P-type diffusion region; 71: lead-out region; 80, 200: shallow trench isolation structure; 90: sidewall; 101: active region; 300: hard mask layer; 400: photoresist; 500: trench; 600: dielectric layer DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0046] like Figure 5 to Figure 7 As shown, this embodiment provides a high voltage device structure, the structure comprising:

[0047] Substrate 10,

[0048] A gate dielectric layer 20, wherein the gate dielectric layer 20 is formed in a trench, and the trench is formed in the substrate 10, wherein a thickness of a middle region of the gate dielectric layer 20 is greater than a thickness of an edge region thereof;

[0049] A high-voltage P-well 30 formed in the substrate 10;

[0050] a first N-type diffusion region 41, wherein the first N-type diffusion region 41 is formed in the high-voltage P-well 30 at a first side surface of the gate dielectric layer 20 and partially extends to below the gate dielectric layer 20;

[0051] a second N-type diffusion region 42, which is spaced apart from the first N-type diffusion region 41, is formed in the high-voltage P-well 30 at the second side surface of the gate dielectric layer 20, and partially extends to below the gate dielectric layer 20;

[0052] a drain terminal 51 formed in a surface layer of the first N-type diffusion region 41;

[0053] A source terminal 52, wherein the source terminal 52 is formed in a surface layer of the second N-type diffusion region 52;

[0054] A gate material layer 60, wherein the gate material layer 60 is formed on the surface of the gate dielectric layer 20, and includes a first region 61, a second region 62, and a third region 63, wherein the second region 62 connects the first region 61 and the third region 63, and the three are in an I-shape, and the second region 62 is located in a middle region of the gate dielectric layer 20 where the thickness is relatively large, and the length thereof is smaller than the interval between the first N-type diffusion region 41 and the second N-type diffusion region 42, and the width thereof is smaller than the width of the source terminal 52 or the drain terminal 51;

[0055] A P-type diffusion region 70 , which is formed in the high-voltage P-well 30 , is annular in shape, and surrounds the first N-type diffusion region 41 and the second N-type diffusion region 42 ;

[0056] The width of the effective area of ​​the gate material layer 60 is the same as the width of the source terminal 52 and the drain terminal 51 .

[0057] In this embodiment, Figure 5 The area enclosed by the two green boxes is the P-type diffusion area 70. It should be noted that: Figure 6 and Figure 7 The gate dielectric layer 20 is thicker in the middle region and thinner in the edge region (eg Figure 3 As shown, this shape is not drawn only for the convenience of drawing. Moreover, the reason why the middle region of the gate dielectric layer 20 is thicker and the edge region is thinner is that the substrate at the edge of the active region is warped upward by the influence of the shallow trench isolation structure STI. Therefore, when the gate dielectric layer 20 is formed in the active region, the middle region of the gate dielectric layer 20 is thicker and the edge is thinner. Moreover, in this embodiment, Figure 5 The portion in the black circle is the effective area. The so-called effective area refers to the area where the gate material layer 60 overlaps with the active area. In this area, the gate plays a role in controlling the active area, and is therefore called the effective area.

[0058] Specifically, the substrate 10 is a P substrate.

[0059] Specifically, the gate dielectric layer 20 is made of silicon oxide or a material with a high dielectric constant.

[0060] Specifically, the gate material layer 60 is made of polysilicon or metal.

[0061] Specifically, in the length direction, the distance a1 between the edge of the first region 61 and the first edge 41a of the first N-type diffusion region 41 is greater than the distance b1 between the second edge 41b of the first N-type diffusion region 41 and the P-type diffusion region 70, wherein the edge of the first region 61 is the edge close to the second region 62 side.

[0062] Specifically, in the length direction, the distance a2 between the edge of the third region 63 and the first edge 42a of the second N-type diffusion region 42 is greater than the distance b2 between the second edge 42b of the second N-type diffusion region 42 and the P-type diffusion region 70, wherein the edge of the third region 63 is the edge close to the second region side 62.

[0063] Specifically, a distance a1 between an edge of the first region 61 and a first edge 41 a of the first N-type diffusion region 41 is equal to a distance a2 between an edge of the third region 63 and a first edge 42 a of the second N-type diffusion region 42 .

[0064] Specifically, a distance b1 between the second edge of the first N-type diffusion region 41 and the P-type diffusion region 70 is equal to a distance b2 between the second edge of the second N-type diffusion region 42 and the P-type diffusion region 70 .

[0065] Specifically, a distance a1 between an edge of the first region 61 and a first edge 41 a of the first N-type diffusion region 41 is 0.7 um to 1.0 um.

[0066] Specifically, a distance a2 between the edge of the third region 63 and the first edge 42 a of the second N-type diffusion region 42 is 0.7 um to 1.0 um.

[0067] Specifically, in the width direction, a distance c between an edge of the second region 62 and an edge of the source terminal 52 / the drain terminal 51 is greater than 1 / 20 of the width of the source terminal 52 / the drain terminal 51 and less than 1 / 10 of the width of the source terminal 52 / the drain terminal 51 .

[0068] Specifically, the structure also includes a shallow trench isolation structure 80, and the shallow trench isolation 80 is formed between the P-type diffusion region 70 and the first N-type diffusion region 41 and the second N-type diffusion region 42, and is formed in a designated area of ​​the first N-type diffusion region 41 and the second N-type diffusion region 42 and is located between the source terminal 52 / the drain terminal 51 and the gate dielectric layer 20.

[0069] Specifically, the structure further includes a lead-out region 71 , and the lead-out region 71 is formed in the surface layer of the P-type diffusion region 70 .

[0070] More specifically, the lead-out region 71 is a P+ lead-out region.

[0071] Specifically, the structure further includes sidewall spacers 90 , and the sidewall spacers 90 are formed on both sides of the gate material layer 60 .

[0072] In this embodiment, the substrate 10 in each figure is also represented by P-sub, the high voltage P well 30 is also represented by HVPW, HVPW is the abbreviation of high voltage P type well, the first N type diffusion region 41 and the second N type diffusion region 42 are also represented by HVNDF, HVNDF is the abbreviation of high voltage N type diffusion, the P type diffusion region 70 is also represented by HVPDF, HVPDF is the abbreviation of high voltage P type diffusion; the shallow trench isolation structure is also represented by STI.

[0073] Furthermore, in this embodiment, a metal interconnection layer is formed on the substrate. Figure 6 and Figure 7 The metal interconnection layer is omitted in the figure. The metal interconnection layer will be formed on the multi-layer front metal layer pattern and the through holes connecting the front metal layer patterns of each layer, and finally the source, drain and gate formed by the front metal layer patterning will be formed. The drain terminal will be connected to the drain, the source terminal will be connected to the source, the lead-out area will serve as the substrate electrode (bulk), and the gate material layer will be connected to the gate.

[0074] In summary, the high-voltage device structure of the present invention removes the edge of the gate material layer of the device effective area with the same width as the source and drain, that is, forms a second area with a smaller width, so that the width of the second area is not enough to form the coupling of the gate, thereby reducing the control of the gate on the edge parasitic transistor, so that the parasitic transistor is not turned on in advance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A high voltage device structure, characterized in that: The structure comprises: Substrate, A gate dielectric layer, wherein the gate dielectric layer is formed in a trench, and the trench is formed in the substrate, wherein a thickness of a middle region of the gate dielectric layer is greater than a thickness of an edge region thereof; A high-voltage P-well is formed in the substrate; a first N-type diffusion region, wherein the first N-type diffusion region is formed in the high-voltage P-well at a first side surface of the gate dielectric layer and partially extends to below the gate dielectric layer; a second N-type diffusion region, the second N-type diffusion region being spaced apart from the first N-type diffusion region, formed in the high-voltage P-well at the second side surface of the gate dielectric layer, and partially extending to below the gate dielectric layer; A drain terminal, wherein the drain terminal is formed in a surface layer of the first N-type diffusion region; A source terminal, the source terminal being formed in a surface layer of the second N-type diffusion region; A gate material layer, the gate material layer is formed on the surface of the gate dielectric layer, and includes a first region, a second region and a third region, wherein the second region connects the first region and the third region, and the three are in an I-shape, and the second region is located in a middle region of the gate dielectric layer with a larger thickness, and the length of the second region is smaller than the interval between the first N-type diffusion region and the second N-type diffusion region, and the width of the second region is smaller than the width of the source end or the drain end; A P-type diffusion region, the P-type diffusion region is formed in the high-voltage P-well, is annular, and surrounds the first N-type diffusion region and the second N-type diffusion region; Wherein, the width of the effective area of ​​the gate material layer is the same as the width of the source end and the drain end.

2. The high voltage device structure according to claim 1, characterized in that: In the length direction, a distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is greater than a distance b1 between a second edge of the first N-type diffusion region and the P-type diffusion region, wherein the edge of the first region is the edge close to the second region.

3. The high voltage device structure according to claim 2, characterized in that: In the length direction, a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region is greater than a distance b2 between a second edge of the second N-type diffusion region and the P-type diffusion region, wherein the edge of the third region is an edge close to the second region side.

4. The high voltage device structure according to claim 3, characterized in that: A distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is equal to a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region.

5. The high voltage device structure according to claim 3, characterized in that: A distance b1 between the second edge of the first N-type diffusion region and the P-type diffusion region is equal to a distance b2 between the second edge of the second N-type diffusion region and the P-type diffusion region.

6. The high voltage device structure according to claim 2, characterized in that: A distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is 0.7 um to 1.0 um.

7. The high voltage device structure according to claim 3, characterized in that: A distance a2 between an edge of the third region and a first edge of the second N-type diffusion region is 0.7 um to 1.0 um.

8. The high voltage device structure according to claim 1, characterized in that: In the width direction, a distance c between an edge of the second region and an edge of the source terminal / the drain terminal is greater than 1 / 20 of the width of the source terminal / the drain terminal and less than 1 / 10 of the width of the source terminal / the drain terminal.

9. The high voltage device structure according to claim 1, characterized in that: The structure also includes a shallow trench isolation structure, which is formed between the P-type diffusion region and the first N-type diffusion region and the second N-type diffusion region, and is formed in a designated area of ​​the first N-type diffusion region and the second N-type diffusion region and is located between the source terminal / the drain terminal and the gate dielectric layer.

10. The high voltage device structure according to claim 1, characterized in that: The structure further includes a lead-out region formed in a surface layer of the P-type diffusion region.

11. The high voltage device structure according to claim 10, characterized in that: The lead-out region is a P+ lead-out region.

12. The high voltage device structure according to claim 1, characterized in that: The gate material layer is made of polysilicon or metal.

13. The high voltage device structure according to claim 1, characterized in that: The gate dielectric layer is made of silicon oxide or a material with a high dielectric constant.

14. The high voltage device structure according to claim 1, characterized in that: The structure further includes sidewall spacers formed on both sides of the gate material layer.

15. The high voltage device structure according to claim 1, characterized in that: The substrate is a P substrate.

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