Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

The present invention suppresses variation in characteristics of a device caused by embedding a gate electrode. This nitride semiconductor device is provided with a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a source electrode, a drain electrode, and at least one blind hole extending from the upper surface of the second nitride semiconductor layer to the inside of the first nitride semiconductor layer. A buried gate electrode provided in the blind hole; and a gate finger electrode provided across the upper surface of the buried gate electrode and the upper surface of the second nitride semiconductor layer. The side surface of the blind hole is along the {1-100} plane of the first nitride semiconductor layer.

Description

Technical Field

[0001] The technology disclosed in this application specification relates to nitride semiconductors. Background Art

[0002] As a transistor capable of operating in a high frequency region, there is a high electron mobility transistor (HEMT) using a two-dimensional electron gas (2DEG) generated at a heterojunction interface of a nitride semiconductor having a wurtzite crystal structure.

[0003] Such a nitride semiconductor HEMT is a transistor capable of high-speed and high-output operation due to high 2DEG density and high 2DEG mobility.

[0004] In order to increase the output or high-speed operation of HEMTs using nitride semiconductors, it is effective to reduce the size of the gate electrode and shorten the channel length. On the other hand, shortening the channel length deteriorates the controllability of the drain current under the gate voltage, and the short channel effect becomes prominent.

[0005] As a structure for suppressing the short channel effect, for example, Patent Document 1 or Non-Patent Document 1 discloses a semiconductor device in which a gate electrode is buried and a channel is controlled from two or three directions to control a drain current.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application No. 2020-526921

[0009] Non-patent literature

[0010] Non-patent literature 1: Q. Dai et al., “Deep Sub-60mV / decade Subthreshold Swing inAlGaN / GaN FinMISHFETs with M-Plane Sidewall Channel”, 2019, P1699 Summary of the invention

[0011] The main surface of the nitride semiconductor HEMT is formed as a c-plane ((0 0 0 1) plane), and a channel is formed along the c-plane. Therefore, when forming a buried gate electrode, the gate electrode is buried perpendicularly to the main surface.

[0012] In a nitride semiconductor having a wurtzite crystal structure, the a-plane ({1 1 -2 0} plane) or the m-plane ({1 -1 0 0} plane) which is a crystal plane perpendicular to the main surface has a rotational symmetry of 60°. In addition, in a nitride semiconductor having a wurtzite crystal structure, the chemical resistance of the a-plane is lower than that of the m-plane. Therefore, the a-plane is etched by the solution at a high speed, resulting in deterioration of the surface flatness during chemical vapor deposition.

[0013] In the semiconductor device disclosed in Patent Document 1 or Non-Patent Document 1, the buried gate electrode is circular or rectangular in plan view. In such a structure, in order to form the buried gate electrode, the crystal planes of the side surfaces of the hole provided in the nitride semiconductor are not consistent. That is, when the buried gate electrode is made rectangular, when one side surface is set as an m-plane, the surface opposite to the surface is the m-plane, but the two non-opposing surfaces are the a-planes.

[0014] When the crystal planes of the side surfaces of the holes provided in the nitride semiconductor are not consistent, there is a possibility of processing deviation or deterioration of surface flatness when processing the holes for embedding the gate electrode. In addition, there is a possibility of deterioration of surface flatness in the process after hole processing. These processing deviations cause dimensional deviations of the embedded gate electrode, which is important for channel control.

[0015] The size deviation of the gate electrode causes the threshold deviation between each buried gate electrode, resulting in the deviation of transistor characteristics. In addition, the reduction of surface flatness causes the interface characteristics between the buried gate electrode and the nitride semiconductor to decrease, which reduces the effective mobility. In addition, the reliability of the semiconductor element is reduced due to the reduced adhesion between the buried gate electrode and the nitride semiconductor.

[0016] The technology disclosed in the present specification has been accomplished in view of the above-described problems, and is a technology for suppressing the variation in characteristics of a device caused by embedding a gate electrode.

[0017] A nitride semiconductor device as a first mode of the technology disclosed in the present application specification comprises: a substrate; a first nitride semiconductor layer, arranged on the upper surface of the substrate; a second nitride semiconductor layer, arranged on the upper surface of the first nitride semiconductor layer; a source electrode, arranged on the upper surface of the second nitride semiconductor layer; a drain electrode, arranged on the upper surface of the second nitride semiconductor layer away from the source electrode; at least one blind hole, located between the source electrode and the drain electrode when viewed from above and reaching from the upper surface of the second nitride semiconductor layer to the inside of the first nitride semiconductor layer; a buried gate electrode, arranged in the blind hole; and a gate finger electrode, arranged across the upper surface of the buried gate electrode and the upper surface of the second nitride semiconductor layer, and the side surface of the blind hole is along the {1-1 0 0} plane of the first nitride semiconductor layer.

[0018] According to at least the first embodiment of the technology disclosed in the present specification, since the side surface of the blind hole is along the {1-100} plane, a flat and homogeneous side surface of the nitride semiconductor layer can be obtained. Therefore, the interface characteristics between the buried gate electrode and the side surface of the nitride semiconductor layer can be made uniform, and the characteristic deviation of the device caused by the precision deviation of the hole processing can be suppressed.

[0019] In addition, the purpose, characteristics, aspects, and advantages related to the technology disclosed in the present application specification will become more apparent from the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a perspective view showing an example of the structure of a nitride semiconductor device according to an embodiment.

[0021] Figure 2 is with Figure 1 The nitride semiconductor device shown is a cross-sectional view corresponding to the AA' cross section.

[0022] Figure 3 is with Figure 1 The nitride semiconductor device shown is a cross-sectional view corresponding to the BB' cross section.

[0023] Figure 4 is with Figure 1 A cross-sectional view corresponding to the CC' cross section of the nitride semiconductor device shown.

[0024] Figure 5 is shown with Figure 1 A cross-sectional view of a modified example of the nitride semiconductor device shown is corresponding to a CC' cross section.

[0025] Figure 6 is shown with Figure 1A cross-sectional view of a modified example of the nitride semiconductor device shown is corresponding to a CC' cross section.

[0026] Figure 7 This is a flowchart showing an example of a method for manufacturing a nitride semiconductor device according to an embodiment.

[0027] Figure 8 It is a perspective view showing an example of a process of forming a nitride semiconductor layer and a nitride semiconductor layer on the main surface of a substrate.

[0028] Fig. 9 It is a perspective view showing an example of a process of forming a mask on the upper surface of the nitride semiconductor layer.

[0029] Fig.10 It is a perspective view showing an example of a process of forming a formation region for a buried gate electrode.

[0030] Fig.11 It is a perspective view showing an example of a process of forming a source electrode and a drain electrode.

[0031] Fig.12 It is a perspective view showing an example of a process of forming a buried gate electrode and a gate finger electrode.

[0032] Fig.13 It is a perspective view showing an example of the structure of a nitride semiconductor device according to an embodiment.

[0033] Fig.14 is with Fig.13 The nitride semiconductor device shown is a cross-sectional view corresponding to the AA' cross section.

[0034] Fig.15 is with Fig.13 The nitride semiconductor device shown is a cross-sectional view corresponding to the BB' cross section.

[0035] Fig.16 is with Fig.13 A cross-sectional view corresponding to the CC' cross section of the nitride semiconductor device shown. DETAILED DESCRIPTION

[0036] In the following embodiments, detailed features and the like are shown for explaining the technology, but these are examples, and not all of them are necessarily essential features for implementing the embodiments.

[0037] In addition, the drawings are schematically shown, and for the convenience of explanation, the structure is appropriately omitted or simplified in the drawings. In addition, the size (horizontal and vertical dimensions, etc.) and the relationship between the positions of the structures shown in different drawings may not be accurately recorded and can be appropriately changed. In addition, in drawings such as top views that are not cross-sectional views, hatching is sometimes added to facilitate understanding of the contents of the embodiments.

[0038] In the following description, the same components are shown with the same reference numerals, and their names and functions are the same. Therefore, in order to avoid duplication, their detailed description may be omitted.

[0039] In addition, in the description described in the specification of the present application, when a certain component is described as “having”, “including” or “having”, it is not an exclusive expression excluding the existence of other components unless otherwise specified.

[0040] In addition, in the description recorded in the specification of this application, even if ordinal numbers such as "1st" or "2nd" are used, these terms are used appropriately to make the contents of the implementation method easy to understand, and the contents of the implementation method are not limited to the order that can be generated by these ordinal numbers.

[0041] In addition, in the descriptions recorded in the specification of the present application, expressions indicating an equal state, such as "same", "equal", "uniform" or "homogeneous", etc., unless otherwise specified, include situations in which a state is indicated as being strictly equal and situations in which a tolerance is generated or a difference occurs within a range in which the same degree of functionality can be obtained.

[0042] In addition, in the description recorded in the specification of this application, even if terms such as "upper", "lower", "left", "right", "side", "bottom", "front" or "back" are used to imply specific positions or directions, these terms are used appropriately in order to make the contents of the implementation method easy to understand, and the implementation method has nothing to do with the position or direction during actual implementation.

[0043] In addition, in the descriptions recorded in the specification of the present application, when it is described as "the upper surface of..." or "the lower surface of...", in addition to the upper surface or the lower surface of the target component itself, it also includes a state where other components are formed on the upper surface or the lower surface of the target component. That is, for example, when it is described as "B provided on the upper surface of A", it does not prevent another component "C" from being interposed between A and B.

[0044] In the present specification, "nitride-based semiconductor" is a general term for semiconductors including GaN, AlN, InN, and intermediate compositions thereof.

[0045] <First Embodiment>

[0046] Hereinafter, a nitride semiconductor device and a method for manufacturing the nitride semiconductor device according to the present embodiment will be described.

[0047] <Regarding the Structure of Nitride Semiconductor Device>

[0048] Figure 1 is a perspective view showing an example of the structure of the nitride semiconductor device 100 according to the present embodiment. Figure 2 is with Figure 1 The sectional view corresponds to the AA' section of the nitride semiconductor device 100 shown in FIG. Figure 3 is with Figure 1 The BB' cross-sectional view of the nitride semiconductor device 100 shown in FIG. Figure 4 is with Figure 1 The nitride semiconductor device 100 is shown in a cross-sectional view corresponding to the CC′ cross section.

[0049] like Figure 1 , Figure 2 , Figure 3 as well as Figure 4 By way of example, the nitride semiconductor device 100 of the present embodiment includes a substrate 10, a nitride semiconductor layer 20 arranged on the upper surface of the substrate 10, a nitride semiconductor layer 30 arranged on the upper surface of the nitride semiconductor layer 20, a source electrode 40 arranged on the upper surface of the nitride semiconductor layer 30, a drain electrode 50 arranged on the upper surface of the nitride semiconductor layer 30 so as to be separated from the source electrode 40, a plurality of buried gate electrodes 60 formed between the source electrode 40 and the drain electrode 50 so as to penetrate the nitride semiconductor layer 30 and make the bottom surface contact with the nitride semiconductor layer 20, and a gate finger electrode 70 arranged across the upper surface of the plurality of buried gate electrodes 60 and the upper surface of the nitride semiconductor layer 30.

[0050] In order to form the buried gate electrode 60, at least one blind hole 110 is provided from the upper surface of the nitride semiconductor layer 30 to the inside of the nitride semiconductor layer 20. In the present embodiment, a plurality of blind holes 110 are provided. The buried gate electrode 60 is formed so as to fill the blind holes 110.

[0051] The side surface (i.e. Figure 2 The surface 21a shown, Figure 3The plane 21 shown in FIG. 2 is a plane along the m-plane ({1-1 0 0} plane) of the nitride semiconductor layer 20. The m-plane ({1-1 0 0} plane) is a general term for planes equivalent to (1-1 0 0). That is, the m-plane ({1-1 0 0} plane) includes six planes: (1-1 0 0) plane, (-1 1 0 0) plane, (1 0-1 0) plane, (-1 0 1 0) plane, (0 1 -1 0) plane, and (0 -1 1 0) plane.

[0052] For the substrate 10 , a semiconductor material such as Si, SiC, GaAs, GaN, AlN, InP, or α-Ga 2 O 3 , or an insulating material such as Al 2 O 3 , MgO, or diamond can be used.

[0053] The nitride semiconductor layer 20 is a nitride semiconductor material having a wurtzite crystal structure, such as GaN. The film thickness of the nitride semiconductor layer 20 is, for example, 1 μm.

[0054] The nitride semiconductor layer 30 is made of, for example, Al x Ga 1-x N. The thickness of the nitride semiconductor layer 20 is, for example, 20 nm. As the nitride semiconductor layer 30, a material having a larger band gap than the nitride semiconductor layer 20 can be used to form a heterojunction. For example, by making the nitride semiconductor layer 20 GaN and the nitride semiconductor layer 30 Al x Ga 1-x N can generate a high-density two-dimensional electron gas at the interface between the nitride semiconductor layer 20 and the nitride semiconductor layer 30 , and can form a nitride semiconductor device using the two-dimensional electron gas as a channel.

[0055] A blind hole 110 for forming a buried gate electrode 60 is provided from the upper surface of the nitride semiconductor layer 30 to the inside of the nitride semiconductor layer 20 .

[0056] exist Figure 4 , a hexagonal cross-sectional shape is shown as an example of the cross-sectional shape of the blind hole 110 when viewed from above, but as long as the plane 21 and the plane 21a are m-planes of the nitride semiconductor layer 20, the cross-sectional shape does not necessarily have to be a hexagon.

[0057] Figure 5 as well as Figure 6 is shown with Figure 1 The nitride semiconductor device 100 shown is a cross-sectional view of a modified example corresponding to a CC′ cross section.

[0058] exist Figure 4 In the embodiment, the surfaces 21 form angled surfaces with each other (i.e., they are angled when viewed from above), but they may also be as follows Figure 5 The blind hole 310 shown or Figure 6 The shape of the blind hole 410 is shown. Specifically, Figure 5 For example, when the surface 31a sandwiched by the plurality of embedded gate electrodes 60 in the blind hole 310 is a planar shape, and the surface 31 not sandwiched by the plurality of embedded gate electrodes 60 is a planar shape with a corner, the intersection of the surface 31a and the surface 31 (i.e., the corner) and the corner in the surface 31 may be rounded curved shapes in a plan view. Figure 6 For example, when a surface such as surface 41a sandwiched by multiple embedded gate electrodes 60 in a blind hole 410 is a planar shape with a corner, and a surface such as surface 41 that is not sandwiched by multiple embedded gate electrodes 60 is a planar shape, the part where surface 41a and surface 41 intersect (i.e., the corner) and the corner within surface 41a can also be a rounded curved shape when viewed from above.

[0059] The buried gate electrode 60 penetrates the nitride semiconductor layer 30 in a manner that fills the blind hole 110 of the nitride semiconductor layer 20 and exists halfway to the nitride semiconductor layer 20. The bottom surface of the buried gate electrode 60 exists closer to the substrate 10 side than the interface between the nitride semiconductor layer 20 and the nitride semiconductor layer 30, for example, by 50 nm.

[0060] exist Figure 4 As an example, the buried gate electrode 60 is shown in contact with all the surfaces of the surface 21 and the surface 21a, but the buried gate electrode 60 only needs to be in contact with the surface sandwiched by multiple buried gate electrodes 60, and may not be in contact with the surface not sandwiched by multiple buried gate electrodes 60 (for example, Figure 4 The surfaces shown 21) are in contact.

[0061] In addition, Figure 4 In the embodiment, as an example, a plurality of buried gate electrodes 60 are arranged at equal intervals, but the intervals between the plurality of buried gate electrodes 60 may not be constant. Figure 4 The buried gate electrodes 60 shown are spaced apart from each other by, for example, 200 nm.

[0062] The buried gate electrode 60 forms a Schottky junction with the nitride semiconductor layer 20 and the nitride semiconductor layer 30. The buried gate electrode 60 is formed of a metal, an alloy, a compound containing a metal and a semiconductor, or a semiconductor material doped with impurities. Examples of the metal used in the buried gate electrode 60 include Ti, W, Ni, Pt, and the like.

[0063] The gate finger electrode 70 is as follows Figure 2 As shown in FIG. 1 , a plurality of buried gate electrodes 60 are connected. Figure 3As shown, the gate finger electrode 70 is provided in contact with the upper surface of the nitride semiconductor layer 30. In this case, the channel of the nitride semiconductor device 100 is formed at the interface between the nitride semiconductor layer 20 and the nitride semiconductor layer 30. And, the channel is controlled by the electric field along the Y-axis direction from the buried gate electrode 60 and the electric field along the Z-axis direction from the gate finger electrode 70.

[0064] In addition, a gap may be provided between the gate finger electrode 70 and the nitride semiconductor layer 30. In this case, the channel of the nitride semiconductor device 100 is controlled only by the electric field along the Y-axis direction from the buried gate electrode 60. The gate finger electrode 70 is formed of a metal, an alloy, a compound containing a metal and a semiconductor, or a semiconductor material doped with impurities, which forms an ohmic contact with the buried gate electrode 60. Examples of the metal are Ti, W, Ni, Pt, and the like.

[0065] The source electrode 40 and the drain electrode 50 are disposed on the nitride semiconductor layer 30 in a manner away from the gate finger electrode 70. The source electrode 40 and the drain electrode 50 are formed of metal, alloy, compound containing metal and semiconductor, semiconductor material doped with impurities, etc. The metal used in the source electrode 40 and the drain electrode 50 is, for example, Al, Nb, Pd, etc.

[0066] <About Method for Manufacturing Nitride Semiconductor Device>

[0067] Figure 7 1 is a flowchart showing an example of a method for manufacturing the nitride semiconductor device 100 according to the present embodiment.

[0068] like Figure 7 By way of example, first, in step ST1, a substrate 10 is prepared. For example, the substrate 10 is a 4H-SiC substrate having a wurtzite structure, and the main surface is a (0 0 0 1) plane.

[0069] Next, in step ST2 , the nitride semiconductor layer 20 and the nitride semiconductor layer 30 are formed on the main surface of the substrate 10 by a metal organic vapor deposition method (MOCVD method) or the like.

[0070] Figure 8 1 is a perspective view showing an example of a process of forming a nitride semiconductor layer 20 and a nitride semiconductor layer 30 on a principal surface of a substrate 10. The nitride semiconductor layer 20 having a wurtzite structure is epitaxially grown on the principal surface of the substrate 10 which also has a wurtzite structure, so the principal surface of the nitride semiconductor layer 20 also becomes a (0 0 0 1) plane.

[0071] Next, in step ST3 , a mask 80 is formed on the upper surface of the nitride semiconductor layer 30 .

[0072] Fig. 9 2 is a perspective view showing an example of a process of forming the mask 80 on the upper surface of the nitride semiconductor layer 30. The mask 80 is formed by, for example, the following process.

[0073] First, a mask material is formed on the upper surface of the nitride semiconductor layer 30. As the mask material, for example, a resist such as a photosensitive resin is applied on the upper surface of the nitride semiconductor layer 30. The application method is, for example, spin coating.

[0074] Next, by using a photolithography technique such as optical exposure or electron beam exposure, a mask 80 is formed by opening the resist at a portion corresponding to a region where the buried gate electrode 60 is to be formed.

[0075] For example, an insulator such as SiO or SiN or a metal such as Ti or Ni may be used for the mask 80. In this case, the mask 80 is formed by patterning a mask material such as an insulator or a metal using a resist.

[0076] The insulating material or metal mask material is formed by plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition such as evaporation and sputtering. Next, a resist such as a photosensitive resin is applied on the mask material. The resist coating method is, for example, spin coating. In addition, the resist opening on the area where the buried gate electrode 60 is formed is made by photolithography techniques such as optical exposure or electron beam exposure. Next, the hard mask material on the area where the buried gate electrode 60 is formed is opened by reactive ion etching (RIE) or the like. Next, the resist is removed by ashing using oxygen plasma or solution treatment using an organic solvent or the like, thereby forming a mask 80.

[0077] Next, in step ST4 , the nitride semiconductor layer 30 and the nitride semiconductor layer 20 are etched to form a region where the buried gate electrode 60 is to be formed (a formation region of the buried gate electrode 60 ).

[0078] Fig.10 1 is a perspective view showing an example of a process for forming a formation region of the buried gate electrode 60. Fig.10 For example, the nitride semiconductor layer is etched through the mask 80. The etching method is, for example, reactive ion etching (RIE) including chlorine gas or photoelectrochemical (PEC) etching using a solution including persulfate ions and ultraviolet light.

[0079] The opening shape of the mask 80 is, for example, a hexagon, etc. After the etching of the nitride semiconductor layer 20 , the m-plane of the nitride semiconductor layer 20 is exposed on the side surface in the blind hole 110 .

[0080] On the other hand, when the opening shape of the mask 80 is set to a rectangular or circular shape, the side surface in the opening is exposed to the surface other than the m-plane. In this case, after etching, the m-plane of the nitride semiconductor layer 20 can be exposed by wet etching using a tetramethylammonium hydroxide aqueous solution heated to 80° C. The reason is that in a nitride semiconductor having a wurtzite structure, there is anisotropy of chemical resistance to an aqueous solution of a strong alkali, and the etching rate of the m-plane is the slowest.

[0081] Next, in step ST5 , the source electrode 40 and the drain electrode 50 are formed. Fig.11 4 is a perspective view showing an example of a process of forming the source electrode 40 and the drain electrode 50. Fig.11 For example, a mask 81 having openings corresponding to regions where the source electrode 40 and the drain electrode 50 are to be formed is formed on the upper surface of the nitride semiconductor layer 30. A metal film to be the source electrode 40 and the drain electrode 50 is formed through the mask 81. The metal film is formed by, for example, vapor deposition.

[0082] Next, in step ST6 , the buried gate electrode 60 and the gate finger electrode 70 are formed. Fig.12 1 is a perspective view showing an example of a process of forming the buried gate electrode 60 and the gate finger electrode 70. Fig.12 For example, a mask 82 having openings corresponding to regions where the embedded gate electrode 60 and the gate finger electrode 70 are to be formed is formed on the upper surface of the nitride semiconductor layer 30. A metal film to be the embedded gate electrode 60 and the gate finger electrode 70 is formed through the mask 82. The metal film is formed by, for example, vapor deposition.

[0083] In the nitride semiconductor device 100 having such a buried gate electrode 60, the nitride semiconductor layer 30 forming a channel contacts not only the gate finger electrode 70 on the upper surface but also the buried gate electrode 60 on the side surface. In addition, the nitride semiconductor layer 20 forming a channel contacts the buried gate electrode 60 on the side surface.

[0084] That is, in the nitride semiconductor device 100, the channel formed at the interface between the nitride semiconductor layer 20 and the nitride semiconductor layer 30 is controlled not only by the electric field from the gate finger electrode 70 located on the upper surface of the channel, but also by the electric field from the buried gate electrode 60 located on the side of the channel.

[0085] In the case where the channel is controlled only by the electric field of the gate electrode located on the upper surface, when the gate electrode located on the upper surface is reduced, the controllability of the channel is reduced, and the influence of short channel effects such as the increase in leakage current between the source electrode and the drain electrode, the reduction in subthreshold characteristics, or the change in threshold voltage caused by the drain voltage becomes significant.

[0086] On the other hand, the nitride semiconductor device 100 of this embodiment can control the channel by applying the electric field of the buried gate electrode 60 located on the side of the channel, thereby enabling electric field control from three directions on the channel. Therefore, the controllability of the channel is improved and the influence of the short channel effect can be reduced.

[0087] In a semiconductor device, characteristics of the interface between a semiconductor layer and a gate electrode affect characteristics of the semiconductor device such as a threshold voltage and a subthreshold characteristic.

[0088] In the nitride semiconductor device having the buried gate electrode 60, the gate finger electrode 70 is in contact with the upper surface of the nitride semiconductor layer 30, and the buried gate electrode 60 is in contact with the side surface of the nitride semiconductor layer 20 and the side surface of the nitride semiconductor layer 30. That is, in the nitride semiconductor device having the buried gate electrode 60, it is important to control not only the interface characteristics between the upper surface of the nitride semiconductor layer 30 and the gate finger electrode 70, but also the interface characteristics between the side surface of the nitride semiconductor layer 30 (nitride semiconductor layer 20) and the buried gate electrode 60.

[0089] The etching process of semiconductor materials depends on the chemical and physical properties of the semiconductor material surface. The chemical and physical properties of semiconductor materials vary according to the atomic arrangement of the surface, which varies according to the crystal plane.

[0090] In the nitride semiconductor device having the buried gate electrode 60, in order to form the structure of the buried gate electrode 60, as shown in the above step ST4, hole processing is performed perpendicularly to the c-plane which is the main surface of the nitride semiconductor layer 20 and the nitride semiconductor layer 30. At this time, due to the difference in chemical properties of the crystal plane of the nitride semiconductor, the hole processing is performed in a manner that the m-plane of the nitride semiconductor layer 20 is exposed, so that a flat and homogeneous side surface of the nitride semiconductor layer can be obtained. In addition, as shown in the above step ST4, when wet etching is performed after the hole processing, wet etching is also performed in a manner that the m-plane of the nitride semiconductor layer 20 is exposed, so that a flat and homogeneous side surface of the nitride semiconductor layer can be obtained.

[0091] By making the side surface of the nitride semiconductor layer flat and uniform, the interface characteristics between the buried gate electrode 60 and the side surface of the nitride semiconductor layer can be made uniform.

[0092] In addition, the nitride semiconductor device 100 is provided with a plurality of buried gate electrodes 60, so there are a plurality of interfaces between the side surface of the nitride semiconductor layer 30 (nitride semiconductor layer 20) and the buried gate electrode 60. Therefore, by making the interface characteristics between the side surface of the nitride semiconductor layer and each buried gate electrode 60 uniform, the characteristics of the nitride semiconductor device can be made uniform and the characteristic variation can be suppressed.

[0093] Here, when there are irregularities on the side surface of the nitride semiconductor layer 30 (nitride semiconductor layer 20), a tiny gap is easily generated between the embedded gate electrode 60 and the side surface of the nitride semiconductor layer 30 (nitride semiconductor layer 20). Such a gap may cause the embedded gate electrode 60 to peel off when manufacturing or using the semiconductor device.

[0094] In the nitride semiconductor device 100, a flat side surface of the nitride semiconductor layer 30 (nitride semiconductor layer 20) can be obtained, so the adhesion between the buried gate electrode 60 and the side surface of the nitride semiconductor layer 30 (nitride semiconductor layer 20) can be improved, and the generation of tiny gaps can be suppressed. Therefore, the manufacturing deviation of the nitride semiconductor device can also be suppressed.

[0095] <Second Embodiment>

[0096] In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and their detailed description is appropriately omitted.

[0097] <Regarding the Structure of Nitride Semiconductor Device>

[0098] Fig.13 2 is a perspective view showing an example of the structure of the nitride semiconductor device 200 according to the present embodiment. Fig.14 is with Fig.13 The sectional view corresponds to the AA' section of the nitride semiconductor device 200 shown in FIG. Fig.15 is with Fig.13 The BB' cross-sectional view of the nitride semiconductor device 200 shown in FIG. Fig.16 is with Fig.13 The nitride semiconductor device 200 is shown in a cross-sectional view corresponding to the CC′ cross section.

[0099] like Fig.13 , Fig.14 , Fig.15 as well as Fig.16By way of example, the nitride semiconductor device 200 of the present embodiment comprises: a substrate 10, a nitride semiconductor layer 20 arranged on the upper surface of the substrate 10, a nitride semiconductor layer 30 arranged on the upper surface of the nitride semiconductor layer 20, a source electrode 40 arranged on the upper surface of the nitride semiconductor layer 30, a drain electrode 50 arranged on the upper surface of the nitride semiconductor layer 30 so as to be separated from the source electrode 40, a plurality of buried gate electrodes 60 formed between the source electrode 40 and the drain electrode 50 so as to penetrate the nitride semiconductor layer 30 and make the bottom surface contact with the nitride semiconductor layer 20, and a gate finger electrode 70 arranged across the upper surface of the plurality of buried gate electrodes 60.

[0100] Furthermore, in the present embodiment, in the nitride semiconductor device 200, an insulating film 90 is provided on the surface of the upper surface of the nitride semiconductor layer 30 where the source electrode 40 and the drain electrode 50 are not provided. The insulating film 90 is provided at the interface between the buried gate electrode 60 and the side surface of the nitride semiconductor layer 30 (the side surface in the blind hole 110), the interface between the buried gate electrode 60 and the upper surface and the side surface of the nitride semiconductor layer 20 (the side surface in the blind hole 110), and the interface between the gate finger electrode 70 and the upper surface of the nitride semiconductor layer 30. The buried gate electrode 60 is filled in each blind hole 110 via the insulating film 90.

[0101] The insulating film 90 may exist between the nitride semiconductor layer 30 and the buried gate electrode 60 (i.e., the side surface in the blind hole 110), between the nitride semiconductor layer 20 and the buried gate electrode 60 (i.e., the bottom surface in the blind hole 110), and between the nitride semiconductor layer 30 and the gate finger electrode 70, and may not necessarily cover the entire surface of the nitride semiconductor layer 30. The thickness of the insulating film 90 is, for example, 5 nm. In the insulating film 90, metal oxide materials such as SiO2, Al2O3, HfO2, Gd2O3, Ta2O3, and ZrO2, metal nitride materials such as SiN and AlN, or mixed crystal materials of metal oxides and metal nitrides can be used.

[0102] The insulating film 90 is formed, for example, by the following method. Figure 7 After step ST5 in the flowchart of the method for manufacturing a nitride semiconductor device shown in FIG. 1 , a film of an insulating material is formed by a chemical vapor deposition (CVD) method such as an atomic layer deposition (ALD) method on the upper surface and side surfaces of the nitride semiconductor layer 20 exposed in the formation region of the buried gate electrode 60, the side surfaces of the nitride semiconductor layer 30 exposed in the formation region of the buried gate electrode 60, the upper surface of the nitride semiconductor layer 30, the upper surface of the source electrode 40, and the upper surface of the drain electrode 50.

[0103] Thereafter, by forming a mask pattern and etching using the mask, the insulating material film on the upper surface of the source electrode 40 and the upper surface of the drain electrode 50 is selectively removed.

[0104] In the nitride semiconductor device 200 , an insulating film 90 is provided between the nitride semiconductor layer 30 and the nitride semiconductor layer 20 that form a channel and the buried gate electrode 60 .

[0105] When the insulating film 90 is not provided, the nitride semiconductor layer and the buried gate electrode 60 form a Schottky contact, and a reverse leakage current flows through the Schottky barrier when the channel is cut off, and a forward current flows when the channel is opened.

[0106] Here, by providing the high-resistance insulating film 90 between the nitride semiconductor layer and the buried gate electrode 60 , the resistance between the nitride semiconductor layer and the buried gate electrode 60 is increased, and the current flowing between the nitride semiconductor layer and the buried gate electrode 60 can be reduced.

[0107] By reducing the current flowing between the nitride semiconductor layer and the buried gate electrode 60 , it is possible to reduce the loss of the semiconductor device and improve the power efficiency.

[0108] <Effects Produced by the Multiple Embodiments Described Above>

[0109] Next, examples of the effects produced by the above-described multiple embodiments are shown. In addition, in the following description, the effects are recorded according to the specific structures exemplified by the above-described multiple embodiments, but they can also be replaced with other specific structures exemplified in the specification of this application within the scope of producing the same effects. That is, for the convenience of description, sometimes only one of the corresponding specific structures is recorded representatively, but the specific structure recorded representatively can also be replaced with other corresponding specific structures.

[0110] In addition, the replacement may be performed across a plurality of embodiments. That is, the same effect may be produced by combining the respective structures illustrated in different embodiments.

[0111] According to the above-described embodiment, the nitride semiconductor device includes a substrate 10, a first nitride semiconductor layer, a second nitride semiconductor layer, a source electrode 40, a drain electrode 50, at least one blind hole 110 (or a blind hole 310, a blind hole 410), a buried gate electrode 60, and a gate finger electrode 70. Here, the first nitride semiconductor layer corresponds to, for example, the nitride semiconductor layer 20. In addition, the second nitride semiconductor layer corresponds to, for example, the nitride semiconductor layer 30. The nitride semiconductor layer 20 is provided on the upper surface of the substrate 10. The nitride semiconductor layer 30 is provided on the upper surface of the nitride semiconductor layer 20. The source electrode 40 is provided on the upper surface of the nitride semiconductor layer 30. The drain electrode 50 is provided on the upper surface of the nitride semiconductor layer 30 away from the source electrode 40. The blind hole 110 is located between the source electrode 40 and the drain electrode 50 in a plan view. In addition, the blind hole 110 reaches from the upper surface of the nitride semiconductor layer 30 to the inside of the nitride semiconductor layer 20. The buried gate electrode 60 is disposed in the blind hole 110. The gate finger electrode 70 is disposed across the upper surface of the buried gate electrode 60 and the upper surface of the nitride semiconductor layer 30. Moreover, the side surface of the blind hole 110 is along the {1-100} plane of the nitride semiconductor layer 20.

[0112] According to such a structure, a flat and homogeneous side surface of the nitride semiconductor layer can be obtained by aligning the side surface of the blind hole 110 along the {1-100} plane. Therefore, the interface characteristics between the buried gate electrode 60 and the side surface of the nitride semiconductor layer can be made uniform, and the characteristic deviation of the device caused by the precision deviation of the hole processing can be suppressed.

[0113] Furthermore, even when other structures exemplified in the specification of the present application are appropriately added to the above-mentioned structure, that is, when other structures not mentioned as the above-mentioned structure in the specification of the present application are appropriately added, the same effect can be produced.

[0114] In addition, according to the above-described embodiment, the nitride semiconductor layer 20 has a wurtzite crystal structure. According to such a structure, in a nitride semiconductor having a wurtzite structure, there is anisotropy of chemical resistance to a strong alkali aqueous solution, and the etching rate of the m-plane is the slowest, so by wet etching using a tetramethylammonium hydroxide aqueous solution or the like, the m-plane of the nitride semiconductor layer 20 can be exposed.

[0115] In addition, according to the above-described embodiment, the blind hole 110 is hexagonal in plan view. According to such a structure, the side surface of the blind hole 110 can be used as an m-plane to obtain a flat and homogeneous side surface of the nitride semiconductor layer. Therefore, the interface characteristics between the buried gate electrode 60 and the side surface of the nitride semiconductor layer can be made uniform.

[0116] In addition, according to the above-described embodiment, the blind hole 310 (or the blind hole 410) has a curved shape in a plan view. According to such a structure, the degree of freedom of the shape of the blind hole can be increased.

[0117] In addition, according to the above-described embodiment, the nitride semiconductor device includes an insulating film 90 provided to cover at least a portion of the nitride semiconductor layer 30. Furthermore, the insulating film 90 is provided between the nitride semiconductor layer 30 and the buried gate electrode 60. Furthermore, the insulating film 90 is provided between the nitride semiconductor layer 20 and the buried gate electrode 60. Furthermore, the insulating film 90 is provided between the nitride semiconductor layer 30 and the gate finger electrode 70. According to such a structure, the resistance between the nitride semiconductor layer and the buried gate electrode 60 increases, and the current flowing between the nitride semiconductor layer and the buried gate electrode 60 can be reduced. Furthermore, by reducing the current flowing between the nitride semiconductor layer and the buried gate electrode 60, the loss of the semiconductor device can be reduced, and the power efficiency can be improved.

[0118] According to the above-described embodiment, in the method for manufacturing a nitride semiconductor device, a nitride semiconductor layer 20 is provided on the upper surface of a substrate 10. Furthermore, a nitride semiconductor layer 30 is provided on the upper surface of the nitride semiconductor layer 20. Furthermore, at least one blind hole 110 is formed from the upper surface of the nitride semiconductor layer 30 to the inside of the nitride semiconductor layer 20. Furthermore, a source electrode 40 is provided on the upper surface of the nitride semiconductor layer 30. Furthermore, a drain electrode 50 is provided on the upper surface of the nitride semiconductor layer 30 away from the source electrode 40. Furthermore, an embedded gate electrode 60 is provided in the blind hole 110. Furthermore, a gate finger electrode 70 is provided across the upper surface of the embedded gate electrode 60 and the upper surface of the nitride semiconductor layer 30. Here, the blind hole 110 is located between the source electrode 40 and the drain electrode 50 in a plan view. In addition, the side surface of the blind hole 110 is along the {1-1 0 0} plane of the nitride semiconductor layer 20.

[0119] According to such a structure, a flat and homogeneous side surface of the nitride semiconductor layer can be obtained by aligning the side surface of the blind hole 110 along the {1-100} plane. Therefore, the interface characteristics between the buried gate electrode 60 and the side surface of the nitride semiconductor layer can be made uniform, and the characteristic deviation of the device caused by the precision deviation of the hole processing can be suppressed.

[0120] Furthermore, the order in which each process is performed can be changed without particular limitation.

[0121] In addition, even when other structures exemplified in the specification of the present application are appropriately added to the above-mentioned structure, that is, when other structures not mentioned as the above-mentioned structure in the specification of the present application are appropriately added, the same effect can be produced.

[0122] In addition, according to the above-described embodiment, in the method for manufacturing a nitride semiconductor device, an insulating film 90 is provided on at least the side surface in the blind hole 110. Furthermore, the buried gate electrode 60 is provided in the blind hole 110 via the insulating film 90. According to such a structure, the resistance between the nitride semiconductor layer and the buried gate electrode 60 is increased, and the current flowing between the nitride semiconductor layer and the buried gate electrode 60 can be reduced. Furthermore, by reducing the current flowing between the nitride semiconductor layer and the buried gate electrode 60, the loss of the semiconductor device can be reduced, and the power efficiency can be improved.

[0123] <Regarding Modifications of the Multiple Embodiments Described Above>

[0124] In the above-described embodiments, the material, size, shape, relative arrangement relationship, or implementation conditions of each component may be described, but these are merely examples in all aspects and are not limited thereto.

[0125] Therefore, numerous modifications and equivalents not shown in the examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, the case where at least one component is modified, the case where at least one component is added, or the case where at least one component is omitted, and the case where at least one component in at least one embodiment is extracted and combined with components in other embodiments.

[0126] In at least one embodiment described above, when a material name or the like is described without specifying it, the material may include other additives, such as an alloy, unless there is any contradiction.

[0127] Furthermore, when the above-described embodiment states that “one” component is included, “one or more” of the component may be included unless a contradiction occurs.

[0128] Furthermore, each component in the above-described embodiments is a conceptual unit, and within the scope of the technology disclosed in the present application specification, it includes a case where one component is composed of multiple structures, a case where one component corresponds to a part of a certain structure, and further a case where multiple components are arranged in one structure.

[0129] In addition, as long as the respective components in the above-described embodiments exhibit the same function, structures having other structures or shapes are included.

[0130] In addition, the descriptions in the specification of the present application are referred to for all purposes related to the present technology and are not to be regarded as prior art.

[0131] (Explanation of symbols)

[0132] 10: substrate; 20: nitride semiconductor layer; 21: surface; 21a: surface; 30: nitride semiconductor layer; 31: surface; 31a: surface; 40: source electrode; 41: surface; 41a: surface; 50: drain electrode; 60: buried gate electrode; 70: gate finger electrode; 90: insulating film; 100: nitride semiconductor device; 110: blind hole; 200: nitride semiconductor device; 310: blind hole; 410: blind hole; HEMT: nitride semiconductor.

Claims

1. A nitride semiconductor device comprising: substrate; a first nitride semiconductor layer disposed on the upper surface of the substrate; a second nitride semiconductor layer disposed on an upper surface of the first nitride semiconductor layer; A source electrode is disposed on the upper surface of the second nitride semiconductor layer; a drain electrode disposed on the upper surface of the second nitride semiconductor layer away from the source electrode; at least one blind hole located between the source electrode and the drain electrode in a plan view and extending from the upper surface of the second nitride semiconductor layer to the interior of the first nitride semiconductor layer; A buried gate electrode is disposed in the blind hole; as well as a gate finger electrode provided across the upper surface of the buried gate electrode and the upper surface of the second nitride semiconductor layer, The side surface of the blind hole is along the {1-1 0 0} plane of the first nitride semiconductor layer.

2. The nitride semiconductor device according to claim 1, wherein The first nitride semiconductor layer has a wurtzite crystal structure.

3. The nitride semiconductor device according to claim 1 or 2, wherein: The blind hole is hexagonal in top view.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein: The blind hole has a corner in a plan view, and the corner is curved in a plan view.

5. The nitride semiconductor device according to any one of claims 1 to 4, wherein: further comprising an insulating film provided to cover at least a portion of the second nitride semiconductor layer, The insulating film is provided between the second nitride semiconductor layer and the buried gate electrode, between the first nitride semiconductor layer and the buried gate electrode, and between the second nitride semiconductor layer and the gate finger electrode.

6. The nitride semiconductor device according to any one of claims 1 to 5, wherein: A plurality of blind holes are provided.

7. A method for manufacturing a nitride semiconductor device, A first nitride semiconductor layer is provided on the upper surface of the substrate. A second nitride semiconductor layer is provided on the upper surface of the first nitride semiconductor layer. forming at least one blind hole extending from the upper surface of the second nitride semiconductor layer to the interior of the first nitride semiconductor layer, A source electrode is provided on the upper surface of the second nitride semiconductor layer. A drain electrode is provided on the upper surface of the second nitride semiconductor layer away from the source electrode. A buried gate electrode is provided in the blind hole, A gate finger electrode is provided so as to straddle the upper surface of the buried gate electrode and the upper surface of the second nitride semiconductor layer. The blind hole is located between the source electrode and the drain electrode in a plan view. The side surface of the blind hole is along the {1-1 0 0} plane of the first nitride semiconductor layer.

8. The method for manufacturing a nitride semiconductor device according to claim 7, wherein: An insulating film is also provided on at least one side of the blind hole. The buried gate electrode is disposed in the blind hole via the insulating film.

9. The method for manufacturing a nitride semiconductor device according to claim 7 or 8, wherein: A plurality of blind holes are provided.

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