Method for manufacturing a memory and memory

By introducing an air gap structure between the metal layers of the memory, the RC delay and leakage problems of traditional memory at process nodes below 40 nanometers are solved, the memory's operating speed and storage erase operation time are improved, and more efficient preparation and cost reduction are achieved.

CN119421419BActive Publication Date: 2025-10-10GTA SEMICON CO LTD
2 Cites 0 Cited by

Patent Information

Application Number
CN202411496006.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-10-24
Publication Date
2025-10-10
Estimated Expiration
2044-10-24

AI Technical Summary

Technical Problem

Traditional NOR Flash embedded flash memory technology encounters physical limitations, RC delay and leakage problems at process nodes below 40nm, and the storage erase operation time is long, which cannot meet the mass production requirements of process nodes of 28nm and below.

Method used

A memory preparation method using a new air gap structure introduces an air gap between the metal layers of the memory to reduce RC delay and leakage, thereby improving the operating speed. The method includes steps such as forming a first metal layer, a protective layer, a memory cell array structure, and an oxide layer, and uses chemical vapor deposition and sidewall etching technology to form the air gap.

Benefits of technology

It effectively reduces RC delay and leakage, improves the memory's operating speed and memory erase operation time, reduces preparation costs, and is suitable for mass production of memory at process nodes below 40 nanometers.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The application provides a memory preparation method and a memory. The method comprises the following steps: forming a first metal layer and a first protective layer on one side of the first metal layer; forming a memory cell array structure on a side of the first protective layer away from the first metal layer, the array structure being electrically connected to the first metal layer through a first metal connecting layer; forming a second protective layer on a side of the array structure away from the first metal layer, reducing the thickness of the second protective layer through a sidewall etching technology to obtain a memory cell protective sidewall; filling and forming a third protective layer through a chemical vapor deposition process, the third protective layer being formed with a step structure corresponding to a position between two adjacent memory cells; and depositing an oxidation layer on a side of the third protective layer away from the array structure, an air gap being formed between the oxidation layer and the third protective layer. The application improves the performance and preparation efficiency of the memory.
Need to check novelty before this filing date? Find Prior Art