Storage structure, control method thereof and layout
By designing a storage structure including MOS tubes and ferroelectric field effect tubes, the problem that existing memory still needs to be powered on continuously when power is off is solved, and the function of reading and writing operations without continuous power supply is realized, saving Power consumption.
Patent Information
- Application Number
- CN202310988482.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-07
- Publication Date
- 2025-02-14
AI Technical Summary
Existing memory consumes a high power consumption, especially when power is off, it still needs to be continuously powered on to enable data movement.
A storage structure is designed, including a power terminal, a ground terminal, a MOS tube, a ferroelectric field effect tube and an impedance element. By controlling the state of these components, the function of not requiring continuous power supply during read and write operations is realized.
By utilizing the storage characteristics of the ferroelectric field effect tube, read and write operations without continuous power supply is realized, saving power consumption.
Smart Images
Figure CN119446226A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuits, and in particular to a storage structure and a control method and layout thereof. Background Art
[0002] As the demand for energy conservation continues to increase, OFF-state leakage has become a major challenge facing static random access memory (SRAM) at advanced technology nodes.
[0003] For energy-saving chips such as IoT devices and wearable devices, high density, low power consumption, and general functions are considered key performance parameters. The traditional dual-macro structure (SRAM+NVM) can store data in non-volatile memory (NVM) when the power is off to achieve zero static power consumption. However, when SRAM and NVM use the data bus to achieve data movement, they still need to be powered on continuously, which increases power consumption. Summary of the invention
[0004] The problem solved by the present invention is that the existing memory has high power consumption.
[0005] In order to solve the above problems, the present invention provides a storage structure, including: a power supply end, a ground end, a first MOS tube, a second MOS tube, a first impedance element, a second impedance element, a first ferroelectric field effect tube and a second ferroelectric field effect tube. The first end of the first MOS tube is connected to the first end of the first impedance element, the first end of the first ferroelectric field effect tube and the control end of the second MOS tube, and the second end of the first MOS tube is connected to the ground end. The first end of the second MOS tube is connected to the first end of the second impedance element, the first end of the second ferroelectric field effect tube and the control end of the first MOS tube, and the second end of the second MOS tube is connected to the ground end. The second end of the first impedance element and the second end of the second impedance element are connected to the power supply end.
[0006] Optionally, the first MOS transistor, the second MOS transistor, the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are all N-type transistors.
[0007] Optionally, the storage structure further includes: a third MOS transistor and a fourth MOS transistor. The first end of the third MOS transistor is connected to the second end of the first ferroelectric field effect transistor, and the first end of the fourth MOS transistor is connected to the second end of the second ferroelectric field effect transistor.
[0008] Optionally, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are all N-type transistors.
[0009] Optionally, the storage structure further includes: a word line, a first bit line, a second bit line and a source line. The word line connects the control end of the third MOS tube and the control end of the fourth MOS tube. The first bit line connects the second end of the third MOS tube. The second bit line connects the second end of the fourth MOS tube. The source line connects the control end of the first ferroelectric field effect tube and the control end of the second ferroelectric field effect tube.
[0010] The present invention also provides a control method for the above-mentioned storage structure, comprising: in a standby mode, applying a power supply voltage to the power supply end, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in a conducting state, and the third MOS tube and the fourth MOS tube are both in a cut-off state; in a write mode, applying the power supply voltage to the power supply end, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in a cut-off state, and the third MOS tube and the fourth MOS tube are both in a cut-off state; in a hold mode, stopping applying the power supply voltage to the power supply end, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in a cut-off state, and the third MOS tube and the fourth MOS tube are both in a cut-off state; in a read mode, switching from stopping application to applying the power supply voltage to the power supply end, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in a cut-off state, and the third MOS tube and the fourth MOS tube are both in a conducting state; the standby mode, write mode, hold mode and read mode are executed in sequence.
[0011] Optionally, the control method also includes: in the recovery mode, applying the power supply voltage to the power supply terminal, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in the cut-off state, and the third MOS tube and the fourth MOS tube are both in the cut-off state; the recovery mode is executed later than the read mode.
[0012] The present invention also provides a layout of the above-mentioned storage structure, including: a first fin pattern, a second fin pattern, a third fin pattern, a fourth fin pattern, a first connecting line pattern, a second connecting line pattern, a first gate pattern corresponding to the first MOS tube, a second gate pattern corresponding to the second MOS tube, a third gate pattern corresponding to the third MOS tube, a fourth gate pattern corresponding to the fourth MOS tube, and a first ferroelectric gate pattern corresponding to the first ferroelectric field effect tube, and a second ferroelectric gate pattern corresponding to the second ferroelectric field effect tube; the first fin pattern, the second fin pattern, the third fin pattern and the fourth fin pattern all extend along a first direction; the first ferroelectric gate pattern passes through the first fin pattern along a second direction, and the second direction is perpendicular to the first direction; the third gate pattern is located on a first side of the first ferroelectric gate pattern and extends along the second direction passes through the first fin pattern; the first connecting line pattern is located at the second side of the first ferroelectric gate pattern, and passes through the first fin pattern and the second fin pattern along the second direction; the first gate pattern is located at the first side of the first connecting line pattern, and passes through the second fin pattern and the third fin pattern along the second direction; the second gate pattern is located at the second side of the first connecting line pattern, and passes through the second fin pattern and the third fin pattern along the second direction; the second connecting line pattern is located between the first gate pattern and the second gate pattern, and passes through the third fin pattern and the fourth fin pattern along the second direction; the second ferroelectric gate pattern is located between the second connecting line pattern and the fourth gate pattern, and passes through the fourth fin pattern along the second direction; the fourth gate pattern passes through the fourth fin pattern along the second direction.
[0013] Optionally, the layout of the storage structure also includes: a first grounding pattern and a second grounding pattern; the first grounding pattern is located on the second side of the second gate pattern and passes through the second fin pattern along the second direction, and the first connecting line pattern is located on the first side of the second gate pattern; the second grounding pattern is located on the first side of the first gate pattern and passes through the third fin pattern along the second direction, and the second connecting line pattern is located on the second side of the first gate pattern.
[0014] Optionally, the storage structure also includes: a first bit line and a second bit line, the first bit line is connected to the second end of the third MOS tube, and the second bit line is connected to the second end of the fourth MOS tube; the layout of the storage structure also includes: a first bit line pattern corresponding to the first bit line and a second bit line pattern corresponding to the second bit line; the first bit line pattern is located on the first side of the third gate pattern and passes through the first fin pattern along the second direction, and the first ferroelectric gate pattern is located on the second side of the third gate pattern; the second bit line pattern is located on the second side of the fourth gate pattern and passes through the fourth fin pattern along the second direction, and the second ferroelectric gate pattern is located on the first side of the third gate pattern.
[0015] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0016] By using the storage structure of the present invention, the NVSRAM function is realized, and the read and write operations can be performed normally. In addition, by utilizing the storage characteristics of the first ferroelectric field effect transistor and the second ferroelectric field effect transistor, the power supply end does not need to continuously supply power, thereby saving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a schematic diagram of a storage structure of an embodiment of the present invention;
[0018] Figure 2 is a flow chart of a control method according to an embodiment of the present invention;
[0019] Figure 3 is a signal schematic diagram of a control method according to an embodiment of the present invention;
[0020] Figure 4 It is a schematic diagram of a layout of an embodiment of the present invention. DETAILED DESCRIPTION
[0021] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0022] like Figure 1 As shown, this embodiment provides a storage structure, including: a power supply terminal VCC, a ground terminal VSS, a first MOS transistor T1, a second MOS transistor T2, a first impedance element R1, a second impedance element R2, a first ferroelectric field effect transistor TF1 and a second ferroelectric field effect transistor TF2.
[0023] The first end of the first MOS transistor T1 is connected to the first end of the first impedance element R1, the first end of the first ferroelectric field effect transistor TF1 and the control end of the second MOS transistor T2. The second end of the first MOS transistor T1 is connected to the ground end VSS.
[0024] The first end of the second MOS transistor T2 is connected to the first end of the second impedance element R2, the first end of the second ferroelectric field effect transistor TF2 and the control end of the first MOS transistor T1. The second end of the second MOS transistor T2 is connected to the ground terminal VSS. The second end of the first impedance element R1 and the second end of the second impedance element R2 are connected to the power supply terminal VCC.
[0025] The first ferroelectric field effect transistor TF1 and the second ferroelectric field effect transistor TF2 are based on MOSFET, and use a film layer containing ferroelectric materials as a gate oxide layer. The ferroelectric materials include: HfOSi, HfOZr, HfOAl, etc. The ferroelectric field effect transistor can use the polarization state of the ferroelectric film to modulate the semiconductor surface state, thereby modulating the conduction state between the source and drain of the field effect transistor, distinguishing between logic "0" and "1", so as to achieve the purpose of storing data.
[0026] The storage structure provided in this embodiment is used to implement the NVSRAM function, and normal read and write operations can be performed. In addition, by utilizing the storage characteristics of the first ferroelectric field effect transistor TF1 and the second ferroelectric field effect transistor TF2, the power supply terminal VCC does not need to be continuously powered, further saving power consumption.
[0027] The storage structure may further include: a third MOS transistor T3 and a fourth MOS transistor T4.
[0028] A first end of the third MOS transistor T3 is connected to a second end of the first ferroelectric field effect transistor FT1 , and a first end of the fourth MOS transistor T4 is connected to a second end of the second ferroelectric field effect transistor.
[0029] The first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, the fourth MOS transistor T4, the first ferroelectric field effect transistor TF1 and the second ferroelectric field effect transistor TF2 can all be N-type transistors. Compared with P-type transistors, the work function layer thin film stack thickness requirement is relatively thin, meeting the high-density size requirements, and the carrier mobility is relatively high.
[0030] The memory structure may further include a word line WL, a first bit line BL, a second bit line BLB, and a source line SL.
[0031] The word line WL connects the control end of the third MOS transistor T3 and the control end of the fourth MOS transistor T4. The first bit line BL connects the second end of the third MOS transistor T3. The second bit line BLB connects the second end of the fourth MOS transistor T4. The source line SL connects the control end of the first ferroelectric field effect transistor FT1 and the control end of the second ferroelectric field effect transistor FT2.
[0032] Compared with the traditional SRAM, in this embodiment, the control end of the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 are respectively arranged between the first bit line BL, the second bit line BLB and the internal node, the control end of the first ferroelectric field effect transistor FT1 and the control end of the second ferroelectric field effect transistor FT2 are connected to the source line SL, which is independent of the word line WL, and the first impedance element R1 and the second impedance element R2 are connected in parallel to the power supply terminal VCC. Due to the separate control of the source line SL, the word line WL and the power supply terminal VCC, the foundation is laid for the discontinuous power supply of the power supply terminal VCC.
[0033] Combination Figure 2 and Figure 3 As shown, this embodiment provides a Figure 1 The control method of the storage structure shown in the figure includes: a voltage VL at a first end of a first impedance element R1, a voltage VR at a first end of a second impedance element R2
[0034] Step S1, in standby mode, applying power supply voltage to power supply terminal VCC, making the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 both in the on state, making the third MOS transistor T3 and the fourth MOS transistor T4 both in the off state. At this time, the voltage VL at the first end of the first impedance element R1 is at a high level, and the voltage VR at the first end of the second impedance element R2 is at a low level;
[0035] Step S2, in the write mode, applying the power supply voltage to the power supply terminal VCC, so that the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 are both in the cut-off state, and the third MOS transistor T3 and the fourth MOS transistor T4 are both in the cut-off state. At this time, the voltage VL at the first end of the first impedance element R1 is at a high level, and the voltage VR at the first end of the second impedance element R2 is at a low level;
[0036] Step S3, in the hold mode, stop applying the power supply voltage to the power supply terminal, so that the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 are both in the cut-off state, and the third MOS transistor T3 and the fourth MOS transistor T4 are both in the cut-off state. At this time, the voltage VL at the first end of the first impedance element R1 becomes a low level, and the voltage VR at the first end of the second impedance element R2 is a low level;
[0037] Step S4, in the read mode, switching from stopping application to applying power supply voltage to the power supply terminal, making the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 both in the cut-off state, making the third MOS transistor T3 and the fourth MOS transistor T4 both in the on state. At this time, the voltage VL at the first end of the first impedance element R1 first maintains a low level and then changes to a high level, and the voltage VR at the first end of the second impedance element R2 is a low level; the standby mode, write mode, hold mode and read mode are executed in sequence.
[0038] Still taking the first MOS tube T1, the second MOS tube T2, the third MOS tube T3, the fourth MOS tube T4, the first ferroelectric field effect tube TF1 and the second ferroelectric field effect tube TF2 as N-type tubes as an example, when the control end inputs a high level, they are in the on state, and when the control end inputs a low level, they are in the off state.
[0039] The power supply of the storage structure is controlled by whether the power supply voltage is applied to the power supply terminal VCC, the switching of the on state and the off state of the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 is controlled by the voltage on the source line SL, and the switching of the on state and the off state of the third MOS transistor T3 and the fourth MOS transistor T4 is controlled by the voltage on the word line WL.
[0040] In step S1, in the standby mode, the power supply voltage is applied to the power supply terminal VCC, the source line SL is applied to a high level, and the word line WL is applied to a low level. Therefore, in the standby mode, the storage structure is powered, the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 are both in the on state, and the third MOS transistor T3 and the fourth MOS transistor T4 are both in the off state.
[0041] After the standby mode, the write mode of step S2 is entered, the power supply voltage continues to be applied to the power supply terminal VCC, the voltage on the source line SL changes from a high level to a low level, and the word line WL remains at a low level. Therefore, in the write mode, the storage structure is powered, the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 change from an on state to an off state, and the third MOS transistor T3 and the fourth MOS transistor T4 remain in an off state. It can be seen from the electric polarization intensity curves of the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 that the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 store data.
[0042] After the write mode, the holding mode of step S3 is entered, the power supply voltage is stopped from being applied to the power supply terminal VCC, the source line SL is still at a low level, and the word line WL is also kept at a low level. Therefore, in the holding mode, the storage structure is powered off, and the first ferroelectric field effect transistor FT1, the second ferroelectric field effect transistor FT2, the third MOS transistor T3 and the fourth MOS transistor T4 are all in a cut-off state. Therefore, using the storage structure of this embodiment, after the write operation, the holding mode is entered, and the power supply can be disconnected during the stage where the data is saved to save energy consumption.
[0043] After the hold mode, the read mode of step S4 is entered, the power supply terminal VCC changes from stopping application to applying power supply voltage, the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 are still in the cut-off state, but the third MOS transistor T3 and the fourth MOS transistor T4 enter the conduction state. Therefore, in the read mode, the storage structure is re-powered, the third MOS transistor T3 and the fourth MOS transistor T4 enter the conduction state, and the stored data can be output to the first bit line BL and the second bit line BLB.
[0044] Optionally, the recovery mode is entered after the read mode, and the standby state is entered after the recovery mode. In the recovery mode, a power supply voltage is applied to the power supply terminal VCC, so that the first ferroelectric field effect transistor FT1 and the second ferroelectric field effect transistor FT2 are both in the cut-off state, and the third MOS tube and the fourth MOS tube are both in the cut-off state. At this time, the voltage VL at the first end of the first impedance element R1 is at a high level, and the voltage VR at the first end of the second impedance element R2 is at a low level; the recovery mode is executed later than the read mode.
[0045] It can be seen from the above working process that the storage structure of this embodiment can disconnect the power supply in the holding mode, thereby saving energy consumption.
[0046] like Figure 4 As shown, this embodiment also provides a layout of the above storage structure.
[0047] The layout of the storage structure includes: a first fin pattern 1, a second fin pattern 2, a third fin pattern 3, a fourth fin pattern 4, a first connecting line pattern 11, a second connecting line pattern 12, a first gate pattern T1-1 corresponding to the first MOS transistor T1, a second gate pattern T2-1 corresponding to the second MOS transistor T2, a third gate pattern T3-1 corresponding to the third MOS transistor T3, a fourth gate pattern T4-1 corresponding to the fourth MOS transistor T4, and a first ferroelectric gate pattern TF1-1 corresponding to the first ferroelectric field effect transistor TF1, and a second ferroelectric gate pattern TF2-1 corresponding to the second ferroelectric field effect transistor TF2.
[0048] The first fin pattern 1, the second fin pattern 2, the third fin pattern 3, and the fourth fin pattern 4 all extend along the first direction. The first ferroelectric gate pattern TF1-1 passes through the first fin pattern 1 along the second direction, and the second direction is perpendicular to the first direction. The third gate pattern T3-1 is located on the first side of the first ferroelectric gate pattern TF1-1 and passes through the first fin pattern 1 along the second direction. The first connecting line pattern 11 is located on the second side of the first ferroelectric gate pattern TF1-1 and passes through the first fin pattern 1 and the second fin pattern 2 along the second direction.
[0049] The first gate pattern T1-1 is located at a first side of the first connection line pattern 11 and passes through the second fin pattern 2 and the third fin pattern 3 along the second direction. The second gate pattern T2-1 is located at a second side of the first connection line pattern 11 and passes through the second fin pattern 2 and the third fin pattern 3 along the second direction.
[0050] The second connection line pattern 12 is located between the first gate pattern T1-1 and the second gate pattern T2-1, and passes through the third fin pattern 3 and the fourth fin pattern 4 along the second direction. The second ferroelectric gate pattern TF2-1 is located between the second connection line pattern 12 and the fourth gate pattern T4-1, and passes through the fourth fin pattern 4 along the second direction. The fourth gate pattern T4-1 passes through the fourth fin pattern 4 along the second direction.
[0051] The layout of the memory structure may further include: a first ground pattern VSS1, a second ground pattern VSS2, a first bit line pattern BL-1 corresponding to the first bit line BL, and a second bit line pattern BLB-1 corresponding to the second bit line BLB. The first ground pattern VSS1 and the second ground pattern VSS2 may correspond to the ground terminal VSS.
[0052] The first ground pattern VSS1 is located at the second side of the second gate pattern T2-1 and passes through the second fin pattern 2 along the second direction, and the first connection line pattern 11 is located at the first side of the second gate pattern T2-1. The second ground pattern VSS2 is located at the first side of the first gate pattern T1-1 and passes through the third fin pattern 3 along the second direction, and the second connection line pattern 12 is located at the second side of the first gate pattern T1-1.
[0053] The first bit line pattern BL-1 is located at a first side of the third gate pattern T3-1 and passes through the first fin pattern 1 along the second direction, and the first ferroelectric gate pattern TF1-1 is located at a second side of the third gate pattern T3-1. The second bit line pattern BLB-1 is located at a second side of the fourth gate pattern T4-1 and passes through the fourth fin pattern 4 along the second direction, and the second ferroelectric gate pattern TF2-1 is located at a first side of the third gate pattern T3-1.
[0054] The first ferroelectric field effect transistor and the second ferroelectric field effect transistor in the storage structure of this embodiment can be compatible with the manufacturing process of other MOS transistors, and may include:
[0055] forming a fin corresponding to the fin pattern;
[0056] forming a dummy gate on the fin, wherein the dummy gate comprises a dummy gate electrode and a dummy gate oxide layer;
[0057] forming an insulating layer between the dummy gates;
[0058] removing the dummy gate electrode and the dummy gate oxide layer to form an opening in the insulating layer;
[0059] forming an interface layer, a high-K node layer, and a work function layer in the opening;
[0060] forming a mask, and forming a gate including a ferroelectric material according to the mask;
[0061] After the gate is formed, a connecting line structure and the like are formed.
[0062] The above steps can all be completed using existing processes and will not be described in detail here.
[0063] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A storage structure, characterized in that: include: A power supply terminal, a ground terminal, a first MOS transistor, a second MOS transistor, a first impedance element, a second impedance element, a first ferroelectric field effect transistor, and a second ferroelectric field effect transistor; The first end of the first MOS transistor is connected to the first end of the first impedance element, the first end of the first ferroelectric field effect transistor and the control end of the second MOS transistor, and the second end of the first MOS transistor is connected to the ground end; The first end of the second MOS transistor is connected to the first end of the second impedance element, the first end of the second ferroelectric field effect transistor and the control end of the first MOS transistor, and the second end of the second MOS transistor is connected to the ground end; The second end of the first impedance element and the second end of the second impedance element are connected to the power supply end.
2. The storage structure according to claim 1, characterized in that: The first MOS transistor, the second MOS transistor, the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are all N-type transistors.
3. The storage structure according to claim 1, characterized in that: Also includes: A third MOS tube and a fourth MOS tube; The first end of the third MOS tube is connected to the second end of the first ferroelectric field effect tube, and the first end of the fourth MOS tube is connected to the second end of the second ferroelectric field effect tube.
4. The storage structure according to claim 3, characterized in that: The first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are all N-type transistors.
5. The storage structure according to claim 3, characterized in that: Also includes: a word line, a first bit line, a second bit line and a source line; The word line connects the control end of the third MOS tube and the control end of the fourth MOS tube; The first bit line is connected to the second end of the third MOS tube; The second bit line is connected to the second end of the fourth MOS tube; The source line connects the control end of the first ferroelectric field effect transistor and the control end of the second ferroelectric field effect transistor.
6. A method for controlling the storage structure according to claim 3, characterized in that: include: In the standby mode, a power supply voltage is applied to the power supply terminal, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in a conducting state, and the third MOS transistor and the fourth MOS transistor are both in a cut-off state; In the write mode, the power supply voltage is applied to the power supply terminal, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in the cut-off state, and the third MOS transistor and the fourth MOS transistor are both in the cut-off state; In the holding mode, the power supply voltage is stopped from being applied to the power supply terminal, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in the cut-off state, and the third MOS transistor and the fourth MOS transistor are both in the cut-off state; In the read mode, the power supply voltage is applied to the power supply terminal from the stop state, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in the cut-off state, and the third MOS transistor and the fourth MOS transistor are both in the on state; The standby mode, the write mode, the hold mode, and the read mode are sequentially executed.
7. The control method of the storage structure according to claim 6, characterized in that: Also includes: In the recovery mode, the power supply voltage is applied to the power supply terminal, so that the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are both in the cut-off state, and the third MOS transistor and the fourth MOS transistor are both in the cut-off state; The recovery mode is executed later than the read mode.
8. A layout of the storage structure according to claim 3, characterized in that: include: A first fin pattern, a second fin pattern, a third fin pattern, a fourth fin pattern, a first connecting line pattern, a second connecting line pattern, a first gate pattern corresponding to the first MOS tube, a second gate pattern corresponding to the second MOS tube, a third gate pattern corresponding to the third MOS tube, a fourth gate pattern corresponding to the fourth MOS tube, and a first ferroelectric gate pattern corresponding to the first ferroelectric field effect tube, and a second ferroelectric gate pattern corresponding to the second ferroelectric field effect tube; The first fin pattern, the second fin pattern, the third fin pattern and the fourth fin pattern all extend along a first direction; The first ferroelectric gate pattern passes through the first fin pattern along a second direction, and the second direction is perpendicular to the first direction; The third gate pattern is located at a first side of the first ferroelectric gate pattern and passes through the first fin pattern along the second direction; The first connection line pattern is located at a second side of the first ferroelectric gate pattern and passes through the first fin pattern and the second fin pattern along the second direction; The first gate pattern is located at a first side of the first connection line pattern and passes through the second fin pattern and the third fin pattern along the second direction; The second gate pattern is located at a second side of the first connection line pattern and passes through the second fin pattern and the third fin pattern along the second direction; The second connection line pattern is located between the first gate pattern and the second gate pattern, and passes through the third fin pattern and the fourth fin pattern along the second direction; The second ferroelectric gate pattern is located between the second connection line pattern and the fourth gate pattern, and passes through the fourth fin pattern along the second direction; The fourth gate pattern passes through the fourth fin pattern along the second direction.
9. The layout of the storage structure as claimed in claim 8, characterized in that: Also includes: a first ground pattern and a second ground pattern; The first ground pattern is located at a second side of the second gate pattern and passes through the second fin pattern along the second direction, and the first connection line pattern is located at a first side of the second gate pattern; The second ground pattern is located at a first side of the first gate pattern and passes through the third fin pattern along the second direction. The second connection line pattern is located at a second side of the first gate pattern.
10. The layout of the storage structure as claimed in claim 9, characterized in that: The storage structure further includes: a first bit line and a second bit line, the first bit line is connected to the second end of the third MOS transistor, and the second bit line is connected to the second end of the fourth MOS transistor; The layout of the storage structure further includes: a first bit line pattern corresponding to the first bit line and a second bit line pattern corresponding to the second bit line; The first bit line pattern is located at a first side of the third gate pattern and passes through the first fin pattern along the second direction, and the first ferroelectric gate pattern is located at a second side of the third gate pattern; The second bit line pattern is located at a second side of the fourth gate pattern and passes through the fourth fin pattern along the second direction. The second ferroelectric gate pattern is located at a first side of the third gate pattern.