Decoding circuit and method of Biss-C encoder based on SPI function of ARM kernel

Abstract

The invention relates to a decoding circuit and method of a Biss-C encoder based on an ARM (Advanced RISC Machines) kernel SPI (Serial Peripheral Interface) function, a non-isolated decoding circuit is constructed through an ARM chip, a 422 chip and an encoder, and an isolated decoding circuit is constructed through the ARM chip, a digital isolation circuit, the 422 chip and the encoder. According to the decoding circuit constructed by the invention, the design and development cost of the servo system of the Biss-C protocol encoder is saved. Meanwhile, on the basis that the ARM chip is used for decoding the angle information of the Biss-C protocol, the ARM chip can be used as a main control chip for servo control. Meanwhile, according to the decoding method disclosed by the invention, the data of the Biss-C encoders with various resolutions can be read at a high speed by configuring the SPI of the ARM. The angle information can be reliably and correctly extracted from the Biss-C data packet through displacement, judgment and error verification on software.

Description

Technical Field

[0001] The invention belongs to the technical field of software development, in particular to a decoding circuit and method of a Biss-C encoder based on an ARM core SPI function. Background Art

[0002] The Biss-C protocol is a bidirectional synchronous communication protocol formed by many encoders based on the Biss protocol of IC_haus of Germany. The protocol is designed as a fully digital connection with status bits and check bits to ensure the security and reliability of communication transmission. At the same time, the protocol has low hardware requirements and has been widely used in absolute encoder systems for high-precision position control. Internationally renowned encoder manufacturers such as Renishaw, Heidenhain, and Tamagawa have widely adopted this protocol in their products.

[0003] In high-precision servo control systems, the Biss-C protocol needs to be decoded to obtain the encoder's position information. There are currently two mainstream solutions: the first is a soft decoding solution using FPGA, and the second is a hardware decoding solution using a dedicated decoding chip from Ic-Haus, such as IC-MB4.

[0004] The main control platform of the servo system is usually a DSP chip or an ARM chip, and all control algorithms are in it. Using the first solution for decoding, the data in the FPGA needs to be transmitted to the main control chip through bus transmission, and the bus transmission will occupy a large number of interfaces of the main control chip. Using the second solution for decoding, the angle information of IC-MB4 needs to be read through the main control platform through SPI, and the current procurement cycle of imported chips IC-MB4 is relatively long, which is not friendly to design and development. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a decoding circuit and method for a Biss-C encoder based on the SPI function of the ARM core. By configuring the SPI of the ARM, data of the Biss-C encoder with multiple resolutions can be read at high speed.

[0006] The present invention solves the technical problem by adopting the following technical solutions:

[0007] The decoding circuit of the Biss-C encoder based on the ARM core SPI function includes a non-isolated decoding circuit and an isolated decoding circuit, wherein the non-isolated decoding circuit includes an ARM chip, a 422 chip and an encoder, the SPI_SCK pin of the ARM chip is connected to the transmitting end TX of the 422 chip; the SPI_MISO pin of the ARM chip is connected to the receiving end RX of the 422 chip, the output end Y of the transmitting end TX of the 422 chip is connected to the encoder clock differential interface MA+ through a clock line, and the output end Z of the transmitting end TX of the 422 chip is connected to the encoder clock differential interface MA- through a clock line; the output end B of the transmitting end RX of the 422 chip is connected to the encoder data differential interface CL+ through a data line, and the output end A of the transmitting end RX of the 422 chip is connected to the encoder data differential interface CL- through a data line.

[0008] Moreover, the isolated decoding circuit includes an ARM chip, a digital isolator, a 422 chip and an encoder, the SPI_SCK pin of the ARM chip is connected to the IN-1 pin of the digital isolator, and the OUT-1 pin of the digital isolator is connected to the transmitting end TX of the 422 chip; the SPI_MISO pin of the ARM chip is connected to the IN-2 pin of the digital isolator, the IN-2 pin of the digital isolator is connected to the receiving end RX of the 422 chip, the output end Y of the transmitting end TX of the 422 chip is connected to the encoder clock differential interface MA+ through a clock line, and the output end Z of the transmitting end TX of the 422 chip is connected to the encoder clock differential interface MA- through a clock line; the output end B of the transmitting end RX of the 422 chip is connected to the encoder data differential interface CL+ through a data line, and the output end A of the transmitting end RX of the 422 chip is connected to the encoder data differential interface CL- through a data line.

[0009] A decoding method for a decoding circuit of a Biss-C encoder based on an ARM core SPI function comprises the following steps:

[0010] Step 1: SPI configuration of ARM chip;

[0011] Step 2: According to the SPI configuration of the ARM chip in step 1, process the BISS-C data packet and read the data through SPI.

[0012] Furthermore, the step 1 comprises the following steps:

[0013] Step 1.1, configure the SPI of the ARM chip to master mode;

[0014] Step 1.2, configure the SPI of the ARM chip to collect data when the clock pin is idle high and on the falling edge;

[0015] Step 1.3, configure the data packet of the ARM chip into an 8-bit transmission format for adjusting the data packet;

[0016] Step 1.4, configure the ARM chip's SPI to half-duplex mode - receive only or full-duplex mode for reading data;

[0017] Step 1.5, determine the working rate of SPI according to the working frequency of the encoder;

[0018] Step 1.6: Determine the number of data that SPI reads at one time.

[0019] Furthermore, the step 2 comprises the following steps:

[0020] Step 2.1, build a 64-bit variable temp64, and set the n read in by SPI byte The data is in the following order: rxbuff1, rxbuff2, rxbuff3...rxbuff n ;

[0021] Step 2.2: n byte The data is put into temp64; among them, rxbuff1 is put into the highest 8 bits of temp64, and then put into rxbuff2, rxbuff3, etc. in sequence; if n byte If it is greater than 8, temp64 will be filled up; otherwise, the remaining spaces will be filled with 0;

[0022] Step 2.3, if the highest two bits of temp64 are 1 and the third bit is 0, it means that the data packet is initially correct and proceed to step 2.4, otherwise the data packet is incorrect;

[0023] Step 2.4: The data packet is correct. Skip the first 3 bits of temp64 and shift temp64 left until the starting bit 1 and the subsequent 0 are found. byte If the number of bits shifted to the left is greater than 8, rxbuff9 and rxbuff 10 , …, rxbuff n ;

[0024] Step 2.5, after finding the start bit 1 and the subsequent 0; the following position bit, error bit, warning bit, and 6 bits of CRC are extracted in sequence;

[0025] Step 2.6: If the error bit is 0, it means that there is a problem with the data; if the error bit is 1, it means that the data transmission can be trusted;

[0026] Step 2.7, set the position bit, error bit, and warning bit according to x 6 +x 1 +x 0The CRC check is performed in this way. If the check result is the same as the 6-bit data of the CRC of the data packet, it means that the data received this time is completely correct, otherwise the data received this time is wrong.

[0027] The advantages and positive effects of the present invention are:

[0028] The present invention constructs a non-isolated decoding circuit through an ARM chip, a 422 chip and an encoder, and constructs an isolated decoding circuit through an ARM chip, a digital isolation circuit, a 422 chip and an encoder. The decoding circuit constructed by the present invention saves the design and development cost of the servo system of the Biss-C protocol encoder. At the same time, on the basis of using the ARM chip to decode the Biss-C protocol angle information, the ARM chip can also be used as the main control chip for servo control. At the same time, the decoding method of the present invention can read the data of the Biss-C encoder of various resolutions at high speed by configuring the SPI of the ARM. Through the shifting, judgment and error checking on the software, the angle information can be reliably and correctly extracted from the Biss-C data packet. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a non-isolated decoding circuit diagram of the present invention;

[0030] Figure 2 This is an isolated decoding circuit diagram of the present invention;

[0031] Figure 3 is a timing diagram of the Biss-C protocol of the present invention;

[0032] Figure 4 is a relevant data diagram specified by the Biss-C protocol of the Renishaw encoder in an embodiment of the present invention;

[0033] Figure 5 It is a 64-bit unsigned number variable definition diagram defined by software decoding in an embodiment of the present invention;

[0034] Figure 6 It is a software decoding flow chart of an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention is further described in detail below with reference to the accompanying drawings.

[0036] The decoding circuit of the Biss-C encoder based on the SPI function of the ARM core includes a non-isolated decoding circuit and an isolated decoding circuit.

[0037] like Figure 1As shown, the non-isolated decoding circuit includes an ARM chip, a 422 chip and an encoder, the SPI_SCK pin of the ARM chip is connected to the transmitter TX of the 422 chip; the SPI_MISO pin of the ARM chip is connected to the receiver RX of the 422 chip, the output terminal Y of the transmitter TX of the 422 chip is connected to the encoder clock differential interface MA+ through a clock line, and the output terminal Z of the transmitter TX of the 422 chip is connected to the encoder clock differential interface MA- through a clock line; the output terminal B of the transmitter RX of the 422 chip is connected to the encoder data differential interface CL+ through a data line, and the output terminal A of the transmitter RX of the 422 chip is connected to the encoder data differential interface CL- through a data line.

[0038] like Figure 2 As shown, the isolated decoding circuit includes an ARM chip, a digital isolator, a 422 chip and an encoder, the SPI_SCK pin of the ARM chip is connected to the IN-1 pin of the digital isolator, and the OUT-1 pin of the digital isolator is connected to the transmitter TX of the 422 chip; the SPI_MISO pin of the ARM chip is connected to the IN-2 pin of the digital isolator, and the IN-2 pin of the digital isolator is connected to the receiving end RX of the 422 chip, the output end Y of the transmitter TX of the 422 chip is connected to the encoder clock differential interface MA+ through a clock line, and the output end Z of the transmitter TX of the 422 chip is connected to the encoder clock differential interface MA- through a clock line; the output end B of the transmitter RX of the 422 chip is connected to the encoder data differential interface CL+ through a data line, and the output end A of the transmitter RX of the 422 chip is connected to the encoder data differential interface CL- through a data line.

[0039] A decoding method for a decoding circuit of a Biss-C encoder based on an ARM core SPI function comprises the following steps:

[0040] Step 1: SPI configuration of ARM chip.

[0041] Step 1.1, configure the SPI of the ARM chip to master mode.

[0042] Figure 3 It is a standard BISS-C protocol, MA represents the clock signal, and SL represents the data sent by the encoder. The ARM chip needs to send a clock signal and receive encoder information, so the SPI of the ARM chip needs to be configured as "master device mode".

[0043] Step 1.2: Configure the SPI of the ARM chip so that the clock pin is idle at a high level and collects data on the falling edge.

[0044] according to Figure 3, the clock idle state of the encoder of the BISS protocol is high level, and the data is stable on the falling edge of the clock. Therefore, the SPI of the ARM chip needs to be configured as "clock pin idle high level" and "falling edge data collection".

[0045] Step 1.3: Configure the data packet of the ARM chip into an 8-bit transmission format for data packet adjustment.

[0046] Step 1.4. Configure the ARM chip's SPI to half-duplex mode - receive only or full-duplex mode for reading data.

[0047] Step 1.5: Determine the SPI operating rate according to the encoder's operating frequency.

[0048] Usually, the working frequency of the encoder is limited. This embodiment takes the Renishaw encoder as an example. The Renishaw encoder rate is between 0.5 and 10 MHz. The SPI reading rate should be between the encoder's working rate.

[0049] Step 1.6: Determine the number of data that SPI reads at one time.

[0050] This embodiment takes Renishaw's 26-bit encoder as an example. Figure 4 , except for the uncertain ACK time, the number of clocks for the remaining bits in a BISS-C data packet is certain. Therefore, the number of clocks for a data packet can be conservatively calculated based on the maximum ACK time.

[0051]

[0052] Among them, n sck Represents the number of clocks required to read a data packet, T sck Represents a clock cycle, "2" represents the first two high levels on the data line, and the four "1"s represent the start bit, the start bit followed by 0, the error bit, and the warning bit.

[0053]

[0054] Among them, n byte Represents the number of bytes that ARM's SPI needs to read at one time. SPI works in 8-bit data mode and can only read an integer number of bytes of data at a time.

[0055] Step 2: According to the SPI configuration of the ARM chip in step 1, process the BISS-C data packet and read the data through SPI.

[0056] Step 2.1, build a 64-bit variable temp64, and set the n read in by SPI byteThe data is in the following order: rxbuff1, rxbuff2, rxbuff3...rxbuff n .

[0057] Step 2.2: n byte The data is placed into temp64; Figure 5 As shown, rxbuff1 is put into the highest 8 bits of temp64, and then into rxbuff2, rxbuff3, etc.; if n byte If it is greater than 8, temp64 is filled up; otherwise, the remaining spaces are filled with 0.

[0058] Step 2.3: If the two highest bits of temp64 are 1 and the third bit is 0, it means that the data packet is initially correct and proceed to step 2.4; otherwise, the data packet is incorrect.

[0059] according to Figure 3 In the timing diagram, the first two clocks, the data line is high level 1, and the third clock data line is low level 0, which is the time for ACK to start.

[0060] Step 2.4: The data packet is correct. Because the data read out at the ACK time is all 0, skip the first 3 bits of temp64 and perform a left shift operation on temp64 until the starting bit 1 and the subsequent 0 are found; byte If the number of bits shifted to the left is greater than 8, rxbuff9 and rxbuff 10 , …, rxbuff n .

[0061] Step 2.5, after finding the start bit 1 and the subsequent 0; the following position bit, error bit, warning bit, and 6 bits of CRC are extracted in sequence.

[0062] Step 2.6: If the error bit is 0, it means that there is a problem with the data; if the error bit is 1, it means that the data transmission can be trusted.

[0063] Step 2.7, set the position bit, error bit, and warning bit according to x 6 +x 1 +x 0 The CRC check is performed in this way. If the check result is the same as the 6-bit data of the CRC of the data packet, it means that the data received this time is completely correct, otherwise the data received this time is wrong.

[0064] The present invention constructs a non-isolated decoding circuit through an ARM chip, a 422 chip and an encoder, and constructs an isolated decoding circuit through an ARM chip, a digital isolation circuit, a 422 chip and an encoder. The decoding circuit constructed by the present invention saves the design and development cost of the servo system of the Biss-C protocol encoder. At the same time, on the basis of using the ARM chip to decode the Biss-C protocol angle information, the ARM chip can also be used as the main control chip for servo control. At the same time, the decoding method of the present invention can read the data of the Biss-C encoder of various resolutions at high speed by configuring the SPI of the ARM. Through the shifting, judgment and error checking on the software, the angle information can be reliably and correctly extracted from the Biss-C data packet.

[0065] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. The decoding circuit of Biss-C encoder based on ARM core SPI function is characterized by: It includes a non-isolated decoding circuit and an isolated decoding circuit, wherein the non-isolated decoding circuit includes an ARM chip, a 422 chip and an encoder, the SPI_SCK pin of the ARM chip is connected to the transmitting end TX of the 422 chip; the SPI_MISO pin of the ARM chip is connected to the receiving end RX of the 422 chip, the output end Y of the transmitting end TX of the 422 chip is connected to the encoder clock differential interface MA+ through a clock line, and the output end Z of the transmitting end TX of the 422 chip is connected to the encoder clock differential interface MA- through a clock line; the output end B of the transmitting end RX of the 422 chip is connected to the encoder data differential interface CL+ through a data line, and the output end A of the transmitting end RX of the 422 chip is connected to the encoder data differential interface CL- through a data line.

2. The decoding circuit of the Biss-C encoder based on the ARM core SPI function according to claim 1, characterized in that: The isolated decoding circuit includes an ARM chip, a digital isolator, a 422 chip and an encoder, the SPI_SCK pin of the ARM chip is connected to the IN-1 pin of the digital isolator, the OUT-1 pin of the digital isolator is connected to the transmitting end TX of the 422 chip; the SPI_MISO pin of the ARM chip is connected to the IN-2 pin of the digital isolator, the IN-2 pin of the digital isolator is connected to the receiving end RX of the 422 chip, the output end Y of the transmitting end TX of the 422 chip is connected to the encoder clock differential interface MA+ through a clock line, and the output end Z of the transmitting end TX of the 422 chip is connected to the encoder clock differential interface MA- through a clock line; the output end B of the transmitting end RX of the 422 chip is connected to the encoder data differential interface CL+ through a data line, and the output end A of the transmitting end RX of the 422 chip is connected to the encoder data differential interface CL- through a data line.

3. A decoding method of a decoding circuit of a Biss-C encoder based on the ARM core SPI function according to any one of claims 1 to 2, characterized in that: The following steps are involved: Step 1: SPI configuration of ARM chip; Step 2: According to the SPI configuration of the ARM chip in step 1, process the BISS-C data packet and read the data through SPI.

4. The decoding method of the decoding circuit of the Biss-C encoder based on the ARM core SPI function according to claim 3, characterized in that: The step 1 comprises the following steps: Step 1.1, configure the SPI of the ARM chip to master device mode; Step 1.2, configure the SPI of the ARM chip to collect data when the clock pin is idle high and on the falling edge; Step 1.3, configure the data packet of the ARM chip into an 8-bit transmission format for adjusting the data packet; Step 1.4, configure the SPI of the ARM chip to half-duplex mode - receive only or full-duplex mode for reading data; Step 1.5, determine the working rate of SPI according to the working frequency of the encoder; Step 1.6: Determine the number of data that SPI reads at one time.

5. The decoding method of the decoding circuit of the Biss-C encoder based on the ARM core SPI function according to claim 1, characterized in that: The step 2 comprises the following steps: Step 2.1, build a 64-bit variable temp64, and set the n read in by SPI byte The data is in the following order: rxbuff1, rxbuff2, rxbuff3...rxbuff n ; Step 2.2: n byte The data is put into temp64; among them, rxbuff1 is put into the highest 8 bits of temp64, and then put into rxbuff2, rxbuff3, etc. in sequence; if n byte If it is greater than 8, temp64 will be filled up; otherwise, the remaining spaces will be filled with 0; Step 2.3, if the highest two bits of temp64 are 1 and the third bit is 0, it means that the data packet is initially correct and proceed to step 2.4, otherwise the data packet is incorrect; Step 2.4: The data packet is correct. Skip the first 3 bits of temp64 and shift temp64 left until the starting bit 1 and the subsequent 0 are found. byte If the number of bits shifted to the left is greater than 8, rxbuff9 and rxbuff 10 , …, rxbuff n ; Step 2.5, after finding the start bit 1 and the subsequent 0; the following position bit, error bit, warning bit, and 6 bits of CRC are extracted in sequence; Step 2.6: If the error bit is 0, it means that there is a problem with the data; if the error bit is 1, it means that the data transmission can be trusted; Step 2.7, set the position bit, error bit, and warning bit according to x 6 +x 1 +x 0 The CRC check is performed in this way. If the check result is the same as the 6-bit data of the CRC of the data packet, it means that the data received this time is completely correct, otherwise the data received this time is wrong.

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