Covalently functionalized MXene artificial protrusions and methods of making same

Abstract

The invention discloses a covalent functionalized MXene artificial synapse and a preparation method thereof, relates to the technical field of artificial intelligence, and aims at solving the problems of how to enrich the overall characteristics of cranial nerve-like chips and promote the artificial intelligence technology. The preparation method comprises the following steps: selecting a substrate; performing patterning treatment on the grid electrode, the source electrode and the drain electrode on the substrate by utilizing a photoetching process, and performing electron beam evaporation to deposit a metal layer and performing stripping to obtain a metal electrode pattern; carrying out patterning processing on the channel region on the substrate by utilizing a photoetching process; the MAX phase material is subjected to in-situ acid etching in combination with mechanical stripping to obtain a few layers of T < 3 > C < 2 > TX MXene; forming a uniform T < 3 > C < 2 > TX MXene film on the substrate through a coating process, and obtaining a channel region pattern through stripping; preparing an iodonium salt solution, and immersing the prepared device into the iodonium salt solution to complete covalent functionalization; and preparing an electrolyte solution, and dripping and casting electrolyte on the Ti3C2TX MXene channel layer, the grid electrode and the exposed substrate.

Description

Technical Field

[0001] The present invention relates to the technical field of artificial intelligence, and in particular to a covalently functionalized MXene artificial synapse and a preparation method thereof. Background Art

[0002] With the rapid development of artificial intelligence, the demand for various intelligent tasks has exploded around the world, from real-time big data, motion control to visual and auditory recognition. However, the traditional von Neumann architecture currently used has become a bottleneck because of its limited parallel computing capabilities and high power consumption for processing big data, which is caused by the data bus that must be used for data transmission between the physically separated processing units and the memory. Therefore, in order to successfully perform big data analysis, a new architecture for neuromorphic computing has been developed. The key idea of ​​the new architecture is to calculate data in memory without data transmission (or small-scale movement of data), thereby reducing power consumption and suppressing latency through parallel data processing capabilities.

[0003] In the field of neuromorphic computing, specially designed hardware such as neuromorphic chips can emulate the functions of neurons and synapses in the human brain to achieve efficient parallel information processing and learning. Both two-terminal memristors and three-terminal neuromorphic transistors are suitable as analog components of artificial synapses and neurons. Artificial synapses driven by three-terminal electrolyte-gated transistors stand out because of their precise controllability of conductance, fast response time, and stable electrical properties. They support synchronous learning processes and can update synaptic weights while data transmission is ongoing. MXene materials, as channel materials, provide advantages for the development of high-performance neuromorphic computing devices with their low migration energy barriers, adjustable surface properties, open interlayer structures, and ease of processing and addition, heralding a wide range of applications in simulating human brain intelligence.

[0004] However, the current electrolyte-gated synaptic transistors based on MXene channel materials exhibit higher postsynaptic currents and lower synaptic plasticity. Therefore, opening the MXene band gap and improving the ion storage capacity by covalently functionalizing and grafting strong electron-withdrawing groups has become an idea for improving the performance of MXene synaptic transistors. This is expected to greatly enrich the overall characteristics of brain-like neural chips and promote the development of artificial intelligence technology. Summary of the invention

[0005] The present invention proposes a covalently functionalized MXene artificial synapse, which includes a substrate layer, a source-gate-drain electrode layer, a channel layer, and an electrolyte layer from bottom to top.

[0006] The present invention is further configured as follows: the channel layer is a covalently functionalized Ti3C2T X MXene.

[0007] The present invention also proposes a method for preparing the covalently functionalized MXene artificial synapse as described above, comprising the following steps: S1: selecting a substrate and cleaning the substrate; S2: patterning the gate, source and drain on the substrate by using a photolithography process, and depositing a metal layer by electron beam evaporation and peeling off to obtain a metal electrode pattern; S3: patterning the channel region on the substrate using a photolithography process and performing a hydrophilic treatment; S4: The MAX phase material is subjected to in-situ acid etching combined with mechanical stripping to obtain a few-layer Ti3C2T X MXene; S5: Forming a uniform Ti3C2T on the substrate through a coating process X MXene film, and the channel area pattern is obtained by peeling; S6: preparing an iodonium salt solution, immersing the device prepared in step S5 into the iodonium salt solution to complete covalent functionalization; after the covalent functionalization is completed, repeatedly rinsing the device with acetonitrile and methanol solution, and then drying it with a nitrogen gun; finally, heat treating it in a vacuum drying oven at 90° C. for 20 minutes to remove the non-volatile solvent; S7: Prepare electrolyte solution, X The MXene channel layer, the gate and the exposed substrate are drop-casted with electrolyte, and the electrolyte covers the channel layer cake and connects the gate to construct Ti3C2T X MXene synaptic transistor.

[0008] The present invention is further configured as follows: the substrate in step S1 is one of silicon oxide wafer, glass, silicon carbide or gallium nitride.

[0009] The present invention is further configured as follows: the material of the source electrode, the gate electrode and the drain electrode in step S2 is Cr / Au or Cr / Pt; and the thickness is 35nm-65nm.

[0010] The present invention is further configured as follows: the hydrophilic treatment in step S3 is performed by ultraviolet ozone or oxygen plasma treatment.

[0011] The present invention is further configured as follows: the Ti3C2T in step S4 X The concentration of MXene is 1-20 mg / ml.

[0012] The present invention is further configured as follows: the coating process in step S5 is one of spin coating, spray coating or dip coating, and the Ti3C2T X The thickness of MXene films is 1-20nm.

[0013] The present invention is further configured as follows: the iodonium salt in step S6 is any one of (perfluoropropyl)phenyliodonium trifluoromethanesulfonate, bis(3-(trifluoromethyl)phenyl)iodonium trifluoromethanesulfonate, 3,3'-dinitrodiphenyliodonium hexafluorophosphate, and (4-cyanophenyl)(mesityl)iodonium trifluoromethanesulfonate; the strong electron-withdrawing group provided is any one of a perfluoropropyl group, a trifluoromethylphenyl group, a nitro group, and a cyano group; the concentration of the iodonium salt solution is 5-15 mg / ml, and the immersion time is 30-90 min.

[0014] The present invention is further configured as follows: the drop-cast electrolyte in step S7 is PEO / Li Cl O4, PEO / Li Cl O4 serves as a lithium ion supply layer, and the mass ratio of PEO to Li Cl O4 is 2.5-5:1.

[0015] The beneficial effects of the present invention are:

[0016] 1. The method for covalent functionalization of iodonium salt provided by the present invention is to react Ti3C2T X The introduction of strong electron-withdrawing groups on the MXene surface opens up the Ti3C2T X The band gap of Ti3C2T X The conductive properties of the material change from metal-like to semiconductor.

[0017] 2. The present invention modulates the channel current by driving the lithium ion migration behavior by electric field, which can simulate the pulse number-dependent plasticity and pulse frequency-dependent plasticity of synapses and realize electrolyte-gated synaptic bionics. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The Ti3C2T prepared by the present invention is shown X Schematic diagram of the structure of MXene synaptic transistor.

[0019] Figure 2 The modified Ti3C2T prepared by the present invention is shown X REELS spectrum.

[0020] Figure 3 The Ti3C2T prepared by the present invention is shown X Graph of the transfer characteristics of a synaptic transistor.

[0021] Figure 4 The Ti3C2T constructed by the present invention is shown X Excitatory postsynaptic current (EPSC) response and decay behavior when a single pulse is applied to a synaptic transistor.

[0022] Figure 5The Ti3C2T constructed by the present invention is shown X The relationship between long-term potentiation (LTP) of synaptic transistors and the number of gate pulses.

[0023] Figure 6 The Ti3C2T constructed by the present invention is shown X The relationship between long-term potentiation (LTP) of synaptic transistors and gate pulse interval. DETAILED DESCRIPTION

[0024] Those skilled in the art can refer to the content of this article and appropriately improve the process parameters. It is particularly important to point out that all similar replacements and modifications are obvious to those skilled in the art, and they are all considered to be included in the present invention. The methods and applications of the present invention have been described through preferred embodiments, and relevant personnel can modify or appropriately change and combine the methods and applications described herein without departing from the content, spirit and scope of the present invention to implement and apply the technology of the present invention.

[0025] Example 1

[0026] This embodiment proposes a covalently functionalized MXene artificial synapse, which includes a substrate layer, a source-gate-drain electrode layer, a channel layer, and an electrolyte layer from top to bottom. The channel layer is a covalently functionalized Ti3C2T X MXene.

[0027] Example 2

[0028] This embodiment provides a method for preparing a covalently functionalized MXene artificial synapse as described in Example 1, comprising the following steps:

[0029] S1: selecting a substrate and cleaning the substrate;

[0030] S2: patterning the gate, source and drain on the substrate by using a photolithography process, and depositing a metal layer by electron beam evaporation and peeling off to obtain a metal electrode pattern;

[0031] S3: patterning the channel region on the substrate using a photolithography process and performing a hydrophilic treatment;

[0032] S4: The MAX phase material is subjected to in-situ acid etching combined with mechanical stripping to obtain a few-layer Ti3C2T X MXene;

[0033] S5: Forming a uniform Ti3C2T on the substrate through a coating process X MXene film, and the channel area pattern is obtained by peeling;

[0034] S6: preparing an iodonium salt solution, immersing the device prepared in step S5 into the iodonium salt solution to complete covalent functionalization; after the covalent functionalization is completed, repeatedly rinsing the device with acetonitrile and methanol solution, and then drying it with a nitrogen gun; finally, heat treating it in a vacuum drying oven at 90° C. for 20 minutes to remove the non-volatile solvent;

[0035] S7: Prepare electrolyte solution, X The electrolyte is drop-cast on the MXene channel layer, the gate and the exposed substrate, and the electrolyte covers the channel layer and connects the gate to construct Ti3C2T X MXene synaptic transistor.

[0036] The substrate in step S1 is selected from any one of silicon oxide wafer, glass, silicon carbide or gallium nitride.

[0037] The source, gate and drain in step S2 are made of Cr / Au or Cr / Pt, and have a thickness of 35nm-65nm.

[0038] The hydrophilic treatment in step S3 is performed by ultraviolet ozone or oxygen plasma treatment.

[0039] Wherein the T i3C2T in step S4 X The MXene concentration is 1-20 mg / ml.

[0040] The coating process in step S5 is any one of spin coating, spray coating or dip coating to form Ti3C2T X The thickness of MXene films is 5-20nm.

[0041] The iodonium salt in step S6 is any one of (perfluoropropyl)phenyliodonium trifluoromethanesulfonate, bis(3-(trifluoromethyl)phenyl)iodonium trifluoromethanesulfonate, 3,3'-dinitrodiphenyliodonium hexafluorophosphate, and (4-cyanophenyl)(mesityl)iodonium trifluoromethanesulfonate, the strong electron-withdrawing group provided is any one of a perfluoropropyl group, a trifluoromethylphenyl group, a nitro group, and a cyano group, the concentration of the iodonium salt solution is 5-15 mg / ml, and the immersion time is 30-90 min.

[0042] The drop-cast electrolyte in step S7 is PEO / Li Cl O4, PEO / Li Cl O4 serves as a lithium ion supply layer, and the mass ratio of PEO to Li Cl O4 is 2.5-5:1.

[0043] Example 3

[0044] like Figure 1 As shown, based on T i3C2T XThe MXene synaptic transistor is a side-gate structure, including substrate, source S, drain D, gate G, Ti3C2T X Channel layer and electrolyte layer, Ti3C2T X The channel layer is grafted with perfluoropropyl groups through a nucleophilic reaction.

[0045] The preparation method described in Example 2 is adopted, which specifically comprises the following steps:

[0046] S1: Select an oxidized silicon wafer as the substrate, and ultrasonically clean the oxidized silicon wafer of 2×2 cm in acetone, isopropanol, and deionized water for 5 minutes in sequence to remove pollutants on the surface of the substrate, and then blow dry it with nitrogen gas;

[0047] S2: gate, source and drain patterning;

[0048] S2-1: patterning the source, gate and drain on the substrate by spin coating a negative photoresist on the substrate, pre-baking, UV exposure, post-baking, developing and fixing, wherein the channel spacing between the source and drain is 5 μm and the length is 100 μm;

[0049] S2-2: depositing a Cr / Au metal layer on the substrate by electron beam evaporation, wherein the thickness of Cr is 5 nm and the thickness of Au is 50 nm;

[0050] S2-3: Soak the substrate after depositing the metal layer in acetone at 95°C for 15 minutes and in isopropanol for 1 minute, and peel off to obtain a patterned metal electrode pattern;

[0051] S3: patterning of the channel layer region;

[0052] S3-1: patterning a channel region on the substrate by spin coating a positive photoresist on the substrate, pre-baking, UV exposure, post-baking, developing and fixing, wherein the channel region has an area of ​​100 μm×100 μm;

[0053] S3-2: Place the substrate in a UV ozone machine and irradiate with UV light for 20 minutes to perform hydrophilic treatment;

[0054] S4: Preparation of few-layer Ti3C2T X MXene;

[0055] S4-1: Weigh 1.6 g of Li F and add it to 20 ml of 9 M HCL, and stir in a polytetrafluoroethylene beaker for 5 min;

[0056] S4-2: Slowly add 1g Ti3AlC2 powder into the above solution, put the polytetrafluoroethylene beaker into a 40℃ oil bath, and continue stirring for 30h;

[0057] S4-3: After the reaction, the reaction mixture was washed 5-6 times with deionized water (centrifuged at 5000 rpm for 5 min) to a pH of 6. Finally, the precipitate with obvious swelling at the bottom was multilayer Ti3C2T X ;

[0058] S4-4: Add the above precipitate to 30 ml of deionized water, shake manually for 10 min, and pour into a washing bottle. Connect the long port to an inert gas, sonicate for 50 min under ventilation and running water, and centrifuge the solution at 3500 rpm for 30 min to obtain a few-layer Ti3C2T X MXene dispersion;

[0059] S5: Channel region T i3C2T X Preparation of thin films;

[0060] S5-1: Place a few layers of Ti3C2T X MXene dispersion was diluted to 5 mg / ml;

[0061] S5-2: Set the spin coating parameters of the coating machine to spin coating at 1000 rpm for 10 s and at 3000 rpm for 30 s;

[0062] S5-3: After the spin coating is completed, the device is placed in a vacuum drying oven for heat treatment at 90°C for 20 minutes to evaporate the remaining solvent;

[0063] S5-4: Spin-coated Ti3C2T X The film substrate was immersed in acetone at 95 °C for 15 min and isopropanol for 1 min, and then peeled off to obtain the patterned Ti3C2T X Channel area.

[0064] S6: covalent functionalization with iodonium salt;

[0065] S6-1: In a glove box, prepare a 10 mg / ml acetonitrile / methanol solution of (perfluoropropyl)phenyliodonium trifluoromethanesulfonate;

[0066] S6-2: Soak the device prepared in step S5 in the solution prepared in step S6-1 for 50 minutes;

[0067] S6-3: After the reaction is completed, the substrate is repeatedly rinsed with acetonitrile and methanol, and blown dry with nitrogen;

[0068] S6-4: Place the device on a hot plate at 90° C. in a glove box and heat for 20 min;

[0069] S7: Building T i3C2T X MXene synaptic transistors;

[0070] S7-1: Weigh 250 mg of polyethylene oxide and 100 mg of lithium perchlorate, add to 10 ml of anhydrous acetonitrile, and stir at 60 ° C overnight until the solution becomes transparent;

[0071] S7-2: Use a pipette to take 2 μL of electrolyte solution and drop-cast it on the channel layer, the gate and the exposed substrate. The electrolyte layer covers the channel layer and is connected to the gate.

[0072] S7-3: Place the device in a vacuum drying oven and heat it at 90°C for 20 minutes to remove the unvolatile acetonitrile.

[0073] The reactive electron energy loss spectroscopy (REELS) of this embodiment was tested by X-ray photoelectron spectroscopy. Figure 2 As shown, Ti3C2T grafted with perfluoropropyl groups X The band gap is 2.82 eV. The transfer curve test of the artificial synapse based on the electrolyte gate transistor obtained in this embodiment is performed using a semiconductor analyzer, and the counterclockwise hysteresis can be used as an information storage window for artificial synapse simulation.

[0074] Example 4

[0075] Based on Ti3C2T X The MXene synaptic transistor is a side-gate structure, including a substrate, a source S, a drain D, a gate G, and a Ti3C2T X Channel layer and electrolyte layer, Ti3C2T X The channel layer is grafted with perfluoropropyl groups through a nucleophilic reaction.

[0076] The preparation method described in Example 2 is adopted, which specifically comprises the following steps:

[0077] S1: Select a glass sheet as the substrate, and ultrasonically clean the 2×2 cm glass sheet in acetone, isopropanol, and deionized water for 5 minutes in sequence to remove contaminants on the surface of the substrate, and then blow dry with nitrogen gas;

[0078] S2: gate, source and drain patterning;

[0079] S2-1: patterning the source, gate and drain on the substrate by spin coating a negative photoresist on the substrate, pre-baking, UV exposure, post-baking, developing and fixing, wherein the channel spacing between the source and drain is 5 μm and the length is 100 μm;

[0080] S2-2: depositing a Cr / Au metal layer on the substrate by electron beam evaporation, wherein the thickness of Cr is 5 nm and the thickness of Au is 60 nm;

[0081] S2-3: Soak the substrate after depositing the metal layer in acetone at 95°C for 15 minutes and in isopropanol for 1 minute, and peel off to obtain a patterned metal electrode pattern;

[0082] S3: patterning of the channel layer region;

[0083] S3-1: patterning a channel region on the substrate by spin coating a positive photoresist on the substrate, pre-baking, UV exposure, post-baking, developing and fixing, wherein the channel region has an area of ​​100 μm×100 μm;

[0084] S3-2: Place the substrate in a UV ozone machine and irradiate with UV light for 20 minutes to perform hydrophilic treatment;

[0085] S4: Preparation of few-layer Ti3C2T X MXene;

[0086] S4-1: Weigh 1.6 g of Li F and add it to 20 ml of 9 M HCL, and stir in a polytetrafluoroethylene beaker for 5 min;

[0087] S4-2: Slowly add 1g Ti3AlC2 powder into the above solution, put the polytetrafluoroethylene beaker into a 40℃ oil bath, and continue stirring for 30h;

[0088] S4-3: After the reaction, the reaction mixture was washed 5-6 times with deionized water (centrifuged at 5000 rpm for 5 min) to a pH of 6. Finally, the precipitate with obvious swelling at the bottom was multilayer Ti3C2T X ;

[0089] S4-4: Add the above precipitate to 30 ml of deionized water, shake manually for 10 min, and pour into a washing bottle. Connect the long port to an inert gas, sonicate for 50 min under ventilation and running water, and centrifuge the solution at 3500 rpm for 30 min to obtain a few-layer Ti3C2T X MXene dispersion;

[0090] S5: Channel region T i3C2T X Preparation of thin films;

[0091] S5-1: Place a few layers of Ti3C2T X MXene dispersion was diluted to 1 mg / ml;

[0092] S5-2: Set the parameters of the pull-up immersion coating apparatus, the operating speed is 20 mm / min, the immersion time is 3 s, and the number of coating times is 15 times;

[0093] S5-3: After coating, the device is placed in a vacuum drying oven for heat treatment at 90°C for 20 minutes to evaporate the remaining solvent;

[0094] S5-4: After coating, X The film substrate was immersed in acetone at 95 °C for 15 min and isopropanol for 1 min, and then peeled off to obtain the patterned Ti3C2T X Channel area.

[0095] S6: covalent functionalization with iodonium salt;

[0096] S6-1: In a glove box, prepare a 5 mg / ml 3,3'-dinitrodiphenyliodonium hexafluorophosphate solution in acetonitrile / methanol;

[0097] S6-2: Soak the device prepared in step S5 in the solution prepared in step S6-1 for 75 minutes;

[0098] S6-3: After the reaction is completed, the substrate is repeatedly rinsed with acetonitrile and methanol, and blown dry with nitrogen;

[0099] S6-4: Place the device on a hot plate at 90° C. in a glove box and heat for 20 min;

[0100] S7: Building T i3C2T X MXene synaptic transistors;

[0101] S7-1: Weigh 250 mg of polyethylene oxide and 62.5 mg of lithium perchlorate, add to 15 ml of anhydrous acetonitrile, and stir at 60 ° C overnight until the solution becomes transparent;

[0102] S7-2: Use a pipette to take 2 μL of electrolyte solution and drop-cast it on the channel layer, the gate and the exposed substrate. The electrolyte layer covers the channel layer and is connected to the gate.

[0103] S7-3: Place the device in a vacuum drying oven and heat it at 90°C for 20 minutes to remove the unvolatile acetonitrile.

[0104] like Figure 4 As shown, a single pulse test was performed on the artificial synapse obtained in this embodiment using a semiconductor analyzer. Under the condition of electrical stimulation of a single pulse amplitude given to the device, the artificial synapse generated a corresponding excitatory postsynaptic current, indicating that the device successfully simulated the functional behavior of biological synapses.

[0105] Example 5

[0106] Based on Ti3C2T X The MXene synaptic transistor is a side-gate structure, including a substrate, a source S, a drain D, a gate G, and a Ti3C2T XChannel layer and electrolyte layer, Ti3C2T X The channel layer is grafted with trifluoromethylphenyl groups through a nucleophilic reaction.

[0107] The preparation method described in Example 2 is adopted, which specifically comprises the following steps:

[0108] S1: Select a silicon carbide wafer as the substrate, and ultrasonically clean the 2×2 cm silicon carbide wafer in acetone, isopropanol, and deionized water for 5 minutes in sequence to remove contaminants on the substrate surface, and then blow dry with nitrogen gas;

[0109] S2: gate, source and drain patterning;

[0110] S2-1: patterning the source, gate and drain on the substrate by spin coating a negative photoresist on the substrate, pre-baking, UV exposure, post-baking, developing and fixing, wherein the channel spacing between the source and drain is 5 μm and the length is 100 μm;

[0111] S2-2: depositing a Cr / Au metal layer on the substrate by electron beam evaporation, wherein the thickness of Cr is 5 nm and the thickness of Au is 45 nm;

[0112] S2-3: Soak the substrate after depositing the metal layer in acetone at 95°C for 15 minutes and in isopropanol for 1 minute, and peel off to obtain a patterned metal electrode pattern;

[0113] S3: patterning of the channel layer region;

[0114] S3-1: patterning a channel region on the substrate by spin coating a positive photoresist on the substrate, pre-baking, UV exposure, post-baking, developing and fixing, wherein the channel region has an area of ​​100 μm×100 μm;

[0115] S3-2: pretreating the cleaned substrate with oxygen plasma for 15 min;

[0116] S4: Preparation of few-layer Ti3C2T X MXene;

[0117] S4-1: Weigh 1.6 g of Li F and add it to 20 ml of 9 M HCL, and stir in a polytetrafluoroethylene beaker for 5 min;

[0118] S4-2: Slowly add 1g Ti3AlC2 powder into the above solution, put the polytetrafluoroethylene beaker into a 40℃ oil bath, and continue stirring for 30h;

[0119] S4-3: After the reaction, the reaction mixture was washed 5-6 times with deionized water (centrifuged at 5000 rpm for 5 min) to a pH of 6. Finally, the precipitate with obvious swelling at the bottom was multilayer Ti3C2T X ;

[0120] S4-4: Add the above precipitate to 30 ml of deionized water, shake manually for 10 min, and pour into a washing bottle. Connect the long port to an inert gas, sonicate for 50 min under ventilation and running water, and centrifuge the solution at 3500 rpm for 30 min to obtain a few-layer Ti3C2T X MXene dispersion;

[0121] S5: Channel region T i3C2T X Preparation of thin films;

[0122] S5-1: Place a few layers of Ti3C2T X MXene dispersion was diluted to 5 mg / ml;

[0123] S5-2: Set the pressure of the spraying equipment to 22PS I, the flow rate to 7L / min, the nozzle diameter to 0.2m, and the spraying time to 10s;

[0124] S5-3: After spraying, place the device in a vacuum drying oven for heat treatment at 90°C for 20 minutes to evaporate the remaining solvent;

[0125] S5-4: After spraying, T i3C2T X The film substrate was immersed in acetone at 95 °C for 15 min and isopropanol for 1 min, and then peeled off to obtain the patterned Ti3C2T X Channel area.

[0126] S6: covalent functionalization with iodonium salt;

[0127] S6-1: In a glove box, prepare a 15 mg / ml acetonitrile / methanol solution of bis(3-(trifluoromethyl)phenyl)iodonium trifluoromethanesulfonate;

[0128] S6-2: Soak the device prepared in step S5 in the solution prepared in step S6-1 for 30 minutes;

[0129] S6-3: After the reaction is completed, the substrate is repeatedly rinsed with acetonitrile and methanol, and blown dry with nitrogen;

[0130] S6-4: Place the device on a hot plate at 90° C. in a glove box and heat for 20 min;

[0131] S7: Building T i3C2T X MXene synaptic transistors;

[0132] S7-1: Weigh 250 mg of polyethylene oxide and 50 mg of lithium perchlorate, add to 15 ml of anhydrous acetonitrile, and stir at 60 ° C overnight until the solution becomes transparent;

[0133] S7-2: Use a pipette to take 2 μL of electrolyte solution and drop-cast it on the channel layer, the gate and the exposed substrate. The electrolyte layer covers the channel layer and is connected to the gate.

[0134] S7-3: Place the device in a vacuum drying oven and heat it at 90°C for 20 minutes to remove the unvolatile acetonitrile.

[0135] like Figure 5 As shown in Figure 2, the response characteristics of the artificial synapse under different numbers of 50ms voltage pulses. Figure 6 Shown is the response characteristics of the artificial synapse under 10 50ms voltage pulses of different frequencies. The more pulses there are and the smaller the voltage pulse frequency, the more obvious the change in the channel current of the device is, simulating the frequency-dependent plasticity of the neural synapse.

[0136] Example 6

[0137] Based on Ti3C2T X The MXene synaptic transistor is a side-gate structure, including a substrate, a source S, a drain D, a gate G, and a Ti3C2T X Channel layer and electrolyte layer, Ti3C2T X The channel layer is grafted with cyano groups through a nucleophilic reaction.

[0138] The preparation method described in Example 2 is adopted, which specifically comprises the following steps:

[0139] S1: Select a GaN wafer as the substrate, and ultrasonically clean the 2×2 cm GaN wafer in acetone, isopropanol, and deionized water for 5 minutes in turn to remove contaminants on the substrate surface, and then blow dry with nitrogen;

[0140] S2: gate, source and drain patterning;

[0141] S2-1: patterning the source, gate and drain on the substrate by spin coating a negative photoresist on the substrate, pre-baking, UV exposure, post-baking, developing and fixing, wherein the channel spacing between the source and drain is 5 μm and the length is 100 μm;

[0142] S2-2: depositing a Cr / Au metal layer on the substrate by electron beam evaporation, wherein the thickness of Cr is 5 nm and the thickness of Au is 60 nm;

[0143] S2-3: Soak the substrate after depositing the metal layer in acetone at 95°C for 15 minutes and in isopropanol for 1 minute, and peel off to obtain a patterned metal electrode pattern;

[0144] S3: patterning of the channel layer region;

[0145] S3-1: patterning a channel region on the substrate by spin coating a positive photoresist on the substrate, pre-baking, UV exposure, post-baking, developing and fixing, wherein the channel region has an area of ​​100 μm×100 μm;

[0146] S3-2: pretreating the cleaned substrate with oxygen plasma for 15 min;

[0147] S4: Preparation of few-layer Ti3C2T X MXene;

[0148] S4-1: Weigh 1.6 g of Li F and add it to 20 ml of 9 M HCL, and stir in a polytetrafluoroethylene beaker for 5 min;

[0149] S4-2: Slowly add 1g Ti3AlC2 powder into the above solution, put the polytetrafluoroethylene beaker into a 40℃ oil bath, and continue stirring for 30h;

[0150] S4-3: After the reaction, the reaction mixture was washed 5-6 times with deionized water (centrifuged at 5000 rpm for 5 min) to a pH of 6. Finally, the precipitate with obvious swelling at the bottom was multilayer Ti3C2T X ;

[0151] S4-4: Add the above precipitate to 30 ml of deionized water, shake manually for 10 min, and pour into a washing bottle. Connect the long port to an inert gas, and ultrasonicate for 50 min under ventilation and running water. Centrifuge the solution at 3500 rpm for 30 min to obtain a few-layer Ti3C2T X MXene dispersion;

[0152] S5: Channel region T i3C2T X Preparation of thin films;

[0153] S5-1: Place a few layers of Ti3C2T X MXene dispersion was diluted to 15 mg / ml;

[0154] S5-2: Set the spin coating parameters of the coating machine to spin coating at 1000 rpm for 10 s and at 3000 rpm for 30 s;

[0155] S5-3: After the spin coating is completed, the device is placed in a vacuum drying oven for heat treatment at 90°C for 20 minutes to evaporate the remaining solvent;

[0156] S5-4: Spin-coated Ti3C2T X The film substrate was immersed in acetone at 95 °C for 15 min and isopropanol for 1 min, and then peeled off to obtain the patterned Ti3C2T X Channel area.

[0157] S6: covalent functionalization with iodonium salt;

[0158] S6-1: In a glove box, prepare a 5 mg / ml acetonitrile / methanol solution of (4-cyanophenyl)(mesityl)iodonium trifluoromethanesulfonate;

[0159] S6-2: Soak the device prepared in step S5 in the solution prepared in step S6-1 for 90 minutes;

[0160] S6-3: After the reaction is completed, the substrate is repeatedly rinsed with acetonitrile and methanol, and blown dry with nitrogen;

[0161] S6-4: Place the device on a hot plate at 90° C. in a glove box and heat for 20 min;

[0162] S7: Building T i3C2T X MXene synaptic transistors;

[0163] S7-1: Weigh 250 mg of polyethylene oxide and 100 mg of lithium perchlorate, add to 10 ml of anhydrous acetonitrile, and stir at 60 ° C overnight until the solution becomes transparent;

[0164] S7-2: Use a pipette to take 2 μL of electrolyte solution and drop-cast it on the channel layer, the gate and the exposed substrate. The electrolyte layer covers the channel layer and is connected to the gate.

[0165] S7-3: Place the device in a vacuum drying oven and heat it at 90°C for 20 minutes to remove the unvolatile acetonitrile.

[0166] In summary, the method for covalent functionalization of iodonium salt provided by the present invention is to react Ti3C2T X The introduction of strong electron-withdrawing groups on the MXene surface opens up the Ti3C2T X The band gap of Ti3C2T X The conductive properties of the material are changed from metal-like to semiconductor. The present invention modulates the channel current by driving the lithium ion migration behavior by electric field, which can simulate the pulse number-dependent plasticity and pulse frequency-dependent plasticity of the synapse and realize electrolyte-gated synapse bionics.

[0167] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be within the scope of protection of the present invention.

Claims

1. A covalently functionalized MXene artificial synapse, characterized in that: From bottom to top, it includes a substrate layer, a source-gate-drain electrode layer, a channel layer, and an electrolyte layer.

2. The covalently functionalized MXene artificial synapse according to claim 1, characterized in that The channel layer is covalently functionalized Ti3C2T X MXene.

3. A method for preparing a covalently functionalized MXene artificial synapse according to any one of claims 1 to 2, characterized in that: The following steps are included: S1: selecting a substrate and cleaning the substrate; S2: patterning the gate, source and drain on the substrate by using a photolithography process, and depositing a metal layer by electron beam evaporation and peeling off to obtain a metal electrode pattern; S3: patterning the channel region on the substrate using a photolithography process and performing a hydrophilic treatment; S4: The MAX phase material was obtained by in-situ acid etching combined with mechanical stripping to obtain a few-layer Ti3C2T X MXene; S5: Forming a uniform Ti3C2T on the substrate by a coating process X MXene film, and the channel area pattern is obtained by peeling; S6: preparing an iodonium salt solution, immersing the device prepared in step S5 into the iodonium salt solution to complete covalent functionalization; after the covalent functionalization is completed, repeatedly rinsing the device with acetonitrile and methanol solution, and then drying it with a nitrogen gun; finally, heat treating it in a vacuum drying oven at 90° C. for 20 minutes to remove the non-volatile solvent; S7: Prepare electrolyte solution and X The MXene channel layer, the gate and the exposed substrate are drop-casted with an electrolyte, the electrolyte covers the channel layer and connects to the gate to construct a Ti3C2T X MXene synaptic transistor.

4. The method for preparing a covalently functionalized MXene artificial synapse according to claim 3, characterized in that: The substrate in step S1 is one of silicon oxide wafer, glass, silicon carbide or gallium nitride.

5. The method for preparing a covalently functionalized MXene artificial synapse according to claim 3, characterized in that: The source, gate and drain in step S2 are made of Cr / Au or Cr / Pt, and have a thickness of 35nm-65nm.

6. The method for preparing a covalently functionalized MXene artificial synapse according to claim 3, characterized in that: The hydrophilic treatment in step S3 is performed by ultraviolet ozone or oxygen plasma treatment.

7. The method for preparing a covalently functionalized MXene artificial synapse according to claim 3, characterized in that: The Ti3C2T in step S4 X The concentration of MXene is 1-20 mg / ml.

8. The method for preparing a covalently functionalized MXene artificial synapse according to claim 3, characterized in that: The coating process in step S5 is one of spin coating, spray coating or dip coating, and the formed Ti3C2T X The thickness of MXene film is 5-20nm.

9. The method for preparing a covalently functionalized MXene artificial synapse according to claim 3, characterized in that: The iodonium salt in step S6 is any one of (perfluoropropyl)phenyliodonium trifluoromethanesulfonate, bis(3-(trifluoromethyl)phenyl)iodonium trifluoromethanesulfonate, 3,3'-dinitrodiphenyliodonium hexafluorophosphate, and (4-cyanophenyl)(mesityl)iodonium trifluoromethanesulfonate, the strong electron-withdrawing group provided is any one of a perfluoropropyl group, a trifluoromethylphenyl group, a nitro group, and a cyano group, the concentration of the iodonium salt solution is 5-15 mg / ml, and the immersion time is 30-90 min.

10. The method for preparing a covalently functionalized MXene artificial synapse according to claim 3, characterized in that: The drop-cast electrolyte in step S7 is PEO / LiClO4, PEO / LiClO4 serves as a lithium ion supply layer, and the mass ratio of PEO to LiClO4 is 2.5-5:1.

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