Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of reducing a lateral leakage current between adjacent pixels such that color mixing between adjacent pixels can be prevented. According to the embodiment of the invention, the display device includes a substrate, a first pixel electrode and a second pixel electrode disposed on the substrate, a first light providing layer disposed on the first pixel electrode, a second light providing layer disposed on the second pixel electrode, and a common electrode disposed on the first light providing layer and the second light providing layer, and a current trapping layer disposed between the first pixel electrode and the second pixel electrode in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0100102 filed on July 31, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device in which a lateral leakage current between adjacent pixels can be reduced so that color mixing between the adjacent pixels can be prevented. Background Art

[0004] An organic light emitting display device includes a light emitting element (eg, an organic light emitting diode) having a brightness that varies according to a current flowing through the light emitting element. Summary of the invention

[0005] Aspects of the present disclosure provide a display device in which a lateral leakage current between adjacent pixels is reduced so that color mixing between adjacent pixels can be prevented.

[0006] However, aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0008] According to an embodiment of the present disclosure, a display device includes: a substrate; a first pixel electrode and a second pixel electrode, which are arranged on the substrate; a first light-providing layer, which is arranged on the first pixel electrode; a second light-providing layer, which is arranged on the second pixel electrode; a common electrode, which is arranged on the first light-providing layer and the second light-providing layer; and a current capture layer, which is arranged between the first pixel electrode and the second pixel electrode in a plan view.

[0009] In an embodiment, a trapping voltage applied to the current trapping layer is lower than a pixel voltage applied to the first pixel electrode.

[0010] In an embodiment, the trapping voltage is the same as the common voltage applied to the common electrode.

[0011] In an embodiment, the display device may further include: a bank overlapping the current trap layer in a plan view, and the bank defines a first emission region of the first pixel electrode and a second emission region of the second pixel electrode.

[0012] In an embodiment, the display device may further include: a light blocking layer overlapping the current trapping layer in a plan view.

[0013] In an embodiment, the display device may further include: a separation portion disposed on the bank to overlap the light blocking layer in a plan view.

[0014] In an embodiment, the current trap layer overlaps the bank, the separation portion, and the light blocking layer.

[0015] In an embodiment, the display device further includes: a separation portion overlapping the light blocking layer. The dam may include a hole formed through the dam.

[0016] In an embodiment, the display device may further include: an insulating layer disposed under the bank, and the insulating layer includes a groove disposed in a region corresponding to the hole.

[0017] In an embodiment, the separation portion may fill the hole and the groove.

[0018] In an embodiment, a portion of the separation part filling the hole and the groove may not cover a sidewall of the current trap layer.

[0019] In an embodiment, the display device may further include: a first color filter overlapping the first emission area; and a second color filter overlapping the second emission area.

[0020] In an embodiment, the current trap layer may have a shape surrounding each of the first pixel electrode and the second pixel electrode, and wherein a portion of the current trap layer may be disposed between the first pixel electrode and the second pixel electrode.

[0021] In an embodiment, the current trap layer may include: a first extending portion extending in a first direction; and a second extending portion extending in a second direction crossing the first direction.

[0022] In an embodiment, the current trap layer may define a plurality of opening regions surrounded by the first extension portion and the second extension portion, and wherein the first pixel electrode and the second pixel electrode are disposed in corresponding opening regions among the plurality of opening regions.

[0023] In an embodiment, the current trapping layer may be directly connected to at least one of the first light-providing layer and the second light-providing layer.

[0024] In an embodiment, the current capture layer may include: a supporting layer, disposed between the first pixel electrode and the second pixel electrode; and a connecting layer, extending from the supporting layer, disposed between the first light providing layer and the second light providing layer, and connected to at least one of the first light providing layer and the second light providing layer.

[0025] In an embodiment, each of the first light-providing layer and the second light-providing layer may include a plurality of light emitting units providing light of different colors.

[0026] According to an embodiment of the present disclosure, a display device may include a substrate and a plurality of light-emitting elements disposed on the substrate. Each of the plurality of light-emitting elements may include: a pixel electrode and a current capture layer disposed on the same plane and comprising the same material, the current capture layer completely surrounding the pixel electrode; a dam disposed on the pixel electrode to cover an edge of the pixel electrode and disposed on the current capture layer to cover the current capture layer; a light-providing layer disposed on the pixel electrode; and a common electrode disposed on the light-providing layer.

[0027] In an embodiment, the bank may completely cover a top surface and sidewalls of the current trapping layer.

[0028] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

[0029] According to an embodiment of the present disclosure, a current capture layer (or charge capture layer) may be provided between adjacent pixels in a display device. The current capture layer may capture charges on a current path between adjacent pixels, thereby reducing lateral leakage current between adjacent pixels. Thus, color mixing between adjacent pixels may be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0031] Figure 1 is a perspective view of an electronic device according to an exemplary embodiment of the present disclosure.

[0032] Figure 2 is a perspective view illustrating a display device included in an electronic device according to an embodiment of the present disclosure.

[0033] Figure 3 yes Figure 2 A cross-sectional view of a display device.

[0034] Figure 4 is a plan view showing a display layer of a display device according to an exemplary embodiment of the present disclosure.

[0035] Figure 5 is a plan view of a pixel electrode of a display device according to an exemplary embodiment.

[0036] Figure 6 It is along Figure 5 A cross-sectional view taken along line II'.

[0037] Figure 7 is a view for illustrating an effect of reducing a lateral leakage current in a display device according to an embodiment of the present disclosure.

[0038] Figure 8 It is shown along Figure 5 A cross-sectional view of another example taken along line II'.

[0039] Fig. 9 It is shown along Figure 5 A cross-sectional view of another example taken along line II'.

[0040] Fig.10 is a cross-sectional view illustrating a structure of a light emitting element according to an exemplary embodiment of the present disclosure.

[0041] Fig.11 , Fig.12 , Fig.13 and Fig.14 is a cross-sectional view illustrating a structure of a light emitting element according to an exemplary embodiment.

[0042] Fig.15 It is shown Fig.13 A cross-sectional view of an example of an organic light emitting diode.

[0043] Fig.16 It is shown Fig.14 A cross-sectional view of an example of an organic light emitting diode. DETAILED DESCRIPTION

[0044] From the following description of exemplary embodiments with reference to the accompanying drawings, the advantages and features of the present disclosure and methods for achieving them will become apparent. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. Exemplary embodiments are provided to make the disclosure of the present disclosure thorough and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the scope of the present disclosure is limited only by the claims.

[0045] As used herein, the phrase "element A on element B" means that element A may be directly disposed on element B and / or element A may be indirectly disposed on element B via another element C. Throughout the specification, the same reference numerals denote the same elements. The drawings, dimensions, ratios, angles, and numbers of elements given in the drawings are merely illustrative and are not limiting.

[0046] Although terms such as first, second, etc. are used to arbitrarily distinguish between the elements described by these terms, and therefore these terms are not necessarily intended to indicate a temporal or other priority order of these elements. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical scope of the present disclosure, a first element may be a second element.

[0047] The features of various exemplary embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. Various exemplary embodiments can be practiced individually or in combination.

[0048] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view of an electronic device according to an exemplary embodiment of the present disclosure.

[0050] Reference Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to any electronic device that provides a display screen. For example, the electronic device 1 may include a television, a monitor, an electronic billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC) (e.g., a laptop computer), an electronic watch, a smart watch, a watch phone, a head-mounted display device, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a video camera, etc.

[0051] The electronic device 1 may include a display device 10 (see Figure 2 ). Examples of display devices may include inorganic light emitting diode display devices, organic light emitting display devices, quantum dot light emitting display devices, plasma display devices, field emission display devices, etc. In the following description, an organic light emitting display device is used as an example of a display device, but the present disclosure is not limited thereto. Any other display device may be used as long as the technical concept of the present disclosure can be equally applied.

[0052] The shape of the electronic device 1 can be modified in various ways. For example, when viewed from the top, the electronic device 1 can have a shape such as a rectangle with a longer horizontal side, a rectangle with a longer vertical side, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DA of the electronic device 1 can also be similar to the overall shape of the electronic device 1. Figure 1 In the example shown in , the electronic device 1 has a rectangular shape having long sides in the second direction DR2 when viewed from the top.

[0053] The electronic device 1 may include a display area DA and a non-display area NDA. In the display area DA, an image can be displayed. In the non-display area NDA, no image is displayed. The display area DA may be referred to as an active area, and the non-display area NDA may be referred to as a non-active area. The display area DA may generally occupy the center of the electronic device 1.

[0054] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. In the second display area DA2 and the third display area DA3, components for implementing various functions of the electronic device 1 may be disposed. In other words, the second display area DA2 and the third display area DA3 may be referred to as component areas.

[0055] Figure 2 is a perspective view illustrating a display device included in an electronic device according to an embodiment of the present disclosure.

[0056] Reference Figure 2 , an electronic device 1 according to an exemplary embodiment of the present disclosure may include a display device 10. The display device 10 may provide a display screen that displays an image in the electronic device 1. When observed from the top, the display device 10 may have a shape similar to the electronic device 1. For example, when observed from the top, the display device 10 may have a shape similar to a rectangle having short sides in the first direction DR1 and long sides in the second direction DR2. The corners where the short sides in the first direction DR1 intersect with the long sides in the second direction DR2 may be rounded with a predetermined curvature. However, it should be understood that the present disclosure is not limited to this. These corners may be formed at right angles. When observed from the top, the shape of the display device 10 is not limited to a quadrilateral, but may be formed into a shape similar to other polygons, a circle, or an ellipse.

[0057] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0058] The display panel 100 may include a main area MA and a sub area SBA.

[0059] The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA positioned around the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may output light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0060] For example, the self-luminous element may include (but is not limited to) at least one of the following: an organic light emitting diode including an organic emission layer, a quantum dot light emitting diode (quantum LED) including a quantum dot emission layer, an inorganic light emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light emitting diode (micro LED).

[0061] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include: a gate driver (not shown) that applies a gate signal to a gate line; and a fan-out line (not shown) that connects the display driver 200 to the display area DA.

[0062] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a pad connected to the display driver 200 and the circuit board 300. According to another exemplary embodiment, the sub-region SBA may be eliminated, and the display driver 200 and the pad may be provided in the non-display area NDA.

[0063] The display driver 200 may output a control signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may apply a supply voltage to a voltage line, and may supply a gate control signal to a gate driver. The display driver 200 may be implemented as an integrated circuit, and may be attached to the display panel 100 by a chip-on-glass (COG) technology, a chip-on-plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 may be disposed in a sub-area SBA, and when the sub-area SBA is bent, the display driver 200 may overlap with the main area MA in the thickness direction. For another example, the display driver 200 may be mounted on a circuit board 300.

[0064] The circuit board 300 may be attached to the pad area of ​​the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0065] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and may sense a change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may determine whether there is an input, and may find the coordinates of the input based on the amount of capacitance change between the touch electrodes. The touch driver 400 may be implemented as an integrated circuit.

[0066] Figure 3 yes Figure 2 A cross-sectional view of a display device.

[0067] Reference Figure 3 , the display panel 100 may include a display layer DU and a color filter layer CFL. The display layer DU may include a substrate SUB, a transistor layer TRL, an emission material layer EMTL, and an encapsulation layer ENC.

[0068] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include, but is not limited to, a polymer resin such as polyimide (PI). According to another exemplary embodiment, the substrate SUB may include a glass material or a metal material.

[0069] The transistor layer TRL may be disposed on the substrate SUB. The transistor layer TRL may include a plurality of transistors forming a pixel circuit of a pixel. The transistor layer TRL may include a gate line, a data line, a voltage line, a gate control line, a fan-out line for connecting the display driver 200 to the data line, a lead for connecting the display driver 200 to a pad, etc. Each of the plurality of transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of a non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0070] The transistor layer TRL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines, and voltage lines in the transistor layer TRL for the pixels may be disposed in the display area DA. The gate control lines and fan-out lines in the transistor layer TRL may be disposed in the non-display area NDA. The leads of the transistor layer TRL may be disposed in the sub-area SBA.

[0071] The emission material layer EMTL may be disposed on the transistor layer TRL. The emission material layer EMTL may include a plurality of light emitting elements each including a first electrode, a second electrode and an emission layer to emit light and a pixel defining layer for defining pixels. The plurality of light emitting elements in the emission material layer EMTL may be disposed in the display area DA.

[0072] According to an exemplary embodiment of the present disclosure, the emission layer may be an organic emission layer including an organic material. The emission layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage and the second electrode receives a cathode voltage through the transistor of the transistor layer TRL, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, so that the holes and electrons are recombined in the organic light emitting layer to emit light.

[0073] According to another exemplary embodiment, the light emitting elements may include quantum dot light emitting diodes each including a quantum dot emission layer, inorganic light emitting diodes each including an inorganic semiconductor, or micro light emitting diodes.

[0074] The encapsulation layer ENC may cover the upper surface and the side surface of the emission material layer EMTL and can protect the emission material layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the emission material layer EMTL.

[0075] Although not shown in the drawings, according to another embodiment, a touch layer may be further provided on the encapsulation layer ENC. The touch layer may include a plurality of touch electrodes for sensing a user's touch by capacitive sensing, and a touch line connecting the plurality of touch electrodes to a touch driver. For example, the touch layer may sense a user's touch by mutual capacitance sensing or self capacitance sensing. According to another embodiment, the touch layer may be provided on a separate substrate arranged on the display layer DU. In this case, the substrate supporting the touch layer may be a base member of the encapsulated display layer DU.

[0076] The color filter layer CFL may be disposed on the encapsulation layer ENC. The color filter layer CFL may include a plurality of color filters respectively disposed on a plurality of emission regions. Each of the plurality of color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light introduced from the outside of the display device 10 to reduce reflection of external light. Therefore, the color filter layer CFL can prevent distortion of color due to reflection of external light.

[0077] Since the color filter layer CFL is directly disposed on the encapsulation layer ENC, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be reduced.

[0078] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may output or receive light within the infrared, ultraviolet, and visible light ranges. For example, the optical device 500 may be an optical sensor (such as a proximity sensor, an illumination sensor, a camera sensor, and an image sensor) that senses light incident on the display device 10.

[0079] Figure 4 is a plan view showing a display layer of a display device according to an exemplary embodiment of the present disclosure.

[0080] Reference Figure 4 , the display layer DU may include a display area DA and a non-display area NDA.

[0081] The display area DA can be set Figure 2 The display panel 100 is located at the center of the display panel 100. In the display area DA, a plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage lines VL may be disposed. Each of the plurality of pixels PX may be defined as a minimum unit that emits light.

[0082] The plurality of gate lines GL may supply the plurality of pixels PX with gate signals received from the gate driver 210. The plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1.

[0083] The plurality of data lines DL may supply the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0084] The plurality of voltage lines VL may supply a voltage received from the display driver 200 to the plurality of pixels PX. The voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low level voltage. The plurality of voltage lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0085] The non-display area NDA may surround the display area DA. In the non-display area NDA, a gate driver 210, a fan-out line FOL, and a gate control line GCL may be disposed. The gate driver 210 may generate a plurality of gate signals based on a gate control signal, and may sequentially supply the plurality of gate signals to the plurality of gate lines GL in a predetermined order.

[0086] The fan-out line FOL may extend from the display driver 200 to the display area DA. The plurality of fan-out lines FOL may supply data voltages received from the display driver 200 to the plurality of data lines DL, respectively.

[0087] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply the gate driver 210 with a gate control signal received from the display driver 200.

[0088] In the sub-area SBA, the display driver 200, the pad area PA, and the first and second touch pad areas TPA1 and TPA2 may be disposed.

[0089] The display driver 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driver 200 may supply data voltages to the plurality of data lines DL through the plurality of fan-out lines FOL, respectively. The data voltages may be applied to the plurality of pixels PX so that the brightness of the plurality of pixels PX may be controlled. The display driver 200 may supply a gate control signal to the gate driver 210 through the gate control line GCL.

[0090] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at the edge of the sub-area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 (for example, see FIG. 1 ) using a material such as an anisotropic conductive film and a self-assembled anisotropic conductive paste (SAP). Figure 2 ).

[0091] The pad area PA may include a plurality of display pads DP. The plurality of display pads DP may be connected to a graphics system through the circuit board 300. The plurality of display pads DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0092] Figure 5 is a plan view of a pixel electrode of a display device according to an exemplary embodiment.

[0093] like Figure 5 As shown in , the display device may include a first pixel electrode PE1, a second pixel electrode PE2, a third pixel electrode PE3, a fourth pixel electrode PE4 and a current trap layer (or charge trap layer) CCL.

[0094] The first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4 may be disposed adjacent to each other. For example, the first pixel electrode PE1 and the second pixel electrode PE2 may be disposed adjacent to each other in the first direction DR1, the second pixel electrode PE2 and the third pixel electrode PE3 may be disposed adjacent to each other in the second direction DR2, and the third pixel electrode PE3 and the fourth pixel electrode PE4 may be disposed adjacent to each other in the first direction DR1.

[0095] The current capture layer CCL may be disposed on the same layer as the pixel electrode. For example, the current capture layer CCL may be disposed in the same layer as the first pixel electrode PE1 to the fourth pixel electrode PE4. The current capture layer CCL and the pixel electrode may be made of the same material at the same time. For example, the current capture layer CCL and the first pixel electrode PE1 to the fourth pixel electrode PE4 may be made of the same material. For example, with respect to the emission layer (e.g., Figure 6 The light providing layer LPL) is provided to the common electrode (eg, Figure 6 In a top emission structure where a common electrode CE is formed, the pixel electrodes PE1 to PE4 and the current capture layer CCL may include a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or may include a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu).

[0096] For example, the current capture layer CCL may be disposed between adjacent pixel electrodes. For example, the current capture layer CCL may be disposed between the first pixel electrode PE1 and the second pixel electrode PE2. In addition, the current capture layer CCL may be disposed between the second pixel electrode PE2 and the third pixel electrode PE3. In addition, the current capture layer CCL may be disposed between the first pixel electrode PE1 and the fourth pixel electrode PE4. When the current capture layer CCL is disposed between each adjacent pixel electrode, the current capture layer CCL may have a grid shape surrounding each of the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4. In other words, the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4 may be surrounded by the current capture layer CCL. For example, when viewed from the top, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may be surrounded by the current capture layer CCL. In other words, the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4 may be respectively disposed in areas defined by the current capture layer CCL (hereinafter, referred to as opening areas OP1, OP2, OP3 and OP4). For example, the first pixel electrode PE1 may be disposed in a first opening area OP1 defined by the current capture layer CCL, the second pixel electrode PE2 may be disposed in a second opening area OP2 defined by the current capture layer CCL, the third pixel electrode PE3 may be disposed in a third opening area OP3 defined by the current capture layer CCL, and the fourth pixel electrode PE4 may be disposed in a fourth opening area OP4 defined by the current capture layer CCL.

[0097] The current capture layer CCL may include a plurality of first extension portions EX1 extending in a first direction DR1, and a plurality of second extension portions EX2 extending in a second direction DR2. The first extension portion EX1 may intersect with the second extension portion EX2. The first extension portion EX1 and the second extension portion EX2 may be connected at the intersection of the first extension portion EX1 and the second extension portion EX2. The first extension portion EX1 and the second extension portion EX2 may be formed as a single piece. The first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4 may be respectively disposed in the opening areas OP1, OP2, OP3, and OP4 defined by the first extension portion EX1 and the second extension portion EX2.

[0098] A portion of the first pixel electrode PE1 (e.g., an edge of the first pixel electrode PE1), a portion of the second pixel electrode PE2 (e.g., an edge of the second pixel electrode PE2), a portion of the third pixel electrode PE3 (e.g., an edge of the third pixel electrode PE3), and a portion of the fourth pixel electrode PE4 (e.g., an edge of the fourth pixel electrode PE4) may be formed by the bank PDL (see Figure 6 ), which will be described later. In other words, a portion of the first pixel electrode PE1 (e.g., an edge of the first pixel electrode PE1), a portion of the second pixel electrode PE2 (e.g., an edge of the second pixel electrode PE2), a portion of the third pixel electrode PE3 (e.g., an edge of the third pixel electrode PE3), and a portion of the fourth pixel electrode PE4 (e.g., an edge of the fourth pixel electrode PE4) may partially overlap with the above-mentioned bank PDL.

[0099] Portions of the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4 that are not covered by the bank PDL but are exposed may be the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4, respectively. For example, the first emission area EA1 may be an emission area of ​​the first pixel including the first pixel electrode PE1, the second emission area EA2 may be an emission area of ​​the second pixel including the second pixel electrode PE2, the third emission area EA3 may be an emission area of ​​the third pixel including the third pixel electrode PE3, and the fourth emission area EA4 may be an emission area of ​​the fourth pixel including the fourth pixel electrode PE4.

[0100] Figure 6 It is along Figure 5 A cross-sectional view taken along line II'.

[0101] like Figure 6 As shown in FIG. 1 , the display device 10 (see Figure 2 ) may include a transistor layer TRL, an emission material layer EMTL, an encapsulation layer ENC and a color filter layer CFL.

[0102] The substrate SUB may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The substrate SUB may be a substrate doped with first type impurities.

[0103] The well W may be disposed in the substrate SUB. The well W may be doped with a second type impurity. The second type impurity may be different from the first type impurity. For example, when the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. On the other hand, when the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.

[0104] The source region S, drain region D, and channel region CH of the transistor TR may be disposed in the well W. For example, the source region S (or source electrode) and drain region D (or drain electrode) of the transistor TR may be positioned in the well W. Each of the source region S and the drain region D may be doped with a first type of impurity. The gate electrode G of the transistor TR may intersect and overlap the well W. When viewed from the top, the well W is divided into two regions by the gate electrode G. One of the two regions may be the source region S, and the other of the two regions may be the drain region D. In other words, in the well W, the source region S and the drain region D may be positioned on both sides of the gate electrode G, respectively, and the gate electrode G is disposed between the source region S and the drain region D. The channel region CH of the transistor may be positioned in the region where the gate electrode G overlaps the well W.

[0105] The source region S may include a first lightly doped region having a lower impurity concentration than other portions of the source region S. In other words, a portion of the source region S may include impurities having a lower concentration than other portions of the source region S. The drain region D may include a second lightly doped region having a lower impurity concentration than other portions of the drain region D. In other words, a portion of the drain region D may include impurities having a lower concentration than other portions of the drain region D.

[0106] The first lightly doped region and the second lightly doped region may be disposed close to the channel region CH of the transistor TR. For example, the first lightly doped region may be disposed close to the channel region CH so that the first lightly doped region overlaps with a first spacer disposed on one side of the gate electrode G, and the second lightly doped region may be disposed close to the channel region CH so that the second lightly doped region overlaps with a second spacer disposed on the opposite side of the gate electrode G. As described above, due to the first lightly doped region and the second lightly doped region, the distance between the heavily doped region of the source region S and the heavily doped region of the drain region D may be increased. As a result, the length of the channel region CH may be increased. Therefore, short channel effects such as punch-through and hot carriers may be prevented.

[0107] The interlayer dielectric film VA may be disposed on the substrate SUB. The interlayer dielectric film VA may include a plurality of insulating films stacked in the third direction DR3.

[0108] The passivation film PAS may be disposed on the interlayer dielectric film VA.

[0109] The emission material layer EMTL may be disposed on the passivation film PAS. The emission material layer EMTL may include, for example, a first light emitting element ED1, a second light emitting element ED2, a third light emitting element ED3, and a fourth light emitting element (eg, disposed in Figure 5For example, the first light emitting element ED1 of the emission material layer EMTL may be disposed in the first emission area EA1, the second light emitting element ED2 of the emission material layer EMTL may be disposed in the second emission area EA2, the third light emitting element ED3 of the emission material layer EMTL may be disposed in the third emission area EA3, and the fourth light emitting element of the emission material layer EMTL may be disposed in the fourth emission area EA4.

[0110] Each of the first light emitting element ED1 , the second light emitting element ED2 , the third light emitting element ED3 , and the fourth light emitting element may emit white light.

[0111] The first light emitting element ED1 may include a first pixel electrode PE1 (or a first anode electrode), a first light-supply layer LPL1 , and a common electrode CE that are stacked on each other in the third direction DR3 .

[0112] The second light emitting element ED2 may include a second pixel electrode PE2 (or a second anode electrode), a second light-supply layer LPL2 , and a common electrode CE that are stacked on each other in the third direction DR3 .

[0113] The third light emitting element ED3 may include a third pixel electrode PE3 (or a third anode electrode), a third light-supply layer LPL3 , and a common electrode CE which are stacked on each other in the third direction DR3 .

[0114] The fourth light emitting element may include fourth pixel electrodes PE4 (see FIG. 1 ) stacked one on another in the third direction DR3. Figure 5 ) (or a fourth anode electrode), a fourth light-providing layer and a common electrode CE.

[0115] The first light providing layer LPL1, the second light providing layer LPL2, the third light providing layer LPL3, and the fourth light providing layer may include a plurality of emission layers providing light of different colors, and the plurality of emission layers may be stacked on each other in the third direction DR3. Different lights from the emission layers may be mixed to generate white light. Each of the first light providing layer LPL1, the second light providing layer LPL2, the third light providing layer LPL3, and the fourth light providing layer may further include a charge generation layer.

[0116] The first pixel electrode PE1 , the second pixel electrode PE2 , the third pixel electrode PE3 , and the fourth pixel electrode PE4 may be connected to the source region S of the corresponding transistor TR through the pixel connection electrode PCE and the metal connection layer ME.

[0117] The current capture layer CCL may receive power from the outside. For example, the edge of the current capture layer CCL may extend in at least one of the first direction DR1 and the second direction DR2, and may be connected to a power supply unit. The power supply unit may supply a capture voltage or a capture current (e.g., a DC voltage or a DC current) to the current capture layer CCL. Herein, the capture voltage (e.g., a DC voltage) may be a voltage lower than the voltage applied to the pixel electrode (hereinafter referred to as the pixel voltage). For example, when the pixel voltage is a positive voltage, the capture voltage (e.g., a DC voltage) may be a voltage lower than the minimum pixel voltage. For example, when the pixel voltage is a positive voltage, the capture voltage (e.g., a DC voltage) may be a voltage of negative polarity. For example, the capture voltage may be the same as the common voltage applied to the common electrode CE.

[0118] The first pixel electrode PE1 may be arranged to correspond to the first emission area EA1, the second pixel electrode PE2 may be arranged to correspond to the second emission area EA2, the third pixel electrode PE3 may be arranged to correspond to the third emission area EA3, and the fourth pixel electrode PE4 may be arranged to correspond to the fourth emission area EA4 (see Figure 5 )correspond.

[0119] A bank PDL (or a pixel defining film) may be disposed on the first pixel electrode PE1 , the second pixel electrode PE2 , the third pixel electrode PE3 , and the fourth pixel electrode PE4 .

[0120] The embankment PDL may define each of the emission areas EA1, EA2, EA3, and EA4 of the pixel. To this end, for example, the embankment PDL may be arranged to expose some areas of the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4 arranged on the passivation film PAS. The embankment PDL may cover the edge of the first pixel electrode PE1, the edge of the second pixel electrode PE2, the edge of the third pixel electrode PE3, and the edge of the fourth pixel electrode PE4 and completely cover the surface and sidewall of the current capture layer CCL. The embankment PDL may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0121] The separator SPR may be arranged on the bank PDL. Each of the plurality of separators SPR may have an overhanging structure in which the upper surface is wider than the lower surface. Therefore, the separator SPR may have a tapered shape. The light providing layer LPL may be disconnected by the separator SPR having such a structure so that each of the plurality of layers is arranged in a corresponding emission area. In other words, during the process of depositing the light providing material layer, the light providing material layer is disconnected by the separator SPR, and the first light providing layer LPL1, the second light providing layer LPL2, the third light providing layer LPL3 and the fourth light providing layer respectively arranged in different emission areas EA1, EA2, EA3 and EA4 may be arranged on the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4. It should be noted that the light providing layer LPL may also be arranged on the separator SPR. In this way, the first light providing layer LPL1, the second light providing layer LPL2, the third light providing layer LPL3, the fourth light providing layer and the light providing layer LPL on the separator SPR may remain separated.

[0122] The first light-supplying layer LPL1, the second light-supplying layer LPL2, the third light-supplying layer LPL3, the fourth light-supplying layer, and the light-supplying layer LPL on the separating part SPR may include a plurality of light emitting units (or emission units) (eg, see Figures 11 to 16 emitting units EU1, EU2 and / or EU3). For example, each of the plurality of light providing layers LPL1, LPL2, LPL3 may include a first light emitting unit, a second light emitting unit and a third light emitting unit stacked on each other in a third direction DR3. Each of the plurality of light emitting units may provide light of a different wavelength. For example, the first light emitting unit, the second light emitting unit and the third light emitting unit may emit light of different colors. For example, the light providing layer LPL may have a series structure in which a plurality of light emitting units providing light of different colors are stacked on each other in a vertical direction (e.g., in the third direction DR3).

[0123] The first light emitting unit may be disposed on the pixel electrodes PE1, PE2, PE3, and PE4 and the separation portion SPR. The first light emitting unit may include a first emission layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0124] The second light emitting unit may be disposed on the first light emitting unit. The second light emitting unit may include a second emission layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0125] The third light emitting unit may be disposed on the second light emitting unit. The third light emitting unit may include a third emission layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0126] Each of the light emitting elements ED1, ED2, ED3 and the fourth light emitting element can mix the light of the first color (e.g., blue) from the first light emitting unit, the light of the second color (e.g., red) from the second light emitting unit and the light of the third color (e.g., green) from the third light emitting unit to provide white light. For example, each of the first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3 and the fourth light emitting element can emit white light.

[0127] In addition, the first light providing layer LPL1, the second light providing layer LPL2, the third light providing layer LPL3, the fourth light providing layer, and the light providing layer LPL on the separation portion SPR may further include at least one charge generation layer. For example, the charge generation layer may be arranged between adjacent light emitting units in the third direction DR3. The charge generation layer may include, for example, a first charge generation layer and a second charge generation layer stacked on each other in the third direction DR3. In this case, the first charge generation layer may be arranged between the first light emitting unit and the second light emitting unit, and the second charge generation layer may be arranged between the second light emitting unit and the third light emitting unit.

[0128] Each charge generation layer may include a negative charge generation layer and a positive charge generation layer. For example, the first charge generation layer may include a first negative charge generation layer and a first positive charge generation layer stacked in the third direction DR3, and the second charge generation layer may include a second negative charge generation layer and a second positive charge generation layer stacked in the third direction DR3.

[0129] The common electrode CE may be disposed on the first light providing layer LPL1, the second light providing layer LPL2, the third light providing layer LPL3, the fourth light providing layer, and the light providing layer LPL on the separation portion SPR. For example, the common electrode CE may be disposed on the light providing layers LPL1, LPL2, LPL3, and LPL so that the common electrode CE overlaps with the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the fourth pixel electrode PE4, the first emission area EA1, the second emission area EA2, the third emission area EA3, the fourth emission area EA4, and the embankment PDL. In the top emission structure, the common electrode CE may be formed of a transparent conductive material (TCP) capable of transmitting light such as ITO and indium zinc oxide (IZO), or of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag). When the common electrode CM is formed of a semi-transmissive metal material, the light extraction efficiency can be increased by using a microcavity.

[0130] The coating layer CPL may be disposed on the common electrode CE. The coating layer CPL may include an inorganic insulating material. In an exemplary embodiment, the coating layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. Zinc oxide (ZnO x ) can be ZnO or ZnO 2 .

[0131] The encapsulation layer ENC may be disposed on the coating layer CPL. The encapsulation layer ENC may cover the upper surface and the side surface of the emission material layer EMTL, and may protect the emission material layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the emission material layer EMTL. The encapsulation layer ENC may include one or more inorganic films (e.g., a first inorganic encapsulation film TFE1 and a second inorganic encapsulation film TFE3) to prevent oxygen or moisture from penetrating into the emission material layer EMTL. In addition, the encapsulation layer ENC may include at least one organic film to protect the emission material layer EMTL from particles such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

[0132] The first inorganic encapsulation film TFE1 may be disposed on the coating layer CPL, the organic encapsulation film TFE2 may be disposed on the first inorganic encapsulation film TFE1, and the second inorganic encapsulation film TFE3 may be disposed on the organic encapsulation film TFE2. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may each include a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The organic encapsulation film TFE2 may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0133] The light blocking layer BM may be disposed on the encapsulation layer ENC. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 overlapping the emission areas EA1, EA2, and EA3, respectively. For example, the first hole OPT1 may overlap the first emission area EA1. The second hole OPT2 may overlap the second emission area EA2, and the third hole OPT3 may overlap the third emission area EA3.

[0134] The areas or sizes of the holes OPT1, OPT2, and OPT3 may be respectively larger than the areas or sizes of the emission areas EA1, EA2, and EA3 defined by the dam PDL. Since the holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be respectively larger than the emission areas EA1, EA2, and EA3, the light output from the emission areas EA1, EA2, and EA3 can be seen by the user not only from the front but also from the side.

[0135] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be (but not limited to) carbon black, and the organic black pigment may include (but not limited to) at least one of lactam black, perylene black, and aniline black. The light blocking layer BM may prevent visible light from penetrating and mix the colors between the first emission area EA1, the second emission area EA2, and the third emission area EA3 to improve the color gamut of the display device 10.

[0136] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 respectively disposed in the emission areas EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may be associated with the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on a light blocking layer BM including a plurality of holes OPT1, OPT2, and OPT3 respectively associated with the emission areas EA1, EA2, and EA3. It should be noted that, for example, the color filter disposed in the fourth emission area EA4 may have the same color as the color filter disposed in the third emission area EA3.

[0137] The color filters CF1, CF2 and CF3 include a first color filter CF1, a second color filter CF2 and a third color filter CF3 associated with different emission areas EA1, EA2 and EA3, respectively. The color filters CF1, CF2 and CF3 may include a colorant (such as a dye and a pigment) that absorbs light in a wavelength range other than light in a specific wavelength range, and the color filters CF1, CF2 and CF3 may be arranged in an area corresponding to the light emitted from the emission areas EA1, EA2 and EA3. For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 and transmits only red light. The second color filter CF2 may be a green color filter that is arranged to overlap with the second emission area EA2 and transmits only green light. The third color filter CF3 may be a blue color filter that is arranged to overlap with the third emission area EA3 and transmits only blue light. The color filter arranged in the fourth emission area may be a blue color filter.

[0138] The color filters CF1, CF2, and CF3 may be spaced apart from each other on the light blocking layer BM. The color filters CF1, CF2, and CF3 may cover the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, respectively, and the color filters CF1, CF2, and CF3 may have a larger area than the holes OPT1, OPT2, and OPT3, respectively, so that the color filters CF1, CF2, and CF3 are spaced apart from each other on the light blocking layer BM. However, it is to be understood that the present disclosure is not limited thereto. The color filters CF1, CF2, and CF3 may partially overlap with each other. Different color filters CF1, CF2, and CF3 may not overlap with the emission areas EA1, EA2, and EA3, and different color filters CF1, CF2, and CF3 may overlap with each other on the light blocking layer BM. In the display device 10, since the color filters CF1, CF2, and CF3 overlap with each other, the intensity of the reflected light caused by the external light can be reduced. Also, the color of light reflected by external light can be controlled by adjusting the arrangement, shape, and area of ​​the color filters CF1, CF2, and CF3 when viewed from the top.

[0139] An overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to provide upper ends of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic-based resin.

[0140] It should be noted that, in a plan view, the above-described current trap layer CCL may overlap with, for example, the bank PDL, the separation part SPR, and the light blocking layer BM.

[0141] Figure 7 is a view for illustrating an effect of reducing a lateral leakage current in a display device according to an embodiment of the present disclosure.

[0142] like Figure 7As shown in , the current capture layer CCL may be disposed between the first light supply layer LPL1 disposed on the first pixel electrode PE1 and the second light supply layer LPL2 disposed on the second pixel electrode PE2. The current capture layer CCL can reduce the amount of the lateral leakage current IL that can flow from the first light supply layer LPL1 to the second light supply layer LPL2. For example, when the capture voltage Vc (e.g., a negative DC voltage) is applied to the current capture layer CCL as a bias voltage, holes may accumulate on the surface of the current capture layer CCL. These holes can capture electrons of the lateral leakage current IL. For example, a current path from the first light supply layer LPL1 to the current capture layer CCL may be formed by the current capture layer CCL, and thus the capture current IC may flow along the current path. In other words, at least a portion of the lateral leakage current IL (e.g., the capture current IC) may flow to the current capture layer CCL along the above-mentioned current path. As a result, the lateral leakage current IL flowing to adjacent pixels can be reduced, and thus color mixing between adjacent pixels can be prevented.

[0143] Figure 8 It is shown along Figure 5 A cross-sectional view of another example taken along line II'.

[0144] Figure 8 Display device 10 (see Figure 2 )and Figure 6 The display device 10 of FIG. 1 is different in that the current trap layer CCL is directly connected to (or in contact with) the light-supplying layer on the bank PDL. The description will focus on the difference.

[0145] like Figure 8 As shown in , the current trap layer CCL may be in contact with the adjacent light-providing layer.

[0146] As an example, the current trap layer CCL may include a support layer CCLa and a connection layer CCLb.

[0147] The support layer CCLa of the current trap layer CCL may be disposed between adjacent pixel electrodes. For example, the support layer CCLa may be disposed between the first pixel electrode PE1 and the second pixel electrode PE2.

[0148] The connection layer CCLb of the current capture layer CCL may extend from the support layer CCLa toward the first pixel electrode PE1 and the second pixel electrode PE2 to be connected to the first pixel electrode PE1 and the second pixel electrode PE2. The connection layer CCLb and the support layer CCLa may form a body. The connection layer CCLb may be disposed between adjacent light providing layers. For example, the connection layer CCLb may be disposed between the first light providing layer LPL1 and the second light providing layer LPL2. The connection layer CCLb may extend to the adjacent light providing layer to be directly connected to the light providing layer (or to be in contact with the light providing layer). For example, the connection layer CCLb may be directly connected to at least one of the first light providing layer LPL1 and the second light providing layer LPL2 (or to be in contact with at least one of the first light providing layer LPL1 and the second light providing layer LPL2).

[0149] Fig. 9 It is shown along Figure 5 A cross-sectional view of another example taken along line II'.

[0150] Fig. 9 Display device 10 (see Figure 2 )and Figure 6 The display device 10 of FIG. 1 is different in that the separation portion SPR has a groove structure. The description will focus on the difference.

[0151] like Fig. 9 As shown in , each of the plurality of banks PDL may include a hole HL formed through the bank PDL in the third direction DR3, and the insulating film (e.g., the passivation film PAS) may include a groove GR in a region corresponding to the hole HL. The separation portion SPR fills the hole HL and the groove GR. The groove GR filled by each of the plurality of separation portions SPR may be formed, for example, in an insulating film (e.g., the passivation film PAS) under the bank PDL.

[0152] For example, Fig. 9 The separation portion SPR may be disposed between adjacent pixel electrodes and the current trap layer CCL. Fig. 9 The separation portion SPR may have a shape surrounding the pixel electrode and the current trap layer CCL.

[0153] Reference Figures 10 to 16 Describe the light emitting element (e.g. Figure 6 Other structures of the light-emitting elements ED1, ED2 and ED3).

[0154] Fig.10 is a cross-sectional view showing the structure of a light emitting element according to an embodiment of the present disclosure. Figures 11 to 14 is a cross-sectional view showing the structure of a light emitting element according to the embodiment.

[0155] Reference Fig.10And combined with Figure 5 , Figure 6 , Fig.11 and Fig.15 According to an exemplary embodiment, a light emitting element (e.g., an organic light emitting diode) may include a pixel electrode 201, a common electrode 205, and a light providing layer 204 disposed between the pixel electrode 201 and the common electrode 205. The pixel electrode 201 may be one of the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4 described above. In addition, the common electrode 205 may be the common electrode CE described above. In addition, the light providing layer 203 may be one of the first light providing layer LPL1, the second light providing layer LPL2, and the third light providing layer LPL3 described above, the fourth light providing layer, and the light providing layer LPL disposed on the separation portion SPR.

[0156] The pixel electrode 201 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and aluminum zinc oxide (AZO). The pixel electrode 201 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. For example, the pixel electrode 201 may have a three-layer structure of ITO / Ag / ITO.

[0157] The common electrode 205 may be disposed on the light providing layer 203. The common electrode 205 may include a conductor, an alloy, a conductive compound, or any combination thereof having a low work function. For example, the common electrode 205 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum lithium (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), ytterbium (Yb), silver ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The common electrode 205 may be a transmissive electrode, a transflective electrode, or a reflective electrode.

[0158] The light-providing layer 203 may include a high molecular weight organic material or a low molecular weight organic material that emits light of a predetermined color. In addition to various organic materials, the light-providing layer 203 may also include a metal-containing compound such as an organic metal compound, an inorganic material such as a quantum dot, and the like.

[0159] According to an exemplary embodiment, the light providing layer 203 may include an emission layer and a first functional layer and a second functional layer respectively disposed below and above the emission layer. The first functional layer may include, for example, a hole transport layer HTL, or may include a hole transport layer HTL and a hole injection layer HIL. The second functional layer is an optional element disposed on the emission layer. For example, the light providing layer 203 may include or not include a second functional layer. The second functional layer may include an electron transport layer ETL and / or an electron injection layer EIL.

[0160] According to an exemplary embodiment, the light-providing layer 203 may include two or more emission units sequentially stacked between the pixel electrode 201 and the common electrode 205, and a charge generation layer CGL disposed between adjacent emission units. When the light-providing layer 203 includes the emission unit and the charge generation layer CGL, the light-emitting element (e.g., an organic light-emitting diode) may have a series structure. The light-emitting element (e.g., an organic light-emitting diode) can improve color purity and emission efficiency by adopting a stacked structure of a plurality of emission units.

[0161] An emission unit may include an emission layer, and a first functional layer and a second functional layer respectively disposed below and above the emission layer. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. The emission efficiency of an organic light emitting diode as a tandem light emitting element having multiple emission layers can be further increased by the negative charge generation layer and the positive charge generation layer.

[0162] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0163] According to an exemplary embodiment, Fig.11As shown in , a light emitting element (e.g., an organic light emitting diode) may include a first emission unit EU1 including a first emission layer EL1 and a second emission unit EU2 including a second emission layer EL2 stacked on each other. A charge generation layer CGL may be disposed between the first emission unit EU1 and the second emission unit EU2. For example, a light emitting element (e.g., an organic light emitting diode) may include a pixel electrode 201, a first emission layer EL1, a charge generation layer CGL, a second emission layer EL2, and a common electrode 205 sequentially stacked on each other. The first functional layer and the second functional layer may be disposed below and above the first emission layer EL1, respectively. The first functional layer and the second functional layer may be disposed below and above the second emission layer EL2, respectively. The first emission layer EL1 may be a blue emission layer, and the second emission layer EL2 may be a yellow emission layer.

[0164] According to an exemplary embodiment, Fig.12 As shown in , a light emitting element (e.g., an organic light emitting diode) may include a first light emitting unit EU1 including a first emission layer EL1, a third light emitting unit EU3 including the first emission layer EL1, and a second light emitting unit EU2 including a second emission layer EL2. A first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and a second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. For example, a light emitting element (e.g., an organic light emitting diode) may include a pixel electrode 201, a first emission layer EL1, a first charge generation layer CGL1, a second emission layer EL2, a second charge generation layer CGL2, a first emission layer EL1, and a common electrode 205, which are stacked one on another in this order. The first functional layer and the second functional layer may be disposed below and above the first emission layer EL1, respectively. The first functional layer and the second functional layer may be disposed below and above the second emission layer EL2, respectively. The first emission layer EL1 may be a blue emission layer, and the second emission layer EL2 may be a yellow emission layer.

[0165] According to an exemplary embodiment of the present disclosure, in addition to the second emission layer EL2, the second emission unit EU2 of the light emitting element (e.g., the organic light emitting diode) may further include a third emission layer EL3 (see FIG. 1 ) directly contacting the second emission unit EU2 below and / or above the second emission layer EL2. Fig.13 ) and / or the fourth emission layer EL4 (see Fig.14 ). As used herein, the phrase the third emission layer EL3 and / or the fourth emission layer EL4 is in direct contact with the second emission unit EU2 means that no other layer is provided between the second emission layer EL2 and the third emission layer EL3 and / or between the second emission layer EL2 and the fourth emission layer EL4. The third emission layer EL3 may be a red emission layer, and the fourth emission layer EL4 may be a green emission layer.

[0166] For example, Fig.13 As shown in , the light emitting element (e.g., an organic light emitting diode) may include a pixel electrode 201, a first emission layer EL1, a first charge generation layer CGL1, a third emission layer EL3, a second emission layer EL2, a second charge generation layer CGL2, a first emission layer EL1, and a common electrode 205, which are stacked on top of each other in this order. Alternatively, as Fig.14 As shown in the figure, the light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first emission layer EL1, a first charge generation layer CGL1, a third emission layer EL3, a second emission layer EL2, a fourth emission layer EL4, a second charge generation layer CGL2, a first emission layer EL1 and a common electrode 205, which are stacked on top of each other in this order.

[0167] Fig.15 It is shown Fig.13 A cross-sectional view of an example of an organic light emitting diode. Fig.16 It is shown Fig.14 A cross-sectional view of an example of an organic light emitting diode.

[0168] Reference Fig.15 , the light emitting element (e.g., an organic light emitting diode) may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3, which are stacked on each other in this order. The first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0169] The first emission unit EU1 may include a blue emission layer BEML. The first emission unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL disposed between the pixel electrode 201 and the blue emission layer BEML. According to an exemplary embodiment of the present disclosure, a p-doped layer may further be included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type doping material. According to an exemplary embodiment of the present disclosure, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue emission layer BEML and the hole transport layer HTL. The blue light auxiliary layer is capable of increasing the emission efficiency of the blue emission layer BEML. The blue light auxiliary layer is capable of increasing the emission efficiency of the blue emission layer BEML by adjusting the hole charge balance. The electron blocking layer may be used to prevent electrons from being injected into the hole transport layer HTL. The buffer layer may be used to compensate for the resonance distance according to the wavelength of light emitted from the emission layer.

[0170] The second emission unit EU2 may include a yellow emission layer YEML and a red emission layer REML directly contacting the yellow emission layer YEML below the yellow emission layer YEML. The second emission unit EU2 may also include a hole transport layer HTL disposed between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and an electron transport layer ETL disposed between the yellow emission layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0171] The third emission unit EU3 may include a blue emission layer BEML. The third emission unit EU3 may also include a hole transport layer HTL disposed between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue emission layer BEML. The third emission unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue emission layer BEML and the common electrode 205. The electron transport layer ETL may include a single layer or multiple layers. According to an exemplary embodiment of the present disclosure, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may also be included between the blue light emitting layer BEML and the hole transport layer HTL. At least one of the hole blocking layer and the buffer layer may also be included between the blue light emitting layer BEML and the electron transport layer ETL. The hole blocking layer may be used to prevent holes from being injected into the electron transport layer ETL.

[0172] In addition to the stacked structure of the second emission unit EU2, Fig.16 The light emitting element (eg, organic light emitting diode) shown in Fig.15 The light emitting elements (eg, organic light emitting diodes) shown in FIG. 1 are substantially the same. Fig.16 , the second emission unit EU2 may include: a yellow emission layer YEML; a red emission layer REML, directly contacting the yellow emission layer YEML below the yellow emission layer YEML; and a green emission layer GEML, directly contacting the yellow emission layer YEML above the yellow emission layer YEML. The second emission unit EU2 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and an electron transport layer ETL between the green emission layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0173] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the inventive concept. Therefore, the preferred embodiments of the disclosed inventive concept are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device comprises: substrate; A first pixel electrode and a second pixel electrode are disposed on the substrate; A first light-providing layer, disposed on the first pixel electrode; A second light-providing layer is disposed on the second pixel electrode; a common electrode, disposed on the first light-providing layer and the second light-providing layer; and A current trapping layer is provided between the first pixel electrode and the second pixel electrode in a plan view.

2. The display device according to claim 1, wherein: A trap voltage applied to the current trap layer is lower than a pixel voltage applied to the first pixel electrode.

3. The display device according to claim 2, wherein: The capture voltage is the same as a common voltage applied to the common electrode.

4. The display device according to claim 1, wherein: The display device further includes: A bank overlaps the current trap layer in a plan view, and the bank defines a first emission region of the first pixel electrode and a second emission region of the second pixel electrode.

5. The display device according to claim 4, wherein: The display device further includes: The light blocking layer overlaps the current trapping layer in a plan view.

6. The display device according to claim 5, wherein: The display device further includes: A separation portion is provided on the bank to overlap with the light blocking layer in a plan view.

7. The display device according to claim 6, wherein: The current trap layer overlaps the bank, the separation portion, and the light blocking layer.

8. The display device according to claim 5, wherein: The display device further includes: a separation portion overlapping the light blocking layer, Wherein the dam includes a hole formed through the dam.

9. The display device according to claim 8, wherein: The display device further includes an insulating layer disposed under the bank, and the insulating layer includes a groove disposed in a region corresponding to the hole.

10. The display device according to claim 9, wherein: The separation portion fills the hole and the groove.

11. The display device according to claim 10, wherein: Portions of the separation portion filling the hole and the groove do not cover the sidewalls of the current trap layer.

12. The display device according to claim 4, wherein: The display device further includes: a first color filter overlapping the first emission region; and A second color filter overlaps the second emission area.

13. The display device according to claim 1, wherein: The current trap layer has a shape surrounding each of the first pixel electrode and the second pixel electrode, and Wherein, a portion of the current capture layer is disposed between the first pixel electrode and the second pixel electrode.

14. The display device according to claim 13, wherein: The current trapping layer comprises: a first extending portion extending in a first direction; and The second extending portion extends in a second direction intersecting the first direction.

15. The display device according to claim 14, wherein: The current trapping layer defines a plurality of open areas surrounded by the first extension portion and the second extension portion, and Wherein, the first pixel electrode and the second pixel electrode are arranged in corresponding opening areas among the plurality of opening areas.

16. The display device according to claim 1, wherein: The current trapping layer is directly connected to at least one of the first light-providing layer and the second light-providing layer.

17. The display device according to claim 16, wherein: The current trapping layer comprises: a supporting layer, disposed between the first pixel electrode and the second pixel electrode; and A connection layer extends from the support layer, is disposed between the first light-providing layer and the second light-providing layer, and is connected to at least one of the first light-providing layer and the second light-providing layer.

18. The display device according to claim 1, wherein: Each of the first light-providing layer and the second light-providing layer includes a plurality of light emitting units providing light of different colors.

19. A display device, wherein: The display device comprises: substrate; and A plurality of light-emitting elements are disposed on the substrate, each of the plurality of light-emitting elements comprising: A pixel electrode and a current capture layer are arranged on the same plane and include the same material, wherein the current capture layer completely surrounds the pixel electrode; a bank, disposed on the pixel electrode to cover an edge of the pixel electrode, and disposed on the current trapping layer to cover the current trapping layer; a light-providing layer, disposed on the pixel electrode; and The common electrode is arranged on the light-providing layer.

20. The display device according to claim 19, wherein: The bank completely covers a top surface and sidewalls of the current trapping layer.

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