Pixel

Abstract

A pixel according to an embodiment of the present disclosure includes: a first transistor having a gate electrode connected to a first node, a first electrode connected to a first power supply line, and a second electrode connected to a second node; a second transistor connected between the data line and a third node, and having a gate electrode electrically connected to the first scan line; a third transistor connected between the second node and the third node, and having a gate electrode electrically connected to a second scan line; a first capacitor connected between the first node and the third node; and a light emitting element connected between the second node and a second power supply line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0105457, filed on August 11, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a pixel and a display device including the pixel. Background Art

[0004] With the development of information technology, the role of display devices as a connection medium between users and information has become increasingly important. Therefore, more and more people rely on display devices such as liquid crystal display devices and organic light emitting display devices.

[0005] Recently, various display devices including head mounted displays (HMDs) require high-resolution display panels. Summary of the invention

[0006] The present disclosure provides a pixel suitable for a high-resolution display panel and a display device including the pixel.

[0007] According to an embodiment of the present disclosure, a pixel may include: a first transistor having a gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second node; a second transistor connected between a data line and a third node, and the second transistor having a gate electrode electrically connected to a first scan line; a third transistor connected between the second node and the third node, and the third transistor having a gate electrode electrically connected to a second scan line; a first capacitor connected between the first node and the third node; and a light emitting element connected between the second node and the second power line.

[0008] According to an embodiment, the pixel may also include: a fourth transistor connected between the first node and the second node, and the fourth transistor has a gate electrode electrically connected to a third scan line; and a fifth transistor connected between the second node and the light emitting element, and the fifth transistor has a gate electrode electrically connected to an emission control line.

[0009] According to an embodiment, the pixel may further include a second capacitor connected between the first power line and the first node.

[0010] According to an embodiment, the pixel may also include: a fourth transistor connected between the first node and the second node, and the fourth transistor has a gate electrode electrically connected to a third scan line; and a fifth transistor connected between the second node and the light emitting element, and the fifth transistor has a gate electrode electrically connected to an emission control line.

[0011] According to an embodiment, the horizontal period during which the data signal is supplied to the pixel may include: a first period, a second period, a third period, and a fourth period, the voltage of the reference power supply may be supplied to the data line during the first period, the second period, and the third period, and the voltage of the data signal may be supplied to the data line during the fourth period. In addition, the second transistor may be turned on during the first period to the fourth period, and the fifth transistor may be turned off during the first period and the second period.

[0012] According to an embodiment, the fifth transistor may be turned off during a portion of a previous period immediately before the horizontal period.

[0013] According to an embodiment, the fifth transistor may be turned off during the fourth period.

[0014] According to an embodiment, the third transistor may be turned on during the first period, the third period, and the fourth period, and the fourth transistor may be turned on during the first period and the second period.

[0015] According to an embodiment, the fourth transistor may be turned on during a portion of a previous period immediately before the horizontal period.

[0016] According to an embodiment, the third transistor may be turned on during the first period and the third period, and the fourth transistor may be turned on during the first period and the second period.

[0017] The display device according to an embodiment of the present disclosure may include: a pixel connected to a scan line, a data line and an emission control line; a scan driver driving the scan line; a data driver driving the data line; and an emission driver driving the emission control line. Among the pixels, the pixel located on the i-th horizontal line (i is a positive integer) and the j-th vertical line (j is a positive integer) may include: a first transistor having a gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second node; a second transistor connected between the j-th data line and a third node, and the second transistor is turned on in response to an enable first scan signal supplied to the i-th first scan line; a third transistor connected between the second node and the third node, and the third transistor is turned on in response to an enable second scan signal supplied to the i-th second scan line; a first capacitor connected between the first node and the third node; and a light emitting element connected between the second node and the second power line.

[0018] According to an embodiment, a first driving power source may be supplied to the first power source line, and a voltage of a second driving power source lower than a voltage of the first driving power source may be supplied to the second power source line.

[0019] According to an embodiment, the pixel may also include: a fourth transistor connected between the first node and the second node, and the fourth transistor is turned on in response to an enable third scan signal supplied to the i-th third scan line; and a fifth transistor connected between the second node and the light emitting element, and the fifth transistor is turned off in response to a disable emission control signal supplied to the i-th emission control line.

[0020] According to an embodiment, the pixel may also include: a second capacitor connected between the first power line and the first node; a fourth transistor connected between the first node and the second node, and the fourth transistor is turned on in response to an enable third scan signal supplied to the i-th third scan line; and a fifth transistor connected between the second node and the light emitting element, and the fifth transistor is turned off in response to a disable emission control signal supplied to the i-th emission control line.

[0021] According to an embodiment, the horizontal period in which the data signal is supplied to the pixel may include: a first period, a second period, a third period, and a fourth period, and the data driver may supply the voltage of the reference power supply to the j-th data line during the first period to the third period, and supply the voltage of the data signal to the j-th data line during the fourth period. In addition, the scan driver may supply the enable first scan signal to the i-th first scan line during the first period to the fourth period, and the emission driver may supply the disable emission control signal to the i-th emission control line during the first period and the second period.

[0022] According to an embodiment, the voltage of the reference power source may be set to be higher than the voltage of the data signal, and the voltage of the data signal may be set to be equal to or lower than the voltage of the second driving power source.

[0023] According to an embodiment, the emission driver may supply the disable emission control signal to the i-th emission control line during a portion of a previous horizontal period of the horizontal period.

[0024] According to an embodiment, during the fourth period, the emission driver may supply the disable emission control signal to the i-th emission control line.

[0025] According to an embodiment, the scan driver may supply the enable second scan signal to the i-th second scan line during the first cycle, the third cycle, and the fourth cycle, and supply the enable third scan signal to the i-th third scan line during the first cycle and the second cycle.

[0026] According to an embodiment, the scan driver may supply the enabled second scan signal to the i-th second scan line during the first cycle and the third cycle, and supply the enabled third scan signal to the i-th third scan line during the first cycle and the second cycle.

[0027] The objects of the present disclosure are not limited to the above objects, and other technical objects not mentioned will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included in this specification to provide a further understanding of the inventive concept and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the description, explain the principle of the inventive concept.

[0029] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0031] Figure 3 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0032] Figure 4 is shown for driving Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0033] FIG. 5A to FIG. 5G is shown with Figure 4 The driving waveforms in the figure correspond to an embodiment of the operation process of a pixel.

[0034] Figure 6 It is shown Figure 3 Figure 2 shows the simulation results for the pixels shown in Figure 2.

[0035] Figure 7 is shown for driving Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0036] Figure 8 is shown for driving Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0037] Fig. 9 is shown for driving Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0038] Fig.10 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0039] Figures 11 to 14 is a diagram illustrating an electronic device according to various embodiments. DETAILED DESCRIPTION

[0040] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0041] In order to clearly describe the present disclosure, parts not related to the description are omitted, and the same reference numerals are used throughout the specification to represent the same or similar components. Therefore, the above reference numerals may also be used for other drawings.

[0042] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, and therefore the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated in order to clearly express layers and regions.

[0043] In addition, in the description, the expression "same" may mean "substantially the same". That is, the expression "same" may be the same enough to convince a person of ordinary skill in the art. In other expressions, "substantially" may be omitted.

[0044] In the accompanying drawings, some embodiments are described in conjunction with functional blocks, units and / or modules. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, single components, microprocessors, hard-wired circuits, storage elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions described herein, and can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or by a combination of dedicated hardware that performs certain functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from dedicated hardware. In addition, without departing from the scope of the present invention, in some embodiments, blocks, units and / or modules can be physically separated into two or more interacting single blocks, units and / or modules. In addition, without departing from the scope of the present invention, in some embodiments, the blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules.

[0045] The term "connection" between two components may refer to both electrical connection and physical connection, but does not necessarily include both types of connections at each disclosure. For example, "connection" used based on a circuit diagram may specifically refer to electrical connection, while "connection" used based on a cross-sectional view and a plan view may refer to a physical connection, but does not necessarily mean an electrical connection.

[0046] Although ordinal terms such as "first" and "second" are used to describe various components, these components are not limited to any order or sequence. Ordinal terms are used to distinguish one component from another. Therefore, the first component described below can be interchanged with the second component within the technical spirit of the present disclosure.

[0047] The present disclosure is not limited to the embodiments disclosed below, and may be modified and implemented in various forms. In addition, each of the embodiments disclosed below may be implemented alone or in combination with at least one of the other embodiments.

[0048] Figure 1is a diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0049] Reference Figure 1 , also refer to Figure 3 , the display device 100 according to an embodiment of the present disclosure may include a pixel unit 110 (or a display panel), a timing controller 120, a scan driver 130, a data driver 140, an emission driver 150, and a power supply unit 160. The above components may be implemented as separate integrated circuits, and two or more of the above components may be integrated and implemented as one integrated circuit. In addition, the scan driver 130 and the emission driver 150 may be formed in the pixel unit 110.

[0050] The pixel unit 110 may include pixels PX, which are connected to first scan lines SL11, SL12, ... and SL1n, second scan lines SL21, SL22, ... and SL2n, third scan lines SL31, SL32, ... and SL3n, data lines DL1, DL2, ... and DLm, emission control lines EL1, EL2, ... and ELn, and power lines PL1 and PL2, where n and m may be positive integers.

[0051] For example, the pixel PXij located on the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) (see Figure 3 ) can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th emission control line ELi and the j-th data line DLj, where i can be a positive integer less than or equal to n, and j can be a positive integer less than or equal to m. In this document, the i-th first scan line SL1i can also be called the first scan line SL1i, the i-th second scan line SL2i can also be called the second scan line SL2i, the i-th third scan line SL3i can also be called the third scan line SL3i, the i-th emission control line ELi can also be called the emission control line ELi, and the j-th data line DLj can also be called the data line DLj.

[0052] In response to the enabled first scan signal supplied to the first scan lines SL11 to SL1n, the pixels PX may be selected in units of horizontal lines (e.g., the pixels PX connected to the same scan line may be classified as a horizontal line (or pixel row)). The pixels PX selected by enabling the first scan signal may receive a data signal from a data line (any one of DL1 to DLm) connected to the pixels PX. The pixels PX receiving the data signal may generate light having a predetermined brightness in response to the voltage of the data signal.

[0053] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required to drive the scan driver 130. The scan driver 130 may generate an enable first scan signal, an enable second scan signal, and an enable third scan signal while shifting the scan start signal in response to the clock signal.

[0054] For this reason, Figure 2 As shown in FIG. 1 , the scan driver 130 may include a first scan driver 132 , a second scan driver 134 , and a third scan driver 136 .

[0055] Reference Figure 2 , the first scan driver 132 may receive the first scan start signal FLM1 and generate an enable first scan signal by shifting the first scan start signal FLM1 in response to the clock signal. The first scan driver 132 may sequentially supply the enable first scan signal to the first scan lines SL11 to SL1n. When the enable first scan signal is not supplied, the first scan driver 132 may supply the disable first scan signal to the first scan lines SL11 to SL1n.

[0056] The second scan driver 134 may receive the second scan start signal FLM2 and generate an enable second scan signal by shifting the second scan start signal FLM2 in response to the clock signal. The second scan driver 134 may sequentially supply the enable second scan signal to the second scan lines SL21 to SL2n. When the enable second scan signal is not supplied, the second scan driver 134 may supply the disable second scan signal to the second scan lines SL21 to SL2n.

[0057] The third scan driver 136 may receive the third scan start signal FLM3 and generate an enabled third scan signal by shifting the third scan start signal FLM3 in response to the clock signal. The third scan driver 136 may sequentially supply the enabled third scan signal to the third scan lines SL31 to SL3n. When the enabled third scan signal is not supplied, the third scan driver 136 may supply the enabled third scan signal to the third scan lines SL31 to SL3n.

[0058] The first scanning signal, the second scanning signal, and the third scanning signal may be referred to as gate-on voltages at which transistors included in the pixel PX may be turned on. For example, in a P-type transistor, the first scanning signal, the second scanning signal, and the third scanning signal may be low-level voltages.

[0059] The first scan signal, the second scan signal, and the third scan signal may be referred to as gate-off voltages at which transistors included in the pixel PX may be turned off. For example, in a P-type transistor, the first scan signal, the second scan signal, and the third scan signal may be high-level voltages.

[0060] Figure 2 The first scan driver 132, the second scan driver 134, and the third scan driver 136 are shown to be connected to the first scan line SL1i, the second scan line SL2i, and the third scan line SL3i, respectively. However, the embodiments of the present disclosure are not limited thereto. For example, at least two scan lines among the first scan line SL1i, the second scan line SL2i, and the third scan line SL3i may be driven by one scan driver.

[0061] Return to reference Figure 1 , the data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal required to drive the data driver 140. The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. Figure 4 As shown in FIG. 1 , the data driver 140 may sequentially supply a voltage of a reference power source Vref and a voltage Vd of a data signal to the data lines DL1 to DLm during one horizontal period 1H.

[0062] In an embodiment, the reference power source Vref may be set to a voltage higher than (same or higher voltage than) the voltage Vd of the data signal. In an embodiment, the voltage Vd of the data signal may be set to a voltage equal to or lower than the voltage of the second driving power source VSS.

[0063] The emission driver 150 may receive an emission driving signal ECS from the timing controller 120. The emission driving signal ECS may include an emission start signal and a clock signal required to drive the emission driver 150. The emission driver 150 may generate an emission control signal by shifting the emission start signal in response to the clock signal.

[0064] For example, Figure 2 As shown in , the emission driver 150 may receive the emission start signal EFLM and generate a disable emission control signal by shifting the emission start signal EFLM in response to a clock signal. The emission driver 150 may sequentially supply the disable emission control signal to the emission control lines EL1 to ELn. When the disable emission control signal is not supplied, the emission driver 150 may supply the emission control signal to the emission control lines EL1 to ELn.

[0065] The disable emission control signal may be referred to as a gate-off voltage at which a transistor included in the pixel PX may be turned off. For example, in a P-type transistor, the enable emission control signal may be a high-level voltage.

[0066] The emission enable control signal may be referred to as a gate-on voltage at which a transistor included in the pixel PX may be turned on. For example, in a P-type transistor, the emission enable control signal may be a low-level voltage.

[0067] The timing controller 120 may receive input data Din and a control signal CS from the host system through an interface. For example, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS may include various signals including a clock signal.

[0068] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0069] The timing controller 120 may rearrange the input data Din to match the specifications of the display device 100. In addition, the timing controller 120 may correct the input data Din to generate the output data Dout and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din according to an optical measurement result measured during a process.

[0070] The power supply unit 160 may generate various power sources required to drive the display device 100. For example, the power supply unit 160 may generate a first driving power source VDD and a second driving power source VSS.

[0071] The first driving power source VDD may be a power source that supplies a driving current to the pixel PX. The second driving power source VSS may be a power source that receives a driving current from the pixel PX. During a period in which the pixel PX is set to emit light, the voltage of the first driving power source VDD may be set to be higher than the voltage of the second driving power source VSS.

[0072] The first driving power VDD generated in the power supply unit 160 may be supplied to the first power line PL1, and the second driving power VSS generated in the power supply unit 160 may be supplied to the second power line PL2. The first power line PL1 and the second power line PL2 may be commonly connected to the pixel PX, but the embodiments of the present disclosure are not limited thereto.

[0073] In an embodiment, the first power line PL1 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. That is, in an embodiment of the present disclosure, a pixel PX may be connected to any one of the first power lines PL1 and any one of the second power lines PL2.

[0074] Figure 3 is a diagram showing a pixel according to an embodiment of the present disclosure. Figure 3 Pixels located on the i-th horizontal line and the j-th vertical line are shown.

[0075] Reference Figure 3 , the pixel PXij according to the embodiment of the present disclosure can be connected to the corresponding signal lines SL1i, SL2i, SL3i, ELi and DLj. For example, the pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th emission control line ELi and the j-th data line DLj. In an embodiment, the pixel PXij can also be connected to the first power line PL1 and the second power line PL2.

[0076] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0077] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2.

[0078] For example, the first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 through the fifth transistor M5, the second node N2, and the first transistor M1, and the second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light having a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0079] The light emitting element LD may be an organic light emitting diode. In addition, the light emitting element LD may be an inorganic light emitting diode, such as a micro light emitting diode (LED) or a quantum dot light emitting diode. In addition, the light emitting element LD may be an element composed of a combination of an organic material and an inorganic material. Figure 3 In the embodiment, the pixel PXij includes a single light emitting element LD. However, in another embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series and parallel.

[0080] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, and a second capacitor C2.

[0081] In an embodiment, the first to fifth transistors M1 to M5 may be composed of P-type transistors. However, this is just an example, and at least one of the first to fifth transistors M1 to M5 may be replaced with an N-type transistor.

[0082] A first electrode of the first transistor M1 (or driving transistor) may be electrically connected to a first power line PL1, and a second electrode of the first transistor M1 may be connected to a second node N2. Here, "connection" refers to electrical connection. A gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD in response to a voltage of the first node N1.

[0083] The second transistor M2 may be connected between the data line DLj and the third node N3. In addition, the gate electrode of the second transistor M2 may be electrically connected to the first scan line SL1i. The second transistor M2 may be turned on in response to the enable first scan signal GW supplied to the first scan line SL1i to electrically connect the data line DLj and the third node N3.

[0084] The third transistor M3 may be connected between the second node N2 and the third node N3. In addition, the gate electrode of the third transistor M3 may be electrically connected to the second scan line SL2i. The third transistor M3 may be turned on in response to the enable second scan signal GR supplied to the second scan line SL2i to electrically connect the second node N2 and the third node N3.

[0085] The fourth transistor M4 may be connected between the first node N1 and the second node N2. In addition, the gate electrode of the fourth transistor M4 may be electrically connected to the third scan line SL3i. The fourth transistor M4 may be turned on in response to the enable third scan signal GC supplied to the third scan line SL3i to electrically connect the first node N1 and the second node N2. In this case, the gate electrode (i.e., the first node N1) and the second electrode (i.e., the second node N2) of the first transistor M1 may be electrically connected to each other, and thus the first transistor M1 may be connected in the form of a diode.

[0086] The fifth transistor M5 may be connected between the second node N2 and the first electrode of the light emitting element LD. In addition, the gate electrode of the fifth transistor M5 may be electrically connected to the emission control line ELi. The fifth transistor M5 may be turned off in response to the disable emission control signal EM supplied to the emission control line ELi, thereby blocking the electrical connection between the second node N2 and the light emitting element LD.

[0087] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may change the voltage of the first node N1 in response to a voltage change of the third node N3. That is, the first capacitor C1 may be driven as a coupling capacitor.

[0088] The second capacitor C2 may be connected between the first power line PL1 and the first node N1. The second capacitor C2 may store a voltage of the first node N1.

[0089] As described above, the pixel PXij according to an embodiment of the present disclosure may include five transistors M1 to M5 and two capacitors C1 and C2. In addition, the pixel PXij according to an embodiment of the present disclosure may be connected to two power lines PL1 and PL2. Generally, a conventional pixel is connected to three or more power lines and six or more transistors. Therefore, the pixel PXij according to an embodiment of the present disclosure may be applied to a high-resolution display panel because the power lines and transistors occupy minimal space.

[0090] Figure 4 is shown for driving Figure 3 0047] A waveform diagram of an embodiment of a method for a pixel is shown in FIG.

[0091] Reference Figure 4 , also refer to Figure 1 , Figure 2 and Figure 3, a horizontal period 1H (or a specific horizontal period) in which a data signal is supplied to a pixel PXij located on the i-th horizontal line and the j-th vertical line may include a first period T1, a second period T2, a third period T3, and a fourth period T4. In addition, at least a portion of a previous horizontal period in which a data signal is supplied to the i-1-th horizontal line may be referred to as a previous period PT. The previous period PT may include a previous first period PT1 and a previous second period PT2 immediately before the horizontal period 1H.

[0092] The data driver 140 may supply the voltage of the reference power supply Vref to the data line DLj during the first period T1 to the third period T3, and supply the voltage Vd of the data signal to the data line DLj during the fourth period T4. The reference power supply Vref may be set to a voltage higher than the voltage Vd of the data signal. The reference power supply Vref may be set to a voltage lower than the voltage of the first driving power supply VDD. The voltage Vd of the data signal may be set to a voltage equal to or lower than the voltage of the second driving power supply VSS.

[0093] The scan driver 130 (or the first scan driver 132) may supply the enabled first scan signal GW to the first scan line SL1i during the first period T1 to the fourth period T4. The scan driver 130 (or the second scan driver 134) may supply the enabled second scan signal GR to the second scan line SL2i during the previous second period PT2, the first period T1, the third period T3, and the fourth period T4. The scan driver 130 (or the third scan driver 136) may supply the enabled third scan signal GC to the third scan line SL3i during the previous period PT, the first period T1, and the second period T2.

[0094] The emission driver 150 may supply the disable emission control signal EM to the emission control line ELi during the previous period PT, the first period T1, and the second period T2. Here, the disable emission control signal EM may be set to a width wider than a width of the enabled third scan signal GC (or a length longer than a length of the enabled third scan signal GC, a time longer than a time of the enabled third scan signal GC, etc.) to include the following: Figure 4 The unmarked period between the second period T2 and the third period T3 is shown in FIG.

[0095] The previous period PT may be a period in which the pixel PXij does not emit light. The first period T1 may be a period in which the first node N1 is initialized. The second period T2 may be a period in which the threshold voltage of the first transistor M1 is compensated. The third period T3 may be a period in which the first electrode of the light emitting element LD is initialized. The fourth period T4 may be a period in which the voltage Vd of the data signal is supplied to the pixel PXij. The fifth period T5 after the fourth period T4 may be a period in which the pixel PXij emits light in response to the voltage Vd of the data signal.

[0096] FIG. 5A to FIG. 5G is shown with Figure 4 The driving waveforms in the figure correspond to an embodiment of the operation process of a pixel.

[0097] Reference Figure 5A , during the previous first period PT1, the enable third scan signal GC may be supplied to the third scan line SL3i, and the disable emission control signal EM may be supplied to the emission control line ELi.

[0098] In response to the enable third scan signal GC supplied to the third scan line SL3i, the fourth transistor M4 may be turned on. In response to the disable emission control signal EM supplied to the emission control line ELi, the fifth transistor M5 may be turned off. When the fifth transistor M5 is turned off, the electrical connection between the second node N2 and the light emitting element LD may be blocked. In the previous first period PT1, the pixel PXij does not emit light.

[0099] Reference Figure 5B , during the previous second period PT2, the supply of the enable third scan signal GC and the disable emission control signal EM supplied during the previous first period PT1 may be maintained. In addition, during the previous second period PT2, the enable second scan signal GR may be supplied to the second scan line SL2i. In response to the enable second scan signal GR supplied to the second scan line SL2i, the third transistor M3 may be turned on. In response to the turning on of the third transistor M3, the second node N2 and the third node N3 may be electrically connected to each other. During the previous second period PT2, the pixel PXij may maintain a non-luminous state.

[0100] Reference Figure 5C , during the first period T1, the supply of the enabled second scan signal GR, the enabled third scan signal GC, and the disabled emission control signal EM supplied during the previous second period PT2 may be maintained.

[0101] During the first period T1, the enable first scan signal GW may be supplied to the first scan line SL1i. In response to the enable first scan signal GR supplied to the first scan line SL1i, the second transistor M2 may be turned on. In response to the turning on of the second transistor M2, the voltage of the reference power supply Vref from the data line DLj may be supplied to the first node N1 via the third node N3 and the second node N2.

[0102] During the first period T1, the first node N1, the second node N2, and the third node N3 may be initialized to the voltage of the reference power supply Vref. During the first period T1, the first capacitor C1 may be initialized because the same voltage (i.e., the voltage of the reference power supply Vref) is applied to both ends of the first capacitor C1. Similarly, during the first period T1, the second capacitor C2 may be initialized by the voltage of the reference power supply Vref supplied to the first node N1. During the first period T1, the pixel PXij may remain in a non-luminous state.

[0103] Reference Figure 5D During the second period T2, the supply of the enabled first scan signal GW, the enabled third scan signal GC, and the disabled emission control signal EM supplied during the first period T1 may be maintained.

[0104] Unlike the first period T1, during the second period T2, the disable second scan signal GR may be supplied to the second scan line SL2i. In response to the disable second scan signal GR supplied to the second scan line SL2i, the third transistor M3 may be turned off. In response to the turning off of the third transistor M3, the electrical connection between the second node N2 and the third node N3 may be blocked.

[0105] Since the first node N1 is initialized to the voltage of the reference power source Vref lower than the voltage of the first driving power source VDD during the first period T1, the voltage of the first driving power source VDD may be supplied to the first node N1 via the first transistor M1 connected in the form of a diode during the second period T2. In this case, a voltage obtained by subtracting the absolute value of the threshold voltage of the first transistor M1 from the first driving power source VDD may be applied to the first node N1.

[0106] Then, during the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in each of the first capacitor C1 and the second capacitor C2. For example, a voltage corresponding to the difference between a voltage obtained by subtracting the absolute value of the threshold voltage of the first transistor M1 from the voltage of the first driving power supply VDD and a voltage of the reference power supply Vref may be stored in the first capacitor C1. For example, the threshold voltage of the first transistor M1 may be stored in the second capacitor C2. During the second period T2, the pixel PXij may remain in a non-luminous state.

[0107] Reference Figure 5E , during the third period T3, the supply of the enable first scan signal GW supplied during the second period T2 may be maintained.

[0108] During the third period T3, the enabled second scan signal GR may be supplied to the second scan line SL2i, the disabled third scan signal GC may be supplied to the third scan line SL3i, and the enabled emission control signal EM may be supplied to the emission control line ELi.

[0109] The fourth transistor M4 may be turned off in response to the deactivation third scan signal GC supplied to the third scan line SL3i. Since the fourth transistor M4 is turned off, an electrical connection between the first node N1 and the second node N2 may be blocked.

[0110] In response to the enable emission control signal EM supplied to the emission control line ELi, the fifth transistor M5 may be turned on. When the fifth transistor M5 is turned on, the light emitting element LD and the second node N2 may be electrically connected to each other. In response to the enable second scan signal GR supplied to the second scan line SL2i, the third transistor M3 may be turned on. When the second transistor M3 is turned on, the second node N2 and the third node N3 may be electrically connected to each other.

[0111] Therefore, the voltage of the reference power supply Vref supplied from the data line DLj can be supplied to the first electrode of the light emitting element LD via the third node N3, the third transistor M3, the second node N2 and the fifth transistor M5. In response to the voltage of the reference power supply Vref supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD can be discharged. Since the current voltage charged in the parasitic capacitance of the light emitting element LD is discharged (or removed), unexpected low light emission can be prevented. Therefore, the ability of the pixel PXij to express black can be improved.

[0112] In addition, the reference power source Vref may be set to a voltage that maintains a state where the light emitting element LD does not emit light. Therefore, during the third period T3, the pixel PXij may maintain a state where the light emitting element LD does not emit light.

[0113] Reference Fig. 5F During the fourth period T4, the supply of the enabled first scan signal GW and the enabled second scan signal GR supplied during the third period T3 may be maintained. In addition, during the fourth period T4, the voltage Vd of the data signal may be supplied to the data line DLj.

[0114] The voltage Vd of the data signal supplied to the data line DLj may be supplied to the third node N3, the second node N2, and the first electrode of the light emitting element LD. In response to the supply of the voltage Vd of the data signal, the voltage of the third node N3 may be changed (or reduced) from the voltage of the reference power supply Vref to the voltage Vd of the data signal. In this case, the voltage of the first node N1 may also be changed by coupling to the first capacitor C1.

[0115] Here, the amount of change in the voltage at the first node N1 may be determined according to the ratio of the first capacitor C1 to the second capacitor C2. For example, the voltage of the first node N1 may be changed from a voltage obtained by subtracting the absolute value of the threshold voltage of the first transistor M1 from the voltage of the first driving power supply VDD by a value obtained by multiplying the amount of change in the voltage at the third node N3 by C1 / (C1+C2). When the amount of change in the voltage at the first node N1 is controlled by the ratio of the first capacitor C1 to the second capacitor C2, the voltage range of the data signal may be set to be sufficiently wide.

[0116] For example, when the data signal is directly supplied to the gate electrode of the first transistor M1, the voltage range of the data signal can be set relatively narrow. When the data signal has a narrow voltage range, various gray levels (e.g., 256 gray levels) are implemented using the narrow voltage range. Therefore, it may be difficult to express an accurate gray level.

[0117] On the other hand, when the voltage supplied to the gate electrode of the first transistor M1 is controlled by the ratio of the first capacitor C1 and the second capacitor C2 as in the embodiment of the present invention, the voltage range of the data signal can be set sufficiently wide. For example, a voltage corresponding to a voltage obtained by multiplying the voltage of the data signal by C1 / (C1+C2) can be transmitted to the gate electrode of the first transistor M1, and thus the voltage range of the data signal can be set wide. When the data signal has a wide voltage range, grayscale can be easily realized.

[0118] During the fourth period T4, the first capacitor C1 and the second capacitor C2 may store the voltage of the first node N1. Here, the voltage of the first node N1 may be determined by the threshold voltage of the first transistor M1 and the voltage Vd of the data signal. Therefore, during the fourth period T4, a voltage corresponding to the voltage Vd of the data signal and the threshold voltage of the first transistor M1 may be stored in the first capacitor C1 and the second capacitor C2.

[0119] In addition, during the fourth period T4, the voltage Vd of the data signal can be supplied to the first electrode of the light emitting element LD. Here, the voltage Vd of the data signal can be set to a voltage lower than the voltage of the second driving power supply VSS, and the light emitting element LD can be turned off accordingly. Therefore, during the fourth period T4, the voltage Vd of the data signal can be stably supplied to the third node N3.

[0120] Reference Figure 5G During the fifth period T5, the disable scan signals GW, GR, and GC may be supplied to the scan lines SL1i, SL2i, and SL3i, respectively. Then, during the fifth period T5, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be turned off.

[0121] During the fifth period T5, the emission control signal EM may be supplied to the emission control line ELi. In response to the emission control signal EM supplied to the emission control line ELi, the fifth transistor M5 may be turned on. As the fifth transistor M5 is turned on, the light emitting element LD may be electrically connected to the first transistor M1. Then, the current supplied from the first transistor M1 may be supplied to the light emitting element LD in response to the voltage of the first node N1, and the light emitting element LD may emit light of brightness corresponding to the amount of the current supplied from the first transistor M1.

[0122] Figure 6 It is shown Figure 3 Figure 2 shows the simulation results for the pixel shown in . Figure 6 In the example, the x-axis may represent time and the y-axis may represent voltage [V].

[0123] Reference Figure 6 , if the voltage Vd of the supplied data signal is -2V, -3V, -4V, -5V, -6V, and -7V, the voltage VN1 of the first node N1 may vary in response to the voltage Vd of the data signal. That is, in an embodiment of the present disclosure, the voltage VN1 of the first node N1 may vary in response to the change in the voltage Vd of the data signal, and thus, light of brightness corresponding to the voltage Vd of the data signal may be generated in the pixel PXij.

[0124] Table 1 below shows a calculated voltage of the first node N1 (calculated VG) and a simulated voltage of the first node N1 (simulated VG( VN1 )).

[0125] Table 1

[0126] Vd Calculated VG Analog VG (VN1) -2V 3.3 3.81 -3V 2.8 3.31 -4V 2.3 2.81 -5V 1.8 1.81 -6V 1.3 1.31 -7V 0.8 0.82

[0127] In Table 1, it is assumed that the threshold voltage (Vth) of the first transistor M1 is -1.7V, the gate-on voltage supplied to the scan lines SL1, SL2 and SL3 and the emission control line EL is -10V, and the gate-off voltage is 10V. In addition, it is assumed that the first capacitor C1 and the second capacitor C2 have the same capacitance. In addition, it is assumed that the resistance of the first transistor M1 is 8 times the resistance of each of the second transistor M2, the third transistor M3 and the fourth transistor M4. Referring to Table 1, the voltage of the first node N1 calculated in response to the voltage Vd of the data signal (i.e., the calculated VG) may have a voltage difference of about 0.01V with the voltage VN1 of the first node N1 obtained by simulation (i.e., the simulated VG). That is, the pixel PX according to the embodiment of the present disclosure can be driven according to its design purpose.

[0128] Figure 7 is shown for driving Figure 3 The waveform diagram of an embodiment of the pixel method shown in FIG. Figure 7 When Figure 4 to Figure 5G Description of the repeated section.

[0129] Reference Figure 7 , also refer to Figure 3 During the fourth period T4, the disable emission control signal EM may be supplied to the emission control line ELi. In response to the disable emission control signal EM supplied to the emission control line ELi, the fifth transistor M5 may be turned off during the fourth period T4. Then, during the fourth period T4, the voltage Vd of the data signal from the data line DLj may not be supplied to the light emitting element LD.

[0130] Figure 8 is shown for driving Figure 3 The waveform diagram of an embodiment of the pixel method shown in FIG. Figure 8 When Figure 4 to Figure 5G Description of the repeated section.

[0131] Reference Figure 8 , also refer to Figure 3 , the enabled second scan signal GR supplied to the second scan line SL2i may be supplied during the first period T1 and the third period T3. Figure 8 The driving waveform can be different from Figure 4 The driving waveform of FIG. 2 is because the third transistor M3 is set to the off state during the previous second period PT2a and the fourth period T4a.

[0132] When the third transistor M3 is turned off during the previous second period PT2a, the second node N2 and the third node N3 may be disconnected. The previous second period PT2a may be a period in which the pixel PXij does not emit light, and even if the third transistor M3 is turned off, it may not affect the driving of the pixel PXij.

[0133] When the third transistor M3 is turned off during the fourth period T4a, the second node N2 and the third node N3 may be disconnected by the resistor. The fourth period T4a may be a period in which the voltage Vd of the data signal is transmitted to the first node N1. Even if the third transistor M3 is turned off during the fourth period T4a, the voltage of the first node N1 may change the voltage Vd of the data signal supplied to the third node N3. Therefore, the voltage Vd of the data signal may be transmitted to the first node N1.

[0134] In addition, when the third transistor M3 is turned off, the voltage Vd of the data signal may not be supplied to the first electrode of the light emitting element LD. Therefore, the light emitting element LD may maintain the voltage of the reference power source Vref supplied during the third period T3.

[0135] Fig. 9 is shown for driving Figure 3 The waveform diagram of an embodiment of the pixel method shown in FIG. Fig. 9 When Figure 4 to Figure 5G Description of the repeated section.

[0136] Reference Fig. 9 , the enabling third scan signal GC supplied to the third scan line SL3i may be supplied during the first period T1 and the second period T2. Figure 4 Unlike the driving waveform of FIG. 1 , the disabled third scan signal GC may be supplied to the third scan line SL3i during the previous period PTb (ie, the previous first period PT1b and the previous second period PT2b).

[0137] In response to the disable third scan signal GC supplied to the third scan line SL3i, the fourth transistor M4 may be turned off during the previous period PTb. The previous period PTb may be a period in which the pixel PXij does not emit light, and even if the fourth transistor M4 is turned off, it may not affect the driving of the pixel PXij.

[0138] Fig.10 is a diagram showing a pixel according to an embodiment of the present disclosure. Fig.10 , which is located on the i-th horizontal line and the j-th vertical line. Fig.10 When Figure 3 Description of the repeated section.

[0139] Reference Fig.10, the pixel PXija according to an embodiment of the present disclosure may be connected to corresponding signal lines SL1i, SL2i, SL3i, ELi, and DLj.

[0140] The pixel PXija according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0141] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 and may generate light having a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0142] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a first capacitor C1.

[0143] Will Fig.10 The pixels PXija shown in Figure 3 Compared with the pixel PXij shown in Fig.10 The second capacitor C2 is omitted in the pixel PXija shown in FIG. In this case, the voltage variation at the third node N3 may not be transmitted to the first node N1 according to the ratio of the first capacitor C1 to the second capacitor C2, but may be directly transmitted by the first capacitor C1. Other driving processes may be similar to Figure 3 The driving process is the same as in , and the detailed description in this regard will be omitted.

[0144] Figures 11 to 14 is a diagram illustrating an electronic device according to various embodiments.

[0145] Reference Fig.11 , also refer to Figure 1 , the display device 100 according to the above embodiment may be applied to smart glasses. The smart glasses may include a frame 111 and a lens unit 112. The smart glasses may be a wearable electronic device that can be worn on the face of a user, and may have a structure in which a portion of the frame 111 is folded or unfolded. For example, the smart glasses may be a wearable device for augmented reality (AR).

[0146] The frame 111 may include a housing 111b supporting the lens unit 112 and a leg member 111a for being worn by a user. The leg member 111a may be connected to the housing 111b by a hinge and may be folded or unfolded.

[0147] A battery, a touch panel, a microphone, a camera, and the like may be built in the frame 111. In addition, a projector that outputs light, a processor that controls an optical signal, and the like may be built in the frame 111.

[0148] The lens unit 112 may be an optical member that transmits or reflects light. The lens unit 112 may include glass, a transparent synthetic resin, or the like.

[0149] The display device 100 according to the above-described embodiment may be applied to the lens unit 112. For example, the user may visually recognize an image displayed by an optical signal transmitted by the projector of the frame 111 through the lens unit 112. For example, the user may visually recognize information such as time and date displayed on the lens unit 112.

[0150] Reference Fig.12 , also refer to Figure 1 The display device 100 according to the above embodiment may be applied to a head mounted display (HMD). The head mounted display may include a head mounted strap 121 and a display storage box 122. For example, the head mounted display may be a wearable electronic device that can be worn on the user's head.

[0151] The head-mounted strap 121 may be connected to the display storage box 122 and fix the display storage box 122. The head-mounted strap 121 may include a horizontal strap and a vertical strap to fix the head-mounted display to the user's head. The horizontal strap may be arranged to surround the side of the user's head, and the vertical strap may be arranged to surround the top of the user's head. However, the present disclosure is not necessarily limited thereto, and the head-mounted strap 121 may be implemented in the form of a glasses frame or a helmet.

[0152] The display storage box 122 can accommodate the display device 100 and can include at least one lens. At least one lens can provide an image to a user. For example, the display device 100 according to the above embodiment can be applied to a left eye lens and a right eye lens implemented in the display storage box 122.

[0153] Reference Fig.13 , also refer to Figure 1 , the display device 100 according to the above embodiment may be applied to a smart watch. The smart watch may include a display unit 131 and a strap unit 133. The smart watch may be a wearable electronic device, and the strap unit 133 may be mounted on a user's wrist. The display device 100 according to the above embodiment may be applied to the display unit 131. For example, the display unit 131 may provide image data including information such as time and date.

[0154] Reference Fig.14 , also refer to Figure 1 The display device 100 according to the above-described embodiment may be applied to a car display. As an example, the car display may refer to an electronic device provided inside and outside a vehicle to provide image data.

[0155] For example, the display device 100 according to the above embodiment can be applied to at least one of the infotainment panel 141, cluster 142, co-driver display 143, head-up display 144, side mirror display 145 and rear seat display 146 provided in the vehicle.

[0156] The pixel according to the embodiment of the present disclosure may be applied to a high-resolution display panel because the pixel may compensate for the threshold voltage of the driving transistor using five transistors and two (or one) capacitors.

[0157] In the pixel according to the embodiment of the present disclosure, a data signal may be transmitted using capacitor coupling, and thus a voltage range of the data signal may be set wide.

[0158] However, the effects of the present disclosure are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the present disclosure.

[0159] As described above, the preferred embodiments of the present disclosure have been described with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A pixel, wherein The pixels include: a first transistor having a gate electrode connected to the first node, a first electrode connected to the first power line, and a second electrode connected to the second node; a second transistor connected between the data line and the third node, and having a gate electrode electrically connected to the first scan line; a third transistor connected between the second node and the third node, and having a gate electrode electrically connected to a second scan line; a first capacitor connected between the first node and the third node; and The light emitting element is connected between the second node and the second power line.

2. The pixel according to claim 1, wherein: The pixel also includes: a fourth transistor connected between the first node and the second node, and having a gate electrode electrically connected to a third scan line; and A fifth transistor is connected between the second node and the light emitting element, and has a gate electrode electrically connected to an emission control line.

3. The pixel according to claim 1, wherein: The pixel also includes: The second capacitor is connected between the first power line and the first node.

4. The pixel according to claim 3, wherein: The pixel also includes: a fourth transistor connected between the first node and the second node, and having a gate electrode electrically connected to a third scan line; and A fifth transistor is connected between the second node and the light emitting element, and has a gate electrode electrically connected to an emission control line.

5. The pixel according to claim 4, wherein: A horizontal period during which a data signal is supplied to the pixel includes a first period, a second period, a third period, and a fourth period. wherein the voltage of the reference power supply is supplied to the data line during the first period, the second period and the third period, and the voltage of the data signal is supplied to the data line during the fourth period, The second transistor is turned on during the first period to the fourth period, and The fifth transistor is turned off during the first period and the second period.

6. The pixel according to claim 5, wherein: The fifth transistor is turned off during a portion of a previous period immediately before the horizontal period.

7. The pixel according to claim 5, wherein: The fifth transistor is turned off during the fourth period.

8. The pixel according to claim 5, wherein: The third transistor is turned on during the first period, the third period, and the fourth period, and The fourth transistor is turned on during the first period and the second period.

9. The pixel according to claim 8, wherein: The fourth transistor is turned on during a portion of a previous period immediately before the horizontal period.

10. The pixel according to claim 5, wherein: The third transistor is turned on during the first period and the third period, and The fourth transistor is turned on during the first period and the second period.

Images