Pixel

Abstract

A pixel according to an embodiment of the inventive concept includes: a first transistor having a first electrode electrically connected to a first power supply line, a second electrode, and a gate electrode connected to a first node; a light emitting element connected between the second electrode of the first transistor and a second power supply line; a second transistor connected between the first node and the data line, and having a gate electrode electrically connected to the first scan line; a third transistor connected between the first electrode of the first transistor and the second node, and having a gate electrode electrically connected to the first emission control line; a fourth transistor connected between the first power supply line and the second node, and having a gate electrode electrically connected to the second emission control line; and a first capacitor connected between the first node and the second node and sequentially supplying a voltage of the reference power supply and a voltage of the data signal to the data line during the horizontal period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0105700, filed on August 11, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] The inventive concept relates to a pixel and a display device including the pixel. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information is becoming increasingly prominent. In response to this, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0005] Recently, high-resolution display panels are required for various display devices including a head-mounted display device (HMD). Summary of the invention

[0006] An object of the inventive concept is to provide a pixel applicable to a high-resolution display panel and a display device including the same.

[0007] A pixel according to an embodiment conceived in the present invention includes: a first transistor having a first electrode electrically connected to a first power line, a second electrode and a gate electrode connected to a first node; a light emitting element connected between the second electrode of the first transistor and the second power line; a second transistor connected between the first node and a data line, and the second transistor has a gate electrode electrically connected to a first scan line; a third transistor connected between the first electrode and the second node of the first transistor, and the third transistor has a gate electrode electrically connected to a first emission control line; a fourth transistor connected between the first power line and the second node, and the fourth transistor has a gate electrode electrically connected to a second emission control line; and a first capacitor connected between the first node and the second node, and during a horizontal period, a voltage of a reference power supply and a voltage of a data signal can be sequentially supplied to the data line.

[0008] According to an embodiment, the pixel may further include a fifth transistor connected between the first electrode of the light emitting element and the second power supply line, and the fifth transistor has a gate electrode electrically connected to the second scan line.

[0009] According to an embodiment, the pixel may further include a second capacitor connected between the second node and the second scan line.

[0010] According to an embodiment, the pixel may further include a third capacitor connected between the second node and the first power line.

[0011] According to an embodiment, the horizontal period may include a first period, a second period, a third period, a fourth period and a fifth period, the fifth transistor may be turned on during the first period to the third period, the second transistor may be turned on during the first period to the fourth period, the fourth transistor may be turned off during the second period to the fourth period, and the third transistor may be turned off during the third period to the fifth period.

[0012] According to an embodiment, the voltage of the reference power source may be supplied to the data line during the first period and the second period, and the voltage of the data signal may be supplied to the data line during the third period and the fourth period.

[0013] According to an embodiment, the horizontal period may include a first period, a second period, a third period, a fourth period and a fifth period, the fifth transistor may be turned on during the first period to the third period, the second transistor may be turned on during the first period to the fourth period, the fourth transistor may be turned off during the first period to the fourth period, and the third transistor may be turned off during the third period to the fifth period.

[0014] According to an embodiment, the voltage of the reference power source may be supplied to the data line during the first period and the second period, and the voltage of the data signal may be supplied to the data line during the third period and the fourth period.

[0015] According to an embodiment, the pixel may further include a second capacitor connected between the second node and the first emission control line.

[0016] According to an embodiment, a voltage of a first driving power supply may be supplied to the first power line, a voltage of a second driving power supply lower than the voltage of the first driving power supply may be supplied to the second power line, and the reference power supply may have a voltage lower than the voltage of the first driving power supply.

[0017] According to an embodiment, the pixel may further include: a fifth transistor connected between the first electrode of the light emitting element and the third power supply line, and the fifth transistor has a gate electrode electrically connected to the second scan line; and a second capacitor connected between the second node and the second scan line.

[0018] According to an embodiment, a voltage of an initialization power source may be supplied to the third power source line, and when the voltage of the initialization power source is supplied to the first electrode of the light emitting element, the light emitting element may be turned off.

[0019] A display device according to an embodiment of the present invention may include: a pixel connected to a first scan line, a second scan line, a first emission control line, a second emission control line and a data line; a scan driver driving the first scan line and the second scan line; an emission driver driving the first emission control line and the second emission control line; and a data driver driving the data line. A pixel located on an i-th horizontal line (i is a natural number greater than 0) and a j-th vertical line (j is a natural number greater than 0) may include: a first transistor having a first electrode electrically connected to a first power line, a second electrode and a gate electrode connected to a first node; a light emitting element connected between the second electrode and the second power line of the first transistor; a second transistor connected between the first node and the j-th data line and turned on when an activated first scan signal is supplied to the i-th first scan line; a third transistor connected between the first electrode and the second node of the first transistor and turned off when a disabled first emission control signal is supplied to the i-th first emission control line; a fourth transistor connected between the first power line and the second node and turned off when a disabled second emission control signal is supplied to the i-th second emission control line; and a first capacitor connected between the first node and the second node. The horizontal period for driving the pixel may include a first period, a second period, a third period, a fourth period and a fifth period, and the data driver may supply a voltage of a reference power supply to the jth data line during the first period and the second period, and supply a voltage of a data signal to the jth data line during the third period and the fourth period.

[0020] According to an embodiment, the pixel may further include a fifth transistor connected between the first electrode of the light emitting element and the second power line and turned on when the activated second scan signal is supplied to the i-th second scan line.

[0021] According to an embodiment, the scan driver may supply the activated first scan signal to the i-th first scan line during the first cycle to the fourth cycle, and supply the activated second scan signal to the i-th second scan line during the first cycle to the third cycle, and the emission driver may supply the disabled first emission control signal to the i-th first emission control line during the third cycle to the fifth cycle, and supply the disabled second emission control signal to the i-th second emission control line during the second cycle to the fourth cycle.

[0022] According to an embodiment, the scan driver may supply the activated first scan signal to the i-th first scan line during the first cycle to the fourth cycle, and supply the activated second scan signal to the i-th second scan line during the first cycle to the third cycle, and the emission driver may supply the disabled first emission control signal to the i-th first emission control line during the third cycle to the fifth cycle, and supply the disabled second emission control signal to the i-th second emission control line during the first cycle to the fourth cycle.

[0023] According to an embodiment, the display device may further include a second capacitor connected between the second node and the i-th second scan line.

[0024] According to an embodiment, the display device may further include a third capacitor connected between the second node and the first power line.

[0025] According to an embodiment, the display device may further include a second capacitor connected between the second node and the i-th first emission control line.

[0026] According to an embodiment, the display device may further include: a fifth transistor connected between the first electrode of the light emitting element and the third power line and turned on when the activated second scan signal is supplied to the i-th second scan line; and a second capacitor connected between the second node and the i-th second scan line.

[0027] The objects of the inventive concept are not limited to the above objects, and other technical objects not mentioned will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and together with the description, serve to explain the principles of the inventive concept.

[0029] Figure 1 is a diagram illustrating a display device according to an embodiment of the inventive concept.

[0030] Figure 2 It is shown Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0031] Figure 3 is a diagram illustrating a pixel according to an embodiment of the inventive concept.

[0032] Figure 4 is shown for driving Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0033] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Fig. 5F is shown with Figure 4 A driving waveform corresponds to an embodiment of an operation process of a pixel.

[0034] Figure 6 It is shown Figure 3 Figure 2 shows the simulation results for the pixel shown in FIG.

[0035] Figure 7 is shown for driving Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0036] Figure 8 is a diagram illustrating a pixel according to an embodiment of the inventive concept.

[0037] Fig. 9 is a diagram illustrating a pixel according to an embodiment of the inventive concept.

[0038] Fig.10 is a diagram illustrating a pixel according to an embodiment of the inventive concept.

[0039] Fig.11 , Fig.12 , Fig.13 and Fig.14 is a diagram illustrating an electronic device according to various embodiments. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the inventive concept. The inventive concept can be implemented in various forms and is not limited to the embodiments described herein.

[0041] In order to clearly describe the inventive concept, parts irrelevant to the specification may be omitted, and the same or similar components may be represented by the same or similar reference numerals throughout the specification. Therefore, the above reference numerals may also be used in other drawings.

[0042] In addition, for convenience of explanation, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore the inventive concept is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated to clearly represent layers and regions.

[0043] Furthermore, in the specification, the expression "same" may mean "substantially the same". That is, it may be sufficiently identical to convince a person of ordinary skill in the art that it is the same. In other expressions, "substantially" may be omitted.

[0044] Some embodiments related to functional blocks, units and / or modules are described in the accompanying drawings. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs certain functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from dedicated hardware. In addition, in some embodiments, without departing from the scope of the inventive concept, blocks, units and / or modules can be physically divided into two or more interacting separate blocks, units and / or modules. In addition, in some embodiments, without departing from the scope of the inventive concept, blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules.

[0045] The term "connection" between two components may mean that both electrical connection and physical connection are used inclusively, but the inventive concept is not limited thereto. For example, "connection" used based on a circuit diagram may represent an electrical connection, and "connection" used based on a cross-sectional view and a plan view may represent a physical connection.

[0046] Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical spirit of the present invention, the first component described below may be the second component.

[0047] Meanwhile, the inventive concept is not limited to the embodiments disclosed below, and can be modified and implemented in various forms. In addition, each of the embodiments disclosed below can be implemented alone or in combination with at least one of the other embodiments.

[0048] Figure 1 is a diagram illustrating a display device according to an embodiment of the inventive concept. Figure 2 It is shown Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0049] Reference Figure 1, the display device 100 according to an embodiment of the inventive concept may include a pixel unit 110 (or a display panel), a timing controller 120, a scan driver 130, a data driver 140, an emission driver 150, and a power supply unit 160. The above components may be implemented as separate integrated circuits, and two or more of the above components may be integrated and implemented as one integrated circuit. In addition, the scan driver 130 and the emission driver 150 may be formed in the pixel unit 110.

[0050] The pixel unit 110 may include pixels PX connected to first scan lines SL11, SL12, ... and SL1n, second scan lines SL21, SL22, ... and SL2n, first emission control lines EL11, EL12, ... and EL1n, second emission control lines EL21, EL22, ... and EL2n, data lines DL1, DL2, ... and DLm, and power lines PL1 and PL2, where n and m can each be a natural number greater than 0.

[0051] As an example, a pixel PXij located on the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) (see Figure 3 ) can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th first emission control line EL1i, the i-th second emission control line EL2i and the j-th data line DLj, where i can be a natural number greater than 0 and less than or equal to n, and j can be a natural number greater than 0 and less than or equal to m. Herein, the i-th first scan line SL1i can also be referred to as the first scan line SL1i, the i-th second scan line SL2i can also be referred to as the second scan line SL2i, the i-th first emission control line EL1i can also be referred to as the first emission control line EL1i, the i-th second emission control line EL2i can also be referred to as the second emission control line EL2i, and the j-th data line DLj can also be referred to as the data line DLj.

[0052] When an activated first scan signal is supplied to one first scan line among the first scan lines SL11 to SL1n, a pixel PX connected to the one first scan line (e.g., one horizontal line or one pixel row) may be selected. The pixel PX selected by the one first scan signal may receive a data signal from the data lines (DL1 to DLm) connected to the pixel PX, respectively. The pixel PX receiving the data signal may generate light having a predetermined brightness in response to a voltage of the data signal.

[0053] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required for driving the scan driver 130. The scan driver 130 may generate an activated first scan signal and an activated second scan signal by shifting the scan start signal in response to the clock signal.

[0054] For this reason, Figure 2 As shown in FIG. 1 , the scan driver 130 may include a first scan driver 132 and a second scan driver 134 .

[0055] The first scan driver 132 may receive the first scan start signal FLM1 and generate a first scan signal by shifting the first scan start signal FLM1 in response to the clock signal. The first scan driver 132 may sequentially supply the first scan signal to the first scan lines SL11 to SL1n. When the activated first scan signal is not supplied, the first scan driver 132 may supply the disabled first scan signal to each of the first scan lines SL11 to SL1n.

[0056] The second scan driver 134 may receive the second scan start signal FLM2 and generate a second scan signal by shifting the second scan start signal FLM2 in response to the clock signal. The second scan driver 134 may sequentially supply the second scan signal to the second scan lines SL21 to SL2n. When the activated second scan signal is not supplied, the second scan driver 134 may supply the disabled second scan signal to each of the second scan lines SL21 to SL2n.

[0057] The activated first scan signal and the activated second scan signal may refer to a gate-on voltage at which a transistor included in the pixel PX may be turned on. As an example, in a P-type transistor, the activated first scan signal and the activated second scan signal may be a low level voltage.

[0058] The disabled first scan signal and the disabled second scan signal may refer to a gate-off voltage at which a transistor included in the pixel PX may be turned off. As an example, in a P-type transistor, the disabled first scan signal and the disabled second scan signal may be a high level voltage.

[0059] Figure 2 The first scan driver 132 and the second scan driver 134 are shown to be connected to the first scan line SL1 and the second scan line SL2, respectively. However, embodiments of the inventive concept are not limited thereto. As an example, the first scan line SL1 and the second scan line SL2 may be driven by one scan driver.

[0060] The emission driver 150 may receive an emission driving signal ECS from the timing controller 120. The emission driving signal ECS may include an emission start signal and a clock signal required for driving the emission driver 150. The emission driver 150 may generate a first emission control signal and a second emission control signal by shifting the emission start signal in response to the clock signal. To this end, Figure 2 As shown in , the transmit driver 150 may include a first transmit driver 152 and a second transmit driver 154 .

[0061] The first emission driver 152 may receive the first emission start signal EFLM1 and generate a first emission control signal by shifting the first emission start signal EFLM1 in response to the clock signal. The first emission driver 152 may sequentially supply the first emission control signal to the first emission control lines EL11 to EL1n. When the disabled first emission control signal is not supplied, the first emission driver 152 may supply the activated first emission control signal to each of the first emission control lines EL11 to EL1n.

[0062] The second emission driver 154 may receive the second emission start signal EFLM2 and generate a second emission control signal by shifting the second emission start signal EFLM2 in response to the clock signal. The second emission driver 154 may sequentially supply the second emission control signal to the second emission control lines EL21 to EL2n. When the disabled second emission control signal is not supplied, the second emission driver 154 may supply the activated second emission control signal to each of the second emission control lines EL21 to EL2n.

[0063] Figure 2 The first emission driver 152 and the second emission driver 154 connected to the first emission control line EL1 and the second emission control line EL2, respectively, are shown, but embodiments of the inventive concept are not limited thereto. As an example, the first emission control line EL1 and the second emission control line EL2 may be driven by one emission driver.

[0064] The disabled first emission control signal and the disabled second emission control signal may refer to a gate-off voltage at which a transistor included in the pixel PX may be turned off. As an example, in a P-type transistor, the disabled emission control signal may be a high level voltage.

[0065] The activated first emission control signal and the activated second emission control signal may refer to a gate-on voltage at which a transistor included in the pixel PX may be turned on. As an example, in a P-type transistor, the activated emission control signal may be a low level voltage.

[0066] Return to reference Figure 1, the data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal required for driving the data driver 140. The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. As an example, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. Figure 4 As shown in , the data driver 140 may sequentially supply a voltage of a reference power source Vref and a voltage Vd corresponding to a data signal to the data lines DL1 to DLm during one horizontal period 1H.

[0067] The timing controller 120 may receive input data Din and a control signal CS from a host system via an interface. As an example, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS may include various signals including a clock signal.

[0068] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0069] The timing controller 120 may rearrange the input data Din to match the specifications of the display device 100. In addition, the timing controller 120 may correct the input data Din to generate the output data Dout and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din in response to an optical measurement result measured during a process.

[0070] The power supply unit 160 may generate various power sources required for driving the display device 100. As an example, the power supply unit 160 may generate a voltage of a first driving power source VDD and a voltage of a second driving power source VSS.

[0071] The first driving power source VDD may be a power source that supplies a driving current to the pixel PX. The second driving power source VSS may be a power source that receives a driving current from the pixel PX. During a period in which the pixel PX is set to emit light, the voltage of the first driving power source VDD may be set to a voltage higher than the voltage of the second driving power source VSS.

[0072] A voltage of the first driving power VDD generated in the power supply unit 160 may be supplied to the first power line PL1, and a voltage of the second driving power VSS generated in the power supply unit 160 may be supplied to the second power line PL2. The first power line PL1 and the second power line PL2 may be commonly connected to the pixel PX, but embodiments of the inventive concept are not limited thereto.

[0073] In an embodiment, the first power line PL1 may include a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may include a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. That is, in an embodiment of the inventive concept, the pixel PX may be connected to one of the first power lines PL1 and one of the second power lines PL2.

[0074] Figure 3 is a diagram illustrating a pixel according to an embodiment of the inventive concept. Figure 3 Pixels located on the i-th horizontal line and the j-th vertical line are shown.

[0075] Reference Figure 3 , the pixel PXij according to the embodiment of the inventive concept can be connected to the corresponding signal lines SL1i, SL2i, EL1i, EL2i and DLj. For example, the pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th first emission control line EL1i, the i-th second emission control line EL2i and the j-th data line DLj. In an embodiment, the pixel PXij can also be connected to the first power line PL1 and the second power line PL2.

[0076] A pixel PXij according to an embodiment of the inventive concept may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0077] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2.

[0078] As an example, a first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the first transistor M1, the third transistor M3, the second node N2, and the fourth transistor M4, and a second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light having a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0079] The light emitting element LD may be an organic light emitting diode. In addition, the light emitting element LD may be an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode. In addition, the light emitting element LD may be an element including a combination of an organic material and an inorganic material. Figure 3 In the embodiment, the pixel PXij includes a single light emitting element LD. However, in another embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series and parallel.

[0080] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, and a second capacitor C2.

[0081] In an embodiment, the first to fifth transistors M1 to M5 may be P-type transistors. However, this is only an example, and at least one of the first to fifth transistors M1 to M5 may be an N-type transistor.

[0082] The first electrode of the first transistor M1 (or the driving transistor) may be connected to the second electrode of the third transistor M3, and the second electrode of the first transistor M1 may be connected to the first electrode of the light emitting element LD. Here, the expression "connection" may include the meaning of electrical connection. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light emitting element LD in response to the voltage of the first node N1.

[0083] The second transistor M2 may be connected between the data line DLj and the first node N1. In addition, the gate electrode of the second transistor M2 may be electrically connected to the first scan line SL1i. When the activated first scan signal GW is supplied to the first scan line SL1i to electrically connect the data line DLj and the first node N1, the second transistor M2 may be turned on.

[0084] The first electrode of the third transistor M3 may be connected to the second node N2, and the second electrode of the third transistor M3 may be connected to the first electrode of the first transistor M1. In addition, the gate electrode of the third transistor M3 may be electrically connected to the first emission control line EL1i. When the disabled first emission control signal EM1 is supplied to the first emission control line EL1i to block the electrical connection between the second node N2 and the first transistor M1, the third transistor M3 may be turned off.

[0085] The fourth transistor M4 may be connected between the first power line PL1 and the second node N2. In addition, the gate electrode of the fourth transistor M4 may be electrically connected to the second emission control line EL2i. When the disabled second emission control signal EM2 is supplied to the second emission control line EL2i to block the electrical connection between the first power line PL1 and the second node N2, the fourth transistor M4 may be turned off.

[0086] The fifth transistor M5 may be connected between the first electrode of the light emitting element LD and the second power line PL2 (or the second electrode of the light emitting element LD). In addition, the gate electrode of the fifth transistor M5 may be electrically connected to the second scan line SL2i. When the activated second scan signal GI is supplied to the second scan line SL2i to electrically connect the first electrode of the light emitting element LD and the second power line PL2, the fifth transistor M5 may be turned on.

[0087] The first capacitor C1 may be connected between the first node N1 and the second node N2. The first capacitor C1 may store a voltage between the first node N1 and the second node N2. In addition, the first capacitor C1 may be driven as a coupling capacitor and may transfer the amount of voltage change at the first node N1 to the second node N2, or transfer the amount of voltage change at the second node N2 to the first node N1.

[0088] The second capacitor C2 may be connected between the second node N2 and the second scan line SL2i. The second capacitor C2 may be driven as a coupling capacitor and may transfer the amount of voltage change in the second scan line SL2i to the second node N2.

[0089] As described above, the pixel PXij according to the embodiment of the present invention may include five transistors M1 to M5 and two capacitors C1 and C2. In addition, the pixel PXij according to the embodiment of the present invention may be connected to two power lines PL1 and PL2. Generally, a conventional pixel is connected to three or more power lines and six or more transistors. The pixel PXij according to the embodiment of the present invention may be applied to a high-resolution display panel because the area occupied by the power lines and transistors may be minimized.

[0090] Figure 4 is shown for driving Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0091] Reference Figure 4 , also refer to Figure 1 , Figure 2 and Figure 3, a horizontal period 1H (or a specific horizontal period) in which data signals are supplied to pixels PXij located on an i-th horizontal line and a j-th vertical line may include a first period T1, a second period T2, a third period T3, a fourth period T4, and a fifth period T5.

[0092] The data driver 140 may supply the voltage of the reference power supply Vref to the data line DLj during the first period T1 and the second period T2, and supply the voltage Vd of the data signal to the data line DLj during the third period T3 and the fourth period T4. Here, even during the fifth period T5, the data driver 140 may supply the voltage Vd of the data signal to the data line DLj. The voltage of the reference power supply Vref may be set to a voltage (or a constant voltage) at which the first transistor M1 may be turned on when the voltage of the reference power supply Vref is supplied to the first node N1. As an example, the voltage of the reference power supply Vref may be set to a voltage lower than the voltage of the first driving power supply VDD. The voltage Vd of the data signal may be set to a voltage corresponding to the grayscale level of the pixel PXij.

[0093] The scan driver 130 (or the first scan driver 132) may supply the activated first scan signal GW to the first scan line SL1i during the first period T1 to the fourth period T4. The scan driver 130 (or the second scan driver 134) may supply the activated second scan signal GI to the second scan line SL2i during the first period T1 to the third period T3.

[0094] The emission driver 150 (or the first emission driver 152) may supply the disabled first emission control signal EM1 to the first emission control line EL1i during the third period T3 to the fifth period T5. The emission driver 150 (or the second emission driver 154) may supply the disabled second emission control signal EM2 to the second emission control line EL2i during the second period T2 to the fourth period T4.

[0095] The first period T1 may be a period in which the gate electrode of the first transistor M1 is initialized to the voltage of the reference power supply Vref. The second period T2 may be a period in which the threshold voltage of the first transistor M1 is compensated. The third period T3 and the fourth period T4 may be periods in which the voltage Vd of the data signal is supplied to the pixel PXij. The fifth period T5 may be a period in which the voltage Vd of the data signal and a voltage corresponding to the threshold voltage of the first transistor M1 are supplied to the first node N1. The light emitting element LD may be initialized during the first period T1 to the third period T3.

[0096] FIG. 5A to FIG. 5F is shown with Figure 4 A driving waveform corresponds to an embodiment of an operation process of a pixel.

[0097] Reference Figure 5A During the first period T1, the activated first scan signal GW may be supplied to the first scan line SL1i, and the activated second scan signal GI may be supplied to the second scan line SL2i. In addition, during the first period T1, the activated first emission control signal EM1 may be supplied to the first emission control line EL1i, and the activated second emission control signal EM2 may be supplied to the second emission control line EL2i. In addition, during the first period T1, the voltage of the reference power supply Vref may be supplied to the data line DLj.

[0098] When the activated first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 may be turned on. When the second transistor M2 is turned on, the voltage of the reference power supply Vref may be supplied from the data line DLj to the first node N1. Therefore, the first node N1 may be initialized to the voltage of the reference power supply Vref. Here, the voltage of the reference power supply Vref may be set to a voltage at which the first transistor M1 may be turned on. Therefore, the first transistor M1 may be set to a turned-on state.

[0099] When the activated second scan signal GI is supplied to the second scan line SL2i, the fifth transistor M5 may be turned on. When the fifth transistor M5 is turned on, the voltage of the second drive power supply VSS may be supplied to the first electrode of the light emitting element LD. When the voltage of the second drive power supply VSS is supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD may be discharged. As the voltage charged in the parasitic capacitor of the light emitting element LD is discharged (or removed), undesirable weak light emission may be prevented. Therefore, the black performance capability of the pixel PXij may be improved.

[0100] When the activated first emission control signal EM1 is supplied to the first emission control line EL1i, the third transistor M3 may be turned on. Therefore, the second node N2 and the first electrode of the first transistor M1 may be electrically connected to each other. When the activated second emission control signal EM2 is supplied to the second emission control line EL2i, the fourth transistor M4 may be turned on. Therefore, the first power line PL1 and the second node N2 may be electrically connected to each other.

[0101] During the first period T1, current supplied from the first power line PL1 may be supplied to the second power line PL2 via the fourth transistor M4, the third transistor M3, the first transistor M1, and the fifth transistor M5. Therefore, during the first period T1, the light emitting element LD does not emit light.

[0102] Reference Figure 5BDuring the second period T2, the disabled second emission control signal EM2 may be supplied to the second emission control line EL2i. In addition, during the second period T2, the supply of the activated first scan signal GW, the activated second scan signal GI, and the activated first emission control signal EM1 may be maintained.

[0103] When the disabled second emission control signal EM2 is supplied to the second emission control line EL2i, the fourth transistor M4 may be turned off. In this case, the first node N1 may maintain the voltage of the reference power source Vref.

[0104] When the fourth transistor M4 is turned off, the voltage of the second node N2 can be reduced to a voltage obtained by adding the absolute value of the threshold voltage of the first transistor M1 to the voltage of the reference power supply Vref from the first driving power supply VDD. Here, when the threshold voltage of the first transistor M1 has a negative polarity voltage (for example, -2V), the voltage of the second node N2 can be expressed as Vref-Vth (if Vref is -5V, then Vref-Vth=-3V). In the following description, it is assumed that the threshold voltage of the first transistor M1 has a negative polarity voltage.

[0105] During the second period T2, the first node N1 may maintain the voltage of the reference power supply Vref, and the second node N2 may be set to a voltage obtained by subtracting the threshold voltage of the first transistor M1 from the voltage of the reference power supply Vref. Therefore, during the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the first capacitor C1.

[0106] Reference Figure 5C During the third period T3, the disabled first emission control signal EM1 may be supplied to the first emission control line EL1i, and the voltage Vd of the data signal may be supplied to the data line DLj. In addition, during the third period T3, the supply of the activated first scan signal GW, the activated second scan signal GI, and the disabled second emission control signal EM2 may be maintained.

[0107] When the disabled first emission control signal EM1 is supplied to the first emission control line EL1i, the third transistor M3 may be turned off. When the third transistor M3 is turned off, electrical connection between the first electrode of the first transistor M1 and the second node N2 may be blocked, and thus the second node N2 may be set to a floating state.

[0108] During the third period T3, the voltage Vd of the data signal supplied to the data line DLj may be supplied to the first node N1 via the second transistor M2. In this case, the voltage of the first node N1 may be changed from the voltage of the reference power supply Vref to the voltage Vd of the data signal. In this case, the voltage of the second node N2 may also be changed by coupling of the first capacitor C1.

[0109] In an embodiment, the amount of voltage change at the second node N2 may be determined according to the ratio of the first capacitor C1 to the second capacitor C2, such as the change in voltage of the first node N1 multiplied by C1 / (C1+C2).

[0110] [Formula 1]

[0111] V(N2a)=Vref-Vth+(Vd-Vref)×C1 / (C1+C2)

[0112] In Formula 1, V(N2a) may represent the voltage of the second node N2 during the third period T3, (Vd-Vref) may represent the amount of change in voltage at the first node N1, Vth may represent the threshold voltage of the first transistor M1, and C1, C2, and C3 may represent the capacitance of the first capacitor C1, the capacitance of the second capacitor C2, and the capacitance of the third capacitor C3, respectively.

[0113] Reference Figure 5D During the fourth period T4, the disabled second scan signal GI may be supplied to the second scan line SL2i. In addition, during the fourth period T4, the supply of the activated first scan signal GW, the disabled first emission control signal EM1, and the disabled second emission control signal EM2 may be maintained. In addition, during the fourth period T4, the voltage Vd of the data signal may be supplied to the data line DLj.

[0114] When the disabled second scan signal GI is supplied to the second scan line SL2i, the fifth transistor M5 may be turned off. When the fifth transistor M5 is turned off, the electrical connection between the second power line PL2 and the first electrode of the light emitting element LD may be blocked. In this case, because the fourth transistor M4 and the third transistor M3 are kept in the off state, the light emitting element LD may not emit light.

[0115] At the same time, during the fourth period T4, the voltage of the second scan line SL2i may be changed from the voltage of the activated second scan signal GI (e.g., a low voltage) to the voltage of the disabled second scan signal GI (e.g., a high voltage). In this case, the voltage of the second node N2 may also be increased (or raised) by coupling of the second capacitor C2. As an example, the voltage of the second node N2 may be increased by a value obtained by multiplying the amount of voltage change in the second scan line SL2i by C2 / (C1+C2). This may be expressed as the following formula 2.

[0116] [Formula 2]

[0117] V(N2b)=Vref-Vth+(Vd-Vref)×C1 / (C1+C2)+(Vgh-Vgl)×C2 / (C1+C2)

[0118] In Formula 2, V(N2b) may represent a voltage of the second node N2 during the fourth period T4, Vgh may represent a voltage of the disabled second scan signal GI, and Vgl may represent a voltage of the activated second scan signal GI.

[0119] Reference Figure 5E During the fifth period T5, the disabled first scan signal GW may be supplied to the first scan line SL1i, and the activated second emission control signal EM2 may be supplied to the second emission control line EL2i. In addition, during the fifth period T5, the supply of the disabled second scan signal GI and the disabled first emission control signal EM1 may be maintained.

[0120] When the disabled first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 may be turned off. When the second transistor M2 is turned off, the first node N1 may be set to a floating state.

[0121] When the activated second emission control signal EM2 is supplied to the second emission control line EL2i, the fourth transistor M4 may be turned on. When the fourth transistor M4 is turned on, the voltage of the first driving power supply VDD may be supplied to the second node N2. In this case, the voltage of the second node N2 may be changed from the voltage of Formula 2 to the voltage of the first driving power supply VDD.

[0122] In addition, through the coupling of the first capacitor C1, the voltage of the first node N1 may change from the voltage Vd of the data signal to a voltage corresponding to the amount of voltage change at the second node N2. As an example, the voltage of the first node N1 may be expressed as Formula 3 below.

[0123] [Formula 3]

[0124] V(N1)=Vd+VDD-(Vref-Vth+(Vd-Vref)×C1 / (C1+C2)+(Vgh-Vgl)

[0125] ×C2 / (C1+C2))

[0126] In Formula 3, V(N1) may represent the voltage of the first node N1. The voltage of the first driving power supply VDD and the voltage of the reference power supply Vref may be maintained at a constant voltage. Therefore, the voltage of the first node N1 may be determined by the threshold voltage of the first transistor M1 and the voltage Vd of the data signal.

[0127] Reference Fig. 5F After the fifth period T5, the activated first emission control signal EM1 may be supplied to the first emission control line EL1i. In addition, after the fifth period T5, the supply of the disabled first scan signal GW, the disabled second scan signal GI, and the activated second emission control signal EM2 may be maintained.

[0128] Then, during the period after the fifth period T5, the second transistor M2 and the fifth transistor M5 may be turned off, and the third transistor M3 and the fourth transistor M4 may be turned on. In this case, the first transistor M1 may control the amount of current supplied from the first power line PL1 to the second power line PL2 via the light emitting element LD in response to the voltage of the first node N1. As shown in Formula 3, the first node N1 may have a voltage in which the threshold voltage of the first transistor M1 has been considered. Therefore, the current in which the threshold voltage of the first transistor M1 is compensated may be supplied to the light emitting element LD. During the period after the fifth period T5, the light emitting element LD may generate light with a predetermined brightness in response to the amount of current supplied from the first transistor M1.

[0129] Figure 6 It is shown Figure 3 Figure 2 shows the simulation results for the pixel shown in . Figure 6 , the X-axis may represent time, and the Y-axis may represent voltage (V).

[0130] Reference Figure 6 , also refer to Figure 1 and Figure 3 , when the voltage Vd of the data signal is supplied as -4V, -2V, 0V, 2V, and 4V, the voltage VN1 of the first node N1 may change in response to the voltage Vd of the data signal. That is, in an embodiment of the inventive concept, the voltage VN1 of the first node N1 may change in response to the change of the voltage Vd of the data signal, and thus, light having a brightness corresponding to the voltage Vd of the data signal may be generated in the pixel PXij.

[0131] Table 1 below shows a calculated voltage (calculated VG) of the first node N1 and a simulated voltage (simulated VG) of the first node N1.

[0132] [Table 1]

[0133] Vd Calculated VG Emulated VG -4V 1.5 1.55 -2V 1.7 1.75 0V 1.9 1.95 2V 2.1 2.15 4V 2.3 2.35

[0134] In Table 1, it is assumed that the threshold voltage (Vth) of the first transistor M1 is -2V, the gate-on voltage supplied to the scan lines SL1, SL2, and SL3 and the emission control lines EL1 and EL2 is -8V, and the gate-off voltage is 8V. In addition, it is assumed that the capacitance of the first capacitor C1 is 9α, and the capacitance of the second capacitor C2 is 1α. Referring to Table 1, the voltage of the first node N1 calculated according to the voltage Vd of the data signal (i.e., the calculated VG) may have a voltage difference of about 0.05V from the voltage of the first node N1 obtained by simulation (i.e., the simulated VG). That is, the pixel PX according to the embodiment of the inventive concept can be driven as expected.

[0135] Figure 7 is shown for driving Figure 3 The waveform diagram of the embodiment of the pixel method shown in FIG. Figure 7 When Figures 4 to 5F Description of the overlapping part.

[0136] Reference Figure 7 , also refer to Figure 3 During the first period T1a to the fourth period T4, the disabled second emission control signal EM2 may be supplied to the second emission control line EL2i. Figure 7 The driving waveform and Figure 4 Compared with the driving waveform, Figure 7 There may be a difference that the second emission control signal EM2 is supplied disabled during the first period T1a.

[0137] During the first period T1a, when the disabled second emission control signal EM2 is supplied, the fourth transistor M4 may be set to a cut-off state. Then, similar to Figure 5B In the second period T2 shown in FIG. 1 , the threshold voltage of the first transistor M1 can be compensated during the first period T1a. That is, in Figure 7 In the driving waveform of FIG. 1 , the threshold voltage of the first transistor M1 may be compensated during the first period T1a and the second period T2.

[0138] Figure 8 is a diagram illustrating a pixel according to an embodiment of the inventive concept. Figure 8 Pixels located on the i-th horizontal line and the j-th vertical line are shown. Figure 8When Figure 3 The same components are described repeatedly.

[0139] Reference Figure 8 , the pixel PXija according to an embodiment of the inventive concept may be connected to corresponding signal lines SL1i, SL2i, EL1i, EL2i, and DLj.

[0140] A pixel PXija according to an embodiment of the inventive concept may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0141] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 and may generate light having a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0142] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0143] Will Figure 8 The pixels PXija shown in Figure 3 Compared with the pixel PXij shown in Figure 8 In the pixel PXija shown in FIG. 1 , a third capacitor C3 is additionally provided. In this case, during the fourth period T4, the voltage of the second node N2 can be increased by a voltage obtained by multiplying the amount of voltage change in the second scan line SL2i by approximately C2 / (C1+C2+C3). That is, when the third capacitor C3 is added, the amount of voltage increase at the second node N2 can be controlled.

[0144] Fig. 9 is a diagram illustrating a pixel according to an embodiment of the inventive concept. Fig. 9 Pixels located on the i-th horizontal line and the j-th vertical line are shown. Fig. 9 When Figure 3 The same components are described repeatedly.

[0145] Reference Fig. 9 , a pixel PXijb according to an embodiment of the inventive concept may be connected to corresponding signal lines SL1i, SL2i, EL1i, EL2i, and DLj.

[0146] A pixel PXijb according to an embodiment of the inventive concept may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0147] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 and may generate light having a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0148] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, and a second capacitor C2b. The second capacitor C2b may be connected between the second node N2 and the first emission control line EL1i.

[0149] Refer to the following Figure 4 and Fig. 9 The operation process is briefly described. During the third period T3, the voltage of the second node N2 can be changed by the voltage Vd of the data signal supplied to the first node N1. In addition, during the third period T3, the voltage of the second node N2 can be changed by the disabled first emission control signal EM1 supplied to the first emission control line EL1i. That is, during Fig. 9 In the pixel PXijb, during the third period T3, the voltage of the second node N2 may change in response to the amount of change in the voltage in the first emission control line EL1i.

[0150] After the fifth period T5, the activated first emission control signal EM1 may be supplied to the first emission control line EL1i. In this case, the second node N2 may maintain the voltage of the driving power supply VDD. Therefore, the amount of voltage change in the first emission control line EL1i may not affect the voltage of the second node N2.

[0151] That is, in the pixel PXijb according to the embodiment of the inventive concept, the voltage of the second node N2 may increase in response to the amount of voltage change in the first emission control line EL1i, and the voltage and driving process of each node corresponding thereto may be the same as Figure 3 The pixels in are the same.

[0152] Fig.10 is a diagram illustrating a pixel according to an embodiment of the inventive concept. Fig.10 Pixels located on the i-th horizontal line and the j-th vertical line are shown. Fig.10 When Figure 3 The same components are described repeatedly.

[0153] Reference Fig.10 , a pixel PXijc according to an embodiment of the inventive concept may be connected to corresponding signal lines SL1i, SL2i, EL1i, EL2i, and DLj.

[0154] A pixel PXijc according to an embodiment of the inventive concept may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0155] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 and may generate light having a predetermined brightness in response to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0156] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5c, a first capacitor C1, and a second capacitor C2.

[0157] The fifth transistor M5c may be connected between the first electrode of the light emitting element LD and the third power line PL3. The third power line PL3 may receive a voltage of an initialization power source Vinit. The voltage of the initialization power source Vinit may be set to a voltage smaller than a threshold voltage of the light emitting element LD when the voltage of the initialization power source Vinit is supplied to the first electrode of the light emitting element LD (the light emitting element LD is turned off at the threshold voltage of the light emitting element LD).

[0158] In addition to the fifth transistor M5c being connected to the third power line PL3, Fig.10 The actual operation process of the pixel PXijc can be compared with Figure 3 The actual operation process of the pixels is the same.

[0159] Figures 11 to 14 is a diagram illustrating an electronic device according to various embodiments.

[0160] Reference Fig.11 , also refer to Figure 1 , the display device 100 according to the above embodiment may be applied to smart glasses. The smart glasses may include a frame 111 and a lens unit 112. The smart glasses may be a wearable electronic device that can be worn on the face of a user, and may have a structure in which a portion of the frame 111 is folded or unfolded. For example, the smart glasses may be a wearable device for augmented reality (AR).

[0161] The frame 111 may include a housing 111b supporting the lens unit 112 and a leg member 111a to be worn by a user. The leg member 111a may be connected to the housing 111b by a hinge and may be folded or unfolded.

[0162] A battery, a touch panel, a microphone, a camera, etc. may be built into the frame 111. In addition, a projector that outputs light, a processor that controls an optical signal, etc. may be built into the frame 111.

[0163] The lens unit 112 may be an optical member that transmits or reflects light. The lens unit 112 may include glass, a transparent synthetic resin, or the like.

[0164] The display device 100 according to the above-described embodiment may be applied to the lens unit 112. As an example, the user may visually recognize an image displayed by an optical signal transmitted from the projector of the frame 111 through the lens unit 112. For example, the user may visually recognize information such as time and date displayed on the lens unit 112.

[0165] Reference Fig.12 , also refer to Figure 1 The display device 100 according to the above embodiment may be applied to a head mounted display (HMD). The head mounted display may include a head mounted band 121 and a display storage box 122. For example, the head mounted display may be a wearable electronic device that may be worn on the user's head.

[0166] The headband 121 may be connected to the display storage box 122, and the display storage box 122 may be securely fixed to the user's head. The headband 121 may include a horizontal band and a vertical band to fix the head-mounted display to the user's head. The horizontal band may be provided to surround the side of the user's head, and the vertical band may be provided to surround the top of the user's head. However, the inventive concept is not necessarily limited thereto, and the headband 121 may be implemented in the form of a glasses frame or a helmet.

[0167] The display storage box 122 can accommodate the display device 100 and can include at least one lens. At least one lens can provide an image to a user. For example, the display device 100 according to the above embodiment can be applied to a left eye lens and a right eye lens implemented in the display storage box 122.

[0168] Reference Fig.13 , also refer to Figure 1 , the display device 100 according to the above embodiment may be applied to a smart watch. The smart watch may include a display unit 131 and a strap unit 133. The smart watch may be a wearable electronic device, and the strap unit 133 may be mounted on a user's wrist. The display device 100 according to the above embodiment may be applied to the display unit 131. For example, the display unit 131 may provide image data including information such as time and date.

[0169] Reference Fig.14 , also refer to Figure 1 The display device 100 according to the above embodiment may be applied to a car display. For example, the car display may refer to an electronic device provided inside and outside a vehicle to provide image data.

[0170] For example, the display device 100 according to the above embodiment can be applied to at least one of the infotainment panel 141, the instrument panel 142, the passenger display 143, the head-up display 144, the side mirror display 145 and the rear seat display 146 provided in the vehicle.

[0171] A pixel according to an embodiment of the inventive concept may be applied to a high-resolution display panel because it may compensate for a threshold voltage of a driving transistor using five transistors and two (or three) capacitors.

[0172] However, the effects of the inventive concept are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the inventive concept.

[0173] As described above, the preferred embodiments of the inventive concept have been described with reference to the accompanying drawings. However, those skilled in the art will appreciate that various modifications and changes may be made to the inventive concept without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A pixel, wherein The pixels include: a first transistor having a first electrode electrically connected to a first power supply line, a second electrode, and a gate electrode connected to a first node; a light emitting element connected between the second electrode of the first transistor and a second power line; a second transistor connected between the first node and the data line, and having a gate electrode electrically connected to the first scan line; a third transistor connected between the first electrode of the first transistor and a second node, and having a gate electrode electrically connected to a first emission control line; a fourth transistor connected between the first power supply line and the second node, and having a gate electrode electrically connected to a second emission control line; and a first capacitor connected between the first node and the second node, During a horizontal period, a voltage of a reference power source and a voltage of a data signal are sequentially supplied to the data lines.

2. The pixel according to claim 1, wherein: The pixel also includes: A fifth transistor is connected between the first electrode of the light emitting element and the second power supply line, and has a gate electrode electrically connected to the second scanning line.

3. The pixel according to claim 2, wherein: The pixel also includes: a second capacitor connected between the second node and the second scan line; and A third capacitor is connected between the second node and the first power line.

4. The pixel according to claim 2, wherein: The horizontal period includes a first period, a second period, a third period, a fourth period and a fifth period, The fifth transistor is turned on during the first period to the third period. The second transistor is turned on during the first period to the fourth period, wherein the fourth transistor is turned off during the second period to the fourth period, and The third transistor is turned off during the third period to the fifth period.

5. The pixel according to claim 4, wherein: The voltage of the reference power source is supplied to the data line during the first period and the second period, and the voltage of the data signal is supplied to the data line during the third period and the fourth period.

6. The pixel according to claim 2, wherein: The horizontal period includes a first period, a second period, a third period, a fourth period and a fifth period, The fifth transistor is turned on during the first period to the third period. The second transistor is turned on during the first period to the fourth period, The fourth transistor is turned off during the first period to the fourth period. wherein the third transistor is turned off during the third period to the fifth period, and The voltage of the reference power source is supplied to the data line during the first period and the second period, and the voltage of the data signal is supplied to the data line during the third period and the fourth period.

7. The pixel according to claim 2, wherein: The pixel also includes: A second capacitor is connected between the second node and the first emission control line.

8. The pixel according to claim 1, wherein: A voltage of a first driving power source is supplied to the first power source line, and a voltage of a second driving power source lower than the voltage of the first driving power source is supplied to the second power source line, and The reference power source has the voltage lower than the voltage of the first driving power source.

9. The pixel according to claim 1, wherein: The pixel also includes: a fifth transistor connected between the first electrode of the light emitting element and a third power supply line, and having a gate electrode electrically connected to the second scan line; and The second capacitor is connected between the second node and the second scan line.

10. The pixel according to claim 9, wherein: A voltage of an initialization power source is supplied to the third power source line, and when the voltage of the initialization power source is supplied to the first electrode of the light emitting element, the light emitting element is turned off.

Images