Display device

Abstract

A display device driven at high speed is provided. The display device comprises pixels, a scanning line driving circuit and a power supply circuit. The pixel includes first and second transistors in which a semiconductor layer is disposed inside an opening in an interlayer insulating layer formed on a substrate. A first conductive layer serving as a gate electrode of the first transistor has a region extending in a first direction and is electrically connected to the scan line driving circuit. A second conductive layer serving as a source electrode or a drain electrode of the second transistor is disposed under the opening. The second conductive layer has a region extending in a second direction perpendicular to the first direction and is electrically connected to the power supply circuit. The first conductive layer and the second conductive layer have regions that overlap each other with an interlayer insulating layer therebetween.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device, a semiconductor device, a display module, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a display device and a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields for one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them. Background Technology

[0003] Semiconductor devices, including transistors, are widely used in display devices and electronic devices, requiring high integration and high speed. For example, when using semiconductor devices in high-definition display devices, highly integrated semiconductor devices are needed. As one method to improve the integration of transistors, the development of micro-transistors is underway.

[0004] In recent years, there has been a high demand for display devices that can be used in Virtual Reality (VR), Augmented Reality (AR), Substitutional Reality (SR), or Mixed Reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). To enhance the sense of realism and immersion, XR display devices are required to have high resolution and high color reproduction. Examples of devices that can be used in these display devices include liquid crystal displays and light-emitting devices incorporating light-emitting elements such as organic EL (Electroluminescence) elements and light-emitting diodes (LEDs).

[0005] Patent document 1 discloses a VR display device using organic EL elements (also known as organic EL devices). [Preliminary Technology Documents] [Patent Literature]

[0006] [Patent Document 1] International Patent Application Publication No. 2018 / 087625 Summary of the Invention The technical problem that the invention aims to solve

[0007] In order to improve the resolution of the display device and increase the number of pixels per unit area, for example, it is preferable to drive the display device at high speed to ensure the frame rate.

[0008] In view of this, one objective of the present invention is to provide a display device driven at high speed and a method for manufacturing the same. Another objective of the present invention is to provide a high-definition display device and a method for manufacturing the same. Another objective of the present invention is to provide a display device including microtransistors and a method for manufacturing the same. Another objective of the present invention is to provide a display device with high on-state current and a method for manufacturing the same. Another objective of the present invention is to provide a display device with good electrical characteristics and a method for manufacturing the same. Finally, one objective of the present invention is to provide a novel display device, a novel semiconductor device, and a method for manufacturing the same.

[0009] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Note that objectives other than those described above can be extracted from the description, drawings, claims, etc. means of solving technical problems

[0010] One aspect of the present invention is a display device including pixels, a power supply circuit, and a scan line driving circuit. Each pixel includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer. The first insulating layer is disposed on the first conductive layer and includes a first opening extending into the first conductive layer. The first conductive layer is electrically connected to the power supply circuit. The second conductive layer is disposed on the first insulating layer and includes a second opening having a region overlapping the first opening. The first semiconductor layer has a region contacting the first conductive layer and a region contacting the second conductive layer, and has a region located inside the first opening. The second insulating layer is disposed on the first semiconductor in such a way that it has a region located inside the second opening and a region located inside the second opening. The third conductive layer is disposed in such a way that it has a region located inside the first opening and a region located inside the second opening, and has a region sandwiching the second insulating layer and opposing the first semiconductor layer. The second transistor includes the second insulating layer, the second semiconductor layer below the second insulating layer, and the fourth conductive layer on the second insulating layer. The fourth conductive layer has a region overlapping the second semiconductor layer. The fourth conductive layer is electrically connected to the scan line driving circuit. The fourth conductive layer has a region separated from the first insulating layer and the second insulating layer overlapping the first conductive layer.

[0011] In addition, in the above-described manner, the second transistor may also include a fifth conductive layer that is in contact with the second semiconductor layer, and the fifth conductive layer may also be electrically connected to the third conductive layer.

[0012] In addition, in the above-described manner, the display device may also include a signal line driving circuit, the second transistor may also include a sixth conductive layer in contact with the second semiconductor layer, and the sixth conductive layer may also be electrically connected to the signal line driving circuit.

[0013] In addition, in the above method, the pixel may also include a display element, and the pixel electrode of the display element may also be electrically connected to the second conductive layer.

[0014] Alternatively, in the above-described manner, the display device may also have the following structure: including a reference potential generation circuit, a pixel including a third transistor, the third transistor including a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a third semiconductor layer, and a second insulating layer, a first insulating layer disposed on the seventh conductive layer, the first insulating layer including a third opening reaching the seventh conductive layer, the seventh conductive layer being electrically connected to a pixel electrode, an eighth conductive layer disposed on the first insulating layer, the eighth conductive layer including a fourth opening having a region overlapping with the third opening, the eighth conductive layer being electrically connected to the reference potential generation circuit, the third semiconductor layer being disposed such that it has a region contacting the seventh conductive layer and a region contacting the eighth conductive layer, and has a region located inside the third opening and a region located inside the fourth opening, the second insulating layer being disposed on the third semiconductor layer such that it has a region located inside the third opening and a region located inside the fourth opening, the ninth conductive layer being disposed such that it has a region located inside the third opening and a region located inside the fourth opening, and has a region sandwiching the second insulating layer and opposing the third semiconductor layer, the ninth conductive layer being electrically connected to a scan line driving circuit, and the eighth conductive layer having a region overlapping with the fourth conductive layer and a region overlapping with the ninth conductive layer.

[0015] Another aspect of the present invention is a display device including pixels, a scan line driving circuit, and a power supply circuit. The pixel includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer. The first insulating layer is disposed on the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is disposed on the first insulating layer and includes a second opening having a region overlapping the first opening. The first semiconductor layer is disposed such that it has a region contacting the first conductive layer and a region contacting the second conductive layer, and has regions located inside the first opening and regions located inside the second opening. The second insulating layer is disposed on the first semiconductor layer such that it has regions located inside the first opening and regions located inside the second opening. The third conductive layer is disposed such that it has regions located inside the first opening and regions located inside the second opening, and has a region sandwiching the second insulating layer and opposing the first semiconductor layer. The three conductive layers are electrically connected to the scan line driving circuit. The second transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a second semiconductor layer, and a second insulating layer. The first insulating layer is disposed on the fourth conductive layer and includes a third opening reaching the fourth conductive layer. The fourth conductive layer is electrically connected to the power supply circuit. The fifth conductive layer is disposed on the first insulating layer and includes a fourth opening having a region overlapping with the third opening. The second semiconductor layer is disposed such that it has a region contacting the fourth conductive layer and a region contacting the fifth conductive layer, and has a region located inside the third opening and a region located inside the fourth opening. The second insulating layer is disposed on the second semiconductor layer such that it has a region located inside the third opening and a region located inside the fourth opening. The sixth conductive layer is disposed such that it has a region located inside the third opening and a region located inside the fourth opening, and has a region sandwiching the second insulating layer and opposing the second semiconductor layer. The third conductive layer includes a region that overlaps with the fourth conductive layer and the second insulating layer.

[0016] In addition, in the above-described manner, the display device may also include a signal line driving circuit, the first conductive layer may also be electrically connected to the signal line driving circuit, and the first conductive layer may also have a region overlapping with the third conductive layer.

[0017] In addition, in the above method, the second conductive layer can also be electrically connected to the sixth conductive layer.

[0018] In addition, in the above method, the pixel may also include a display element, and the pixel electrode of the display element may also be electrically connected to the fifth conductive layer.

[0019] Alternatively, in the above-described manner, the display device may also have the following structure: including a reference potential generation circuit, a pixel including a third transistor, the third transistor including a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a third semiconductor layer, and a second insulating layer, a first insulating layer disposed on the seventh conductive layer, the first insulating layer including a fifth opening reaching the seventh conductive layer, the seventh conductive layer being electrically connected to a pixel electrode, an eighth conductive layer disposed on the first insulating layer, the eighth conductive layer including a sixth opening having a region overlapping with the fifth opening, the eighth conductive layer being electrically connected to the reference potential generation circuit, the third semiconductor layer being disposed such that it has a region contacting the seventh conductive layer and a region contacting the eighth conductive layer, and has a region located inside the fifth opening and a region located inside the sixth opening, the second insulating layer being disposed on the third semiconductor layer such that it has a region located inside the fifth opening and a region located inside the sixth opening, the ninth conductive layer being disposed such that it has a region located inside the fifth opening and a region located inside the sixth opening, and has a region sandwiching the second insulating layer and opposing the third semiconductor layer, the ninth conductive layer being electrically connected to a scan line driving circuit, and the eighth conductive layer having a region overlapping with the third conductive layer and a region overlapping with the ninth conductive layer.

[0020] In addition, in the above-described manner, the first to third semiconductor layers may also comprise metal oxides. The metal oxides may, for example, comprise indium, zinc, and M (M being one or more selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium, and hafnium). Invention Effects

[0021] According to one aspect of the present invention, a high-speed driven display device and a method for manufacturing the same can be provided. Additionally, according to one aspect of the present invention, a high-definition display device and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a display device including micro-transistors and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a display device including transistors with high on-state current and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a display device with good electrical characteristics and a method for manufacturing the same can be provided. Additionally, according to one aspect of the present invention, a novel display device, a novel semiconductor device, and a method for manufacturing the same can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Brief description of the attached figures

[0023] Figure 1A This is a block diagram illustrating an example of the structure of a display device. Figure 1BThis is a planar diagram showing an example of the structure of a pixel. Figure 1C and Figure 1D This is a circuit diagram showing an example of the structure of a pixel. Figure 2A This is a block diagram illustrating an example of the structure of a display device. Figure 2B This is a circuit diagram showing an example of the structure of a pixel. Figures 3A to 3C This is a circuit diagram showing an example of the structure of a pixel. Figures 4A1 to 4A3 This is a plan view showing an example of the structure of a display device. Figure 4B This is a cross-sectional view showing an example of the structure of a display device. Figure 5A This is a plan view showing an example of the structure of a display device. Figure 5B This is a cross-sectional view showing an example of the structure of a display device. Figure 6 This is a plan view showing an example of the structure of a display device. Figure 7 This is a cross-sectional view showing an example of the structure of a display device. Figure 8A This is a plan view showing an example of the structure of a display device. Figure 8B This is a cross-sectional view showing an example of the structure of a display device. Figure 9 This is a plan view showing an example of the structure of a display device. Figure 10A This is a plan view showing an example of the structure of a display device. Figure 10B This is a cross-sectional view showing an example of the structure of a display device. Figure 11 This is a plan view showing an example of the structure of a display device. Figure 12A This is a plan view showing an example of the structure of a display device. Figure 12B This is a cross-sectional view showing an example of the structure of a display device. Figure 13 This is a plan view showing an example of the structure of a display device. Figure 14A This is a plan view showing an example of the structure of a display device. Figure 14B This is a cross-sectional view showing an example of the structure of a display device. Figure 15A This is a plan view showing an example of the structure of a display device. Figure 15B This is a cross-sectional view showing an example of the structure of a display device. Figure 16 This is a plan view showing an example of the structure of a display device. Figure 17 This is a plan view showing an example of the structure of a display device. Figure 18 This is a plan view showing an example of the structure of a display device. Figure 19 This is a plan view showing an example of the structure of a display device. Figure 20A This is a plan view showing an example of the structure of a display device. Figure 20B This is a cross-sectional view showing an example of the structure of a display device. Figure 21A This is a plan view showing an example of the structure of a display device. Figure 21B This is a cross-sectional view showing an example of the structure of a display device. Figure 22A This is a plan view showing an example of the structure of a display device. Figure 22B This is a cross-sectional view showing an example of the structure of a display device. Figure 23 This is a plan view showing an example of the structure of a display device. Figure 24A This is a plan view showing an example of the structure of a display device. Figure 24B This is a cross-sectional view showing an example of the structure of a display device. Figure 25 This is a plan view showing an example of the structure of a display device. Figure 26A This is a plan view showing an example of the structure of a display device. Figure 26B This is a cross-sectional view showing an example of the structure of a display device. Figure 27 This is a plan view showing an example of the structure of a display device. Figure 28A This is a plan view showing an example of the structure of a display device. Figure 28B This is a cross-sectional view showing an example of the structure of a display device. Figure 29 This is a plan view showing an example of the structure of a display device. Figure 30A This is a plan view showing an example of the structure of a display device. Figure 30B This is a cross-sectional view showing an example of the structure of a display device. Figure 31 This is a plan view showing an example of the structure of a display device. Figure 32A This is a plan view showing an example of the structure of a display device. Figure 32B This is a cross-sectional view showing an example of the structure of a display device. Figure 33 This is a plan view showing an example of the structure of a display device. Figure 34A This is a plan view showing an example of the structure of a display device. Figure 34B This is a cross-sectional view showing an example of the structure of a display device. Figure 35 This is a plan view showing an example of the structure of a display device. Figure 36A This is a plan view showing an example of the structure of a display device. Figure 36B This is a cross-sectional view showing an example of the structure of a display device. Figure 37 This is a plan view showing an example of the structure of a display device. Figure 38A This is a plan view showing an example of the structure of a display device. Figure 38B This is a cross-sectional view showing an example of the structure of a display device. Figure 39A This is a block diagram illustrating an example of the structure of a display device. Figures 39B to 39F This is a circuit diagram showing an example of the structure of a memory cell. Figures 40A to 40C This is a plan view showing an example of the structure of a display device. Figure 41A This is a plan view showing an example of the structure of a display device. Figure 41B This is a cross-sectional view showing an example of the structure of a display device. Figure 42A This is a plan view showing an example of the structure of a display device. Figure 42B This is a cross-sectional view showing an example of the structure of a display device. Figure 43A This is a plan view showing an example of the structure of a display device. Figures 43B1 to 43B3 This is a cross-sectional view showing an example of the structure of a display device. Figure 44A and Figure 44B This is a plan view showing an example of the structure of a display device. Figure 45A1 and Figure 45A2 This is a plan view showing an example of the structure of a display device. Figure 45B This is a cross-sectional view showing an example of the structure of a display device. Figure 46A This is a plan view showing an example of the structure of a display device. Figure 46B This is a cross-sectional view showing an example of the structure of a display device. Figure 47A This is a plan view showing an example of the structure of a display device. Figure 47B This is a cross-sectional view showing an example of the structure of a display device. Figure 48A This is a plan view showing an example of the structure of a display device. Figure 48B This is a cross-sectional view showing an example of the structure of a display device. Figure 49A1 and Figure 49A2 This is a plan view showing an example of the structure of a display device. Figure 49BThis is a cross-sectional view showing an example of the structure of a display device. Figure 50A This is a plan view showing an example of the structure of a display device. Figure 50B This is a cross-sectional view showing an example of the structure of a display device. Figure 51A This is a plan view showing an example of the structure of a display device. Figure 51B This is a cross-sectional view showing an example of the structure of a display device. Figure 52A and Figure 52B This is a plan view showing an example of the structure of a display device. Figure 53A1 and Figure 53A2 This is a plan view showing an example of the structure of a display device. Figure 53B This is a cross-sectional view showing an example of the structure of a display device. Figure 54A This is a plan view showing an example of the structure of a display device. Figure 54B1 and Figure 54B2 This is a cross-sectional view showing an example of the structure of a display device. Figure 55A and Figure 55B This is a cross-sectional view showing an example of the structure of a display device. Figure 56A and Figure 56B This is a cross-sectional view showing an example of the structure of a display device. Figure 57A and Figure 57B This is a cross-sectional view showing an example of the structure of a display device. Figure 58A This is a plan view showing an example of the structure of a display device. Figure 58B This is a cross-sectional view showing an example of the structure of a display device. Figure 59A and Figure 59B This is a plan view showing an example of the structure of a display device. Figure 60A This is a plan view showing an example of the structure of a display device. Figure 60B This is a cross-sectional view showing an example of the structure of a display device. Figures 61A to 61C This is a plan view showing an example of the structure of a display device. Figures 62A to 62C This is a plan view showing an example of the structure of a display device. Figure 63A and Figure 63B This is a plan view showing an example of the structure of a display device. Figure 64A This is a plan view showing an example of the structure of a display device. Figure 64B This is a cross-sectional view showing an example of the structure of a display device. Figure 65A This is a plan view showing an example of the structure of a display device. Figure 65B This is a cross-sectional view showing an example of the structure of a display device. Figure 66 This is a plan view showing an example of the structure of a display device. Figures 67A to 67C This is a plan view showing an example of the structure of a display device. Figure 68A and Figure 68B This is a plan view showing an example of the structure of a display device. Figure 69A This is a plan view showing an example of the structure of a display device. Figure 69B This is a cross-sectional view showing an example of the structure of a display device. Figure 70A1 and Figure 70A2 This is a plan view showing an example of the structure of a display device. Figure 70B This is a cross-sectional view showing an example of the structure of a display device. Figure 71A This is a plan view showing an example of the structure of a display device. Figure 71B This is a cross-sectional view showing an example of the structure of a display device. Figure 72A This is a plan view showing an example of the structure of a display device. Figure 72B This is a cross-sectional view showing an example of the structure of a display device. Figure 73A This is a plan view showing an example of the structure of a display device. Figure 73B This is a cross-sectional view showing an example of the structure of a display device. Figures 74A to 74C This is a plan view showing an example of the structure of a display device. Figures 75A to 75C This is a plan view showing an example of the structure of a display device. Figure 76A and Figure 76B This is a plan view showing an example of the structure of a display device. Figure 77A This is a plan view showing an example of the structure of a display device. Figure 77B This is a cross-sectional view showing an example of the structure of a display device. Figure 78A1 and Figure 78B1 This is a plan view illustrating an example of a manufacturing method for a display device. Figure 78A2 and Figure 78B2 This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 79A1 and Figure 79B1 This is a plan view illustrating an example of a manufacturing method for a display device. Figure 79A2 and Figure 79B2This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 80A1 and Figure 80B1 This is a plan view illustrating an example of a manufacturing method for a display device. Figure 80A2 and Figure 80B2 This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 81A1 and Figure 81B1 This is a plan view illustrating an example of a manufacturing method for a display device. Figure 81A2 and Figure 81B2 This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 82A1 and Figure 82B1 This is a plan view illustrating an example of a manufacturing method for a display device. Figure 82A2 and Figure 82B2 This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figures 83A to 83G This is a planar diagram showing an example of the structure of a pixel. Figures 84A to 84K This is a planar diagram showing an example of the structure of a pixel. Figure 85 This is a perspective view showing an example of the structure of a display device. Figure 86 This is a cross-sectional view showing an example of the structure of a display device. Figure 87 This is a cross-sectional view showing an example of the structure of a display device. Figure 88 This is a cross-sectional view showing an example of the structure of a display device. Figure 89 This is a cross-sectional view showing an example of the structure of a display device. Figure 90 This is a cross-sectional view showing an example of the structure of a display device. Figure 91 This is a cross-sectional view showing an example of the structure of a display device. Figures 92A to 92D This is a diagram illustrating an example of an electronic device. Figures 93A to 93F This is a diagram illustrating an example of an electronic device. Figures 94A to 94G This is a diagram illustrating an example of an electronic device. Methods of implementing the invention

[0024] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0025] Note that in the inventive structure described below, the same symbols are used in different figures to show the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, the same shading lines are sometimes used to indicate parts with the same function, without special additional symbols. Moreover, the same shading lines are sometimes used for multiple layers that can be formed by the same process.

[0026] For ease of understanding, the positions, sizes, and extents of structures shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0027] Furthermore, depending on the circumstances or state, the "film" and "layer" can be interchanged. For example, sometimes a "conductive layer" can be changed into a "conductive film." Or, for example, sometimes an "insulating film" can be changed into an "insulating layer."

[0028] Furthermore, in this specification and other documents, "electrode" and "wiring" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as part of a "wiring," and vice versa. Moreover, "electrode" or "wiring" also includes cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0029] In this specification and other materials, the structure in which at least one light-emitting layer is fabricated in each light-emitting element with a different emission wavelength is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for optimization of materials and structure for each light-emitting element, the freedom in material and structure selection is increased, making it easier to achieve improvements in brightness and reliability.

[0030] In this specification, the light-emitting element (also called a light-emitting device) includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, the layers included in the EL layer (also called functional layers) can be categorized as light-emitting layers, carrier injection layers (hole injection layers and electron injection layers), carrier transport layers (hole transport layers and electron transport layers), and carrier blocking layers (hole blocking layers and electron blocking layers). Note that the carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable based on their cross-sectional shape or characteristics. In addition, sometimes a single layer performs the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0031] In this specification and the like, the light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes.

[0032] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (also called the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface, substrate surface, and surface to be formed of the constituent element do not necessarily have to be completely flat; they may also be approximately planar with slight curvature or approximately planar with slight irregularities.

[0033] In this specification and the like, unless otherwise stated, when the side surface of a layer has a tapered shape, the outermost portion of that side surface is referred to as the end of the layer. For example, unless otherwise stated, when the bottom end of a layer is located outside the top end, the bottom end of the layer is simply referred to as the end.

[0034] Furthermore, in this specification and other materials, for convenience, terms such as "upper," "lower," "left," and "right" are used to indicate the arrangement and to illustrate the positional relationships of the constituent elements with reference to the accompanying drawings. Moreover, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in the specification, and may be appropriately replaced as needed.

[0035] In this specification and the like, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (or simply OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, it is sometimes referred to as an oxide semiconductor. In other words, when described as an OS transistor, it can be converted into a transistor containing either a metal oxide or an oxide semiconductor. Note that sometimes nitrogen-containing metal oxides are collectively referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0036] (Implementation Method 1) In this embodiment, a display device and its manufacturing method according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0037] One aspect of the present invention relates to a display device, including a display section, a scan line driving circuit, a signal line driving circuit, and a power supply circuit, wherein pixels are arranged in a matrix in the display section. In addition to display elements (also called display devices), first transistors and second transistors are disposed within each pixel. The first transistor may be a transistor in which a first semiconductor layer is disposed inside an opening formed in an interlayer insulating layer on a substrate, and the second transistor may be a transistor in which a second semiconductor layer is disposed inside an opening formed in an interlayer insulating layer on the substrate, different from the aforementioned opening. By adopting this structure, the channel length direction of the transistor can be along the side of the interlayer insulating layer of the opening. Therefore, the channel length is not affected by the performance of the exposure apparatus used to manufacture the transistor, and thus the channel length can be set to be smaller than the limiting resolution of the exposure apparatus.

[0038] Here, a first conductive layer disposed below the opening is used as one of the source and drain electrodes of the first transistor. Specifically, an interlayer insulating layer is disposed on the first conductive layer, and an opening is formed in the interlayer insulating layer in such a way that it reaches the first conductive layer. Furthermore, a first semiconductor layer is disposed inside the opening in such a way that it has a region in contact with the first conductive layer. In addition, a second conductive layer is used as the other of the source and drain electrodes of the first transistor, which surrounds the outer periphery of the opening when viewed in plan view. Furthermore, a gate insulating layer is disposed on the first semiconductor layer and the second conductive layer, and a third conductive layer serving as the gate electrode of the first transistor is disposed on the gate insulating layer.

[0039] In this specification and other materials, a plan view may sometimes be referred to as a top view. Additionally, a plan view may sometimes be referred to as a top view.

[0040] The second transistor can adopt the same structure as the first transistor. One of the source and drain electrodes of the second transistor is a fourth conductive layer disposed below the opening. The other of the source and drain electrodes of the second transistor is a fifth conductive layer that surrounds the outer periphery of the opening when viewed from the plane. Furthermore, the aforementioned gate insulating layer is also disposed on the second semiconductor layer and the fifth conductive layer, and a sixth conductive layer serving as the gate electrode of the second transistor is disposed on the gate insulating layer.

[0041] The first or second conductive layer is electrically connected to the signal line driving circuit. The third conductive layer has a region extending in the row direction and is electrically connected to the scan line driving circuit. The fourth conductive layer has a region extending in the column direction and is electrically connected to the power supply circuit. Because the third conductive layer has a region extending in the row direction and the fourth conductive layer has a region extending in the column direction, the third and fourth conductive layers have overlapping regions.

[0042] In one embodiment of the display device of the present invention, in the region where the third conductive layer and the fourth conductive layer overlap, an interlayer insulating layer is disposed on the fourth conductive layer, the aforementioned gate insulating layer is disposed on the interlayer insulating layer, and the third conductive layer is disposed thereon. Therefore, for example, compared to the case where only the gate insulating layer is disposed between the third and fourth conductive layers, the parasitic capacitance formed by the third and fourth conductive layers is reduced. Therefore, the time from when the scan line driving circuit outputs a signal to the third conductive layer to when that signal is supplied to the pixel can be shortened. This allows the display device to be driven at high speed.

[0043] <Example of a display device structure> Figure 1A This is a block diagram illustrating a structural example of a display device 10, which is a display device according to one aspect of the present invention. The display device 10 includes a display unit 20, a scan line driving circuit 11, a signal line driving circuit 13, and a power supply circuit 15. The display unit 20 includes a plurality of pixels 21 arranged in a matrix.

[0044] The scan line drive circuit 11 is electrically connected to the pixel 21 via wiring 41. Wiring 41 extends, for example, in the row direction of the matrix described above.

[0045] The signal line driving circuit 13 is electrically connected to the pixel 21 via wiring 43. Wiring 43 extends, for example, in the column direction of the matrix described above.

[0046] The power supply circuit 15 is electrically connected to the pixel 21 via wiring 45. For example, all pixels 21 can be electrically connected to the power supply circuit 15 via the same wiring 45.

[0047] Pixel 21 includes a display element that can display an image on display unit 20. As a display element, for example, a light-emitting element can be used; specifically, an organic EL element can be used. Alternatively, a liquid crystal element (also called a liquid crystal device) can also be used as a display element.

[0048] The scan line driving circuit 11, for example, has the function of selecting pixels 21 for writing image data row by row. Specifically, the scan line driving circuit 11 can select pixels 21 for writing image data by outputting signals to the wiring 41. Here, the scan line driving circuit 11 outputs the above signal to the wiring 41 of the first row, then to the wiring 41 of the second row, and then sequentially to the wiring 41 of the last row, thereby selecting all pixels 21. Thus, the signal output by the scan line driving circuit 11 to the wiring 41 is a scan signal, and the wiring 41 can be considered a scan line.

[0049] The signal line driving circuit 13 has the function of generating image data. The image data is supplied to the pixels 21 through wiring 43. For example, image data can be written to all pixels 21 included in the row selected by the scan line driving circuit 11. Here, the image data can be represented as a signal (image signal). Thus, wiring 43 can be considered a signal line.

[0050] The power supply circuit 15 has the function of generating a power supply potential and supplying it to the wiring 45. For example, the power supply circuit 15 has the function of generating a high power supply potential (hereinafter simply referred to as "high potential" or "VDD") and supplying it to the wiring 45. Furthermore, the power supply circuit 15 may also have the function of generating a low power supply potential (hereinafter simply referred to as "low potential" or "VSS"). The wiring 45 is supplied with a power supply potential, thus the wiring 45 can be considered a power line.

[0051] Figure 1B This is a plan view showing an example of the structure of pixel 21. Pixel 21 includes multiple sub-pixels 23. Figure 1B An example is shown where pixel 21 includes sub-pixels 23R, 23G, and 23B. Here, if pixel 21 is a display element including a light-emitting element, for example... Figure 1B The planar shape of the sub-pixel shown corresponds to the planar shape of the light-emitting area of ​​the light-emitting element. Note that in Figure 1B In this invention, the aperture ratios (or sizes, or sizes of the light-emitting areas) of sub-pixels 23R, 23G, and 23B are equal or substantially equal, but one aspect of the invention is not limited to this. The aperture ratios of sub-pixels 23R, 23G, and 23B can be suitably determined. The aperture ratios of sub-pixels 23R, 23G, and 23B can be different from each other, and two or more of them can be equal or substantially equal.

[0052] In this specification, for example, when describing the common content among subpixels 23R, 23G, and 23B, the letters distinguishing them are sometimes omitted and they are referred to simply as subpixel 23. When describing the common content among other constituent elements distinguished by letters, symbols with omitted letters are sometimes used.

[0053] exist Figure 1B In the pixel 21 shown, the sub-pixels 23 are arranged in a stripe pattern. Alternatively, the sub-pixels 23 can be arranged in an S-stripe pattern, matrix pattern, Delta pattern, Bayer pattern, or Pentile pattern, etc. An example of the planar shape of the sub-pixels and the arrangement of the sub-pixels can be found in Embodiment 2.

[0054] Subpixels 23R, 23G, and 23B emit light of different colors. Examples of subpixels 23R, 23G, and 23B include subpixels of three colors (R, G, and B) and three colors (Y, C, and M). Furthermore, more than four subpixels 23 can be provided in pixel 21. For example, subpixels of four colors (R, G, B, and white (W)) can be provided in pixel 21. Thus, by including multiple subpixels 23 emitting different colors of light in pixel 21, the display device 10 can display a full-color image on the display unit 20. Additionally, subpixels of R, G, B, and infrared (IR) light can also be provided in pixel 21.

[0055] Alternatively, the display unit 20 may also be equipped with a sensor, for example, a sensor may be provided in the pixel 21. For example, the display unit 20 may also have the function of a fingerprint sensor. For example, the display unit 20 may also have the function of an optical or ultrasonic fingerprint sensor.

[0056] Figure 1C This is a circuit diagram showing an example of the structure of sub-pixel 23. Figure 1C The sub-pixel 23 shown includes pixel circuit 40A and light-emitting element 60.

[0057] Pixel circuit 40A includes transistor 51, transistor 52, and capacitor 57. That is to say, pixel circuit 40A is a 2Tr1C type pixel circuit.

[0058] In pixel circuit 40A, one of the source and drain of transistor 51 is electrically connected to wiring 43. The other of the source and drain of transistor 51 is electrically connected to the gate of transistor 52. The gate of transistor 52 is electrically connected to one electrode of capacitor 57. The gate of transistor 51 is electrically connected to wiring 41.

[0059] One of the source and drain terminals of transistor 52 is electrically connected to wiring 45. The other of the source and drain terminals of transistor 52 is electrically connected to another electrode of capacitor 57. The other electrode of capacitor 57 is electrically connected to one electrode of light-emitting element 60. The other electrode of light-emitting element 60 is electrically connected to wiring 47. Here, one electrode of light-emitting element 60 is referred to as the pixel electrode. Additionally, since wiring 47 can be shared among all sub-pixels 23, for example, the other electrode of light-emitting element 60 can be referred to as the common electrode.

[0060] As described above, wiring 41 is used as a scan line, wiring 43 is used as a signal line, and wiring 45 is used as a power line. Additionally, wiring 47 is used as a power line, for example, when wiring 45 is supplied with a high power supply potential, wiring 47 is supplied with a low power supply potential. Wiring 47 can, for example, be electrically connected to the power supply circuit 15.

[0061] Transistor 51 is used as a switch and is also called a selection transistor. Transistor 51 has the function of controlling the conduction state and non-conduction state between the gate of wiring 43 and transistor 52 according to the potential of wiring 41. When transistor 51 is in the on state, image data is written to pixel circuit 40A, and when transistor 51 is in the off state, the written image data is retained.

[0062] Transistor 52, also known as a driving transistor, controls the amount of current flowing through the light-emitting element 60. Capacitor 57 maintains the gate potential of transistor 52. The brightness of the light-emitting element 60 is controlled based on the potential supplied to the gate of transistor 52 corresponding to the image data. Specifically, when wiring 45 is supplied with a high power supply potential and wiring 47 is supplied with a low power supply potential, the magnitude of the current flowing from wiring 45 to wiring 47 is controlled according to the gate potential of transistor 52, thereby controlling the brightness of the light-emitting element 60.

[0063] OS transistors are preferably used as transistors 51 and 52. For example, OS transistors have higher field-effect mobility than transistors using amorphous silicon. Therefore, by using OS transistors as transistors 51 and 52, the display device 10 can be driven at high speed.

[0064] Furthermore, the source-drain leakage current (also known as off-state current) of the OS transistor in its off-state state is significantly small. Therefore, by using the OS transistor as transistor 51, the charge stored in capacitor 57 can be maintained for a longer period. Consequently, image data written to sub-pixel 23 can be retained for an extended period, reducing the frequency of refresh operations (writing image data to sub-pixel 23 again). This, in turn, reduces the power consumption of the display device 10.

[0065] To increase the brightness of the light-emitting element 60, it is necessary to increase the current flowing through it. This requires increasing the source-drain voltage of the driving transistor 52. Because the source-drain breakdown voltage of an OS transistor is higher than that of a silicon transistor (also known as a Si transistor), a higher voltage can be applied between its source and drain. Therefore, by using an OS transistor as transistor 52, the current flowing through the light-emitting element 60 can be increased, thereby increasing its brightness.

[0066] When the transistor is driven in the saturation region, the OS transistor allows for a smaller change in the source-drain current in response to changes in the gate-source voltage, compared to a Si transistor. Therefore, by using an OS transistor as transistor 52, the current flowing through the source-drain can be determined precisely based on the change in the gate-source voltage. This allows for precise control of the amount of current flowing through the light-emitting element 60. Consequently, the brightness of the light emitted by the sub-pixel 23 can be precisely controlled. This, in turn, increases the number of grayscale values ​​that the sub-pixel 23 can display.

[0067] Regarding the saturation characteristics of the current flowing through a transistor when driven in the saturation region, compared to a Si transistor, an OS transistor can maintain a stable current (saturation current) even when the source-drain voltage is gradually increased. Therefore, by using an OS transistor as transistor 52, even if the current-voltage characteristics of the light-emitting element 60 are non-uniform for each light-emitting element 60, a stable current can still flow through the light-emitting element 60. In other words, when driven in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is increased, thus stabilizing the brightness of the light-emitting element 60.

[0068] As described above, by using the OS transistor as transistor 52, it is possible to achieve "suppression of black blur", "increase in light emission brightness", "multi-grayscale conversion" and "suppression of light emission brightness of light emission element 60 non-uniformly per light emission element 60".

[0069] Note that in Figure 1C Transistors 51 and 52 are n-channel transistors, but one or both of transistors 51 and 52 may also be p-channel transistors. The same applies to other transistors shown in this specification.

[0070] As the light-emitting element 60, OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) are preferably used, for example. Examples of light-emitting materials contained in the light-emitting element 60 include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (e.g., quantum dot materials). Furthermore, LEDs such as micro-LEDs (Light Emitting Diodes) can also be used as the light-emitting element 60.

[0071] Figure 1DThis is a circuit diagram showing an example of the structure of sub-pixel 23. Figure 1D The sub-pixel 23 shown includes pixel circuit 40B and liquid crystal element 69.

[0072] The pixel circuit 40B includes a transistor 51 and a capacitor 57. That is to say, the pixel circuit 40B is a 1Tr1C type pixel circuit.

[0073] In pixel circuit 40B, one of the source and drain of transistor 51 is electrically connected to wiring 43. The other of the source and drain of transistor 51 is electrically connected to one electrode of capacitor 57. One electrode of capacitor 57 is electrically connected to one electrode of liquid crystal element 69. The gate of transistor 51 is electrically connected to wiring 41. The other electrode of capacitor 57 and the other electrode of liquid crystal element 69 are electrically connected to wiring 45. Here, one electrode of liquid crystal element 69 is also referred to as the pixel electrode. Alternatively, the other electrode of liquid crystal element 69 is sometimes referred to as the common electrode. Additionally, in pixel circuit 40B, wiring 45 is supplied with a ground potential.

[0074] In pixel circuit 40B, transistor 51 is used as a switch, which controls the conduction and non-conductivity states between wiring 43 and one electrode of liquid crystal element 69 according to the potential of wiring 41. When transistor 51 is in the on state, image data is written to pixel circuit 40B, and when transistor 51 is in the off state, the written image data is retained.

[0075] Capacitor 57 has the function of maintaining the potential of one electrode of liquid crystal element 69. The orientation state of liquid crystal element 69 is controlled according to the potential corresponding to image data supplied to one electrode of liquid crystal element 69.

[0076] The liquid crystal element 69 can be configured in the following modes, for example: TN (Twisted Nematic) mode; STN (Super-Twisted Nematic) mode; VA (Vertical Alignment) mode; ASM (Axially Symmetric Aligned Micro-cell) mode; OCB (Optically Compensated Birefringence) mode; FLC (Ferroelectric Liquid Crystal) mode; AFLC (Anti-Ferroelectric Liquid Crystal) mode; MVA (Multidomain Vertical Alignment) mode; PVA (Patterned Vertical Alignment) mode; IPS (In Plane Switching) mode; FFS (Fringe Field Switching) mode; or TBA (Transverse Bend Alignment) mode, etc. Other examples include ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and guest-host mode. Note that this is not a limitation; various modes can be used.

[0077] Figure 2A This is a block diagram showing an example of the structure of the display device 10, and it is also... Figure 1A A modified example of the display device 10 shown. Figure 2A The display device 10 shown and Figure 1A The difference in the display device 10 shown is that: the wiring 41 includes wiring 41a and wiring 41b; and a reference potential generation circuit 17 is provided.

[0078] The reference potential generation circuit 17 is electrically connected to the pixel 21 via wiring 48. For example, all pixels 21 can be electrically connected to the reference potential generation circuit 17 via the same wiring 48. For example, the reference potential generation circuit 17 has the function of generating a non-uniform reference potential for correcting the gate-source potential of each transistor 52 and supplying it to the wiring 48. The potential of the wiring 48 becomes the reference potential, and thus the wiring 48 can be referred to as a reference potential line. In addition, the reference potential generation circuit 17 can also be referred to as a power supply circuit. Furthermore, the power supply circuit 15 and the reference potential generation circuit 17 can also be combined as a single circuit. For example, the power supply circuit 15 can also include the reference potential generation circuit 17.

[0079] Figure 2B It is shown Figure 2A The circuit diagram shows an example of the structure of sub-pixels 23 included in pixel 21. Figure 2B The sub-pixel 23 shown includes a pixel circuit 40C and a light-emitting element 60. The pixel circuit 40C has a structure that adds a transistor 53 to the pixel circuit 40A. The pixel circuit 40C is a 3Tr1C type pixel circuit.

[0080] In pixel circuit 40C, the gate of transistor 51 is electrically connected to wiring 41a. One of the source and drain of transistor 53 is electrically connected to the other of the source and drain of transistor 52, the other electrode of capacitor 57, and one electrode of light-emitting element 60. The other of the source and drain of transistor 53 is electrically connected to wiring 48. The gate of transistor 53 is electrically connected to wiring 41b.

[0081] Transistor 53 is used as a switch, which controls the conduction and non-conductivity states between wiring 48 and one electrode of the light-emitting element 60 according to the potential of wiring 41b. Wiring 48 is supplied with a reference potential, for example. Based on the reference potential of wiring 48 supplied through transistor 53, the non-uniformity of the gate-source potential of each transistor 52 can be suppressed.

[0082] Furthermore, the current value of the wiring 48 can be used to set the pixel parameters. More specifically, the wiring 48 can be used as a monitoring line to output the current flowing through the transistor 52 or the light-emitting element 60 to the outside of the pixel 21. The current output to the wiring 48 can be converted into a potential by a source follower circuit, for example, or converted into a digital signal by an AD converter, for example. Note that when the wiring 48 is used as a monitoring line, the display device 10 does not need to include a reference potential generation circuit 17. In addition, when the wiring 48 is used as a monitoring line, the pixel 21 can be electrically connected to different wirings 48 in columns.

[0083] As transistor 53, an OS transistor is preferably used. As mentioned above, for example, OS transistors have higher field-effect mobility compared to transistors using amorphous silicon. Therefore, by using an OS transistor as transistor 53, the display device 10 can be driven at high speed.

[0084] Figure 3A , Figure 3B and Figure 3C It is shown Figure 2A The circuit diagram shows an example of the structure of sub-pixels 23 included in pixel 21. Figure 3A The sub-pixel 23 shown includes a pixel circuit 40D and a light-emitting element 60. The pixel circuit 40D has a structure that adds a transistor 54 and a capacitor 58 to the pixel circuit 40C. The pixel circuit 40D is a 4Tr2C type pixel circuit.

[0085] In pixel circuit 40D, one of the source and drain of transistor 52 is electrically connected to one of the source and drain of transistor 54. The other of the source and drain of transistor 54 is electrically connected to wiring 45. The gate of transistor 54 is electrically connected to wiring 41c. One electrode of capacitor 58 is electrically connected to the other of the source and drain of transistor 52, one of the source and drain of transistor 53, the other electrode of capacitor 57, and one electrode of light-emitting element 60.

[0086] Wiring 41c is electrically connected to the scan line drive circuit 11. That is, in the sub-pixel 23 included by pixel 21, Figure 3A In the structure shown, wiring 41a, wiring 41b and wiring 41c are provided as wiring 41 in the display device 10.

[0087] Transistor 54 is used as a switch, which has the function of controlling the on and off states between wiring 45 and one of the source and drain of transistor 52 according to the potential of wiring 41c.

[0088] When transistor 54 is turned on, a current corresponding to the gate potential of transistor 52 flows, for example, from wiring 45 to wiring 47. As a result, light-emitting element 60 emits light with a brightness corresponding to the gate potential of transistor 52. Conversely, when transistor 54 is turned off, no current flows through light-emitting element 60, thereby preventing light emission from occurring.

[0089] As transistor 54, an OS transistor is preferably used. As mentioned above, for example, OS transistors have higher field-effect mobility compared to transistors using amorphous silicon. Therefore, by using an OS transistor as transistor 54, the display device 10 can be driven at high speed.

[0090] Figure 3BThe sub-pixel 23 shown includes a pixel circuit 40E and a light-emitting element 60. The pixel circuit 40E has a structure in which a transistor 54 is added to the pixel circuit 40C. The pixel circuit 40E is a 4Tr1C type pixel circuit.

[0091] In pixel circuit 40E, one of the source and drain of transistor 54 is electrically connected to the other of the source and drain of transistor 51, the gate of transistor 52, and one electrode of capacitor 57. The other of the source and drain of transistor 54 is electrically connected to wiring 49. The gate of transistor 54 is electrically connected to wiring 41c. In sub-pixel 23... Figure 3B In the structure shown, wiring 41a, wiring 41b and wiring 41c are provided as wiring 41 in the display device 10.

[0092] When transistor 54 is turned on, the gate potential of transistor 52 can be the potential of wiring 49. Here, wiring 49 can be supplied with a low potential, for example. As described above, for example, no current flows through the light-emitting element 60, so the light-emitting element 60 does not emit light.

[0093] Figure 3C The sub-pixel 23 shown includes a pixel circuit 40F and a light-emitting element 60.

[0094] Pixel circuit 40F includes transistors 61, 62, 63, 64, 65, and 66, as well as capacitors 67 and 68. In other words, pixel circuit 40F is a 6Tr2C type pixel circuit.

[0095] In pixel circuit 40F, one of the source and drain of transistor 61 is electrically connected to wiring 45. The other of the source and drain of transistor 61 is electrically connected to one of the source and drain of transistor 62. One of the source and drain of transistor 62 is electrically connected to one of the source and drain of transistor 63. The gate of transistor 61 is electrically connected to wiring 41d.

[0096] The other of the source and drain of transistor 62 is electrically connected to the gate of transistor 63. The gate of transistor 63 is electrically connected to one electrode of capacitor 67. The gate of transistor 62 is electrically connected to wiring 41e.

[0097] One of the source and drain of transistor 64 is electrically connected to wiring 43. The other of the source and drain of transistor 64 is electrically connected to the other of the source and drain of transistor 63. The other of the source and drain of transistor 63 is electrically connected to one of the source and drain of transistor 65. The gate of transistor 64 is electrically connected to wiring 41f.

[0098] One of the source and drain terminals of transistor 65 is electrically connected to one of the source and drain terminals of transistor 66. One of the source and drain terminals of transistor 66 is electrically connected to the other electrode of capacitor 67. The other electrode of capacitor 67 is electrically connected to one electrode of capacitor 68. One electrode of capacitor 68 is electrically connected to one electrode of light-emitting element 60. The gate of transistor 65 is electrically connected to wiring 41g.

[0099] The other of the source and drain of transistor 66 is electrically connected to wiring 48. The gate of transistor 66 is electrically connected to wiring 41e.

[0100] The other electrode of capacitor 68 is electrically connected to wiring 41f. The other electrode of light-emitting element 60 is electrically connected to wiring 47.

[0101] Wiring 41d, wiring 41e, wiring 41f, and wiring 41g are electrically connected to the scan line drive circuit 11. That is, when the sub-pixel 23 included in pixel 21 has... Figure 3C In the structure shown, wiring 41d, wiring 41e, wiring 41f and wiring 41g are provided as wiring 41 in the display device 10.

[0102] Transistors 61, 62, 64, 65, and 66 are used as switches. Transistor 61 has the function of controlling the conduction and non-conductivity states between wiring 45 and one of the source and drain of transistor 62, and between the source and drain of transistor 63, according to the potential of wiring 41d. Transistor 62 has the function of controlling the conduction and non-conductivity states between the other of the source and drain of transistor 61, and between the source and drain of transistor 63 and the gate of transistor 63 and one electrode of capacitor 67, according to the potential of wiring 41e. Transistor 64 has the function of controlling the conduction and non-conductivity states between wiring 43 and one of the source and drain of transistor 63, and between the source and drain of transistor 65, according to the potential of wiring 41f. Transistor 65 has the function of controlling the conduction and non-conductivity states between the other of the source and drain of transistor 63, and between the other of the source and drain of transistor 64 and one electrode of light-emitting element 60, according to the potential of wiring 41g. Transistor 66 has the function of controlling the conduction and non-conductivity states between wiring 48 and one electrode of light-emitting element 60 according to the potential of wiring 41e.

[0103] Transistors 61 to 66 are preferably OS transistors. For example, OS transistors have higher field-effect mobility than transistors using amorphous silicon. Therefore, by using OS transistors as transistors 61 to 66, the display device 10 can be driven at high speed.

[0104] <Example 1 of semiconductor device structure> Figure 4A1 This is a plan view illustrating a structural example of a semiconductor device included in a display device according to one aspect of the present invention, specifically a plan view illustrating a structural example of a transistor 50 and its surrounding structure included in a display device according to one aspect of the present invention. Figure 4B yes Figure 4A1 The cross-sectional view shown is the dotted-dotted line A1-A2. Note that in... Figure 4A1 In the diagram, for example, some components of transistor 50, such as insulating layers, are omitted. Regarding the plan view of the transistor, the following figures also omit some components such as insulating layers.

[0105] For example, transistor 50 can be used as a transistor included in pixel 21. For example, transistor 50 can be used as transistors 51 to 54 and transistors 61 to 66. In addition, transistor 50 can also be used as at least a portion of the transistors included in scan line drive circuit 11, signal line drive circuit 13, power supply circuit 15, and reference potential generation circuit 17.

[0106] Transistor 50 is disposed on substrate 101. Transistor 50 includes conductive layer 111, conductive layer 112, semiconductor layer 113, insulating layer 105, and conductive layer 115. Figure 4A1 An example is shown where conductive layer 112 extends in a direction parallel to conductive layer 111 and in a direction perpendicular to conductive layer 115.

[0107] exist Figure 4A1 and Figure 4B In the diagram, as shown on the coordinate axes, the extension direction of the conductive layer 112 is the X direction. Additionally, the direction perpendicular to the X direction and, for example, parallel to the top surface of the substrate 101 is the Y direction, and the direction perpendicular to the top surface of the substrate 101 is the Z direction. In the following figures, the definitions of the X, Y, and Z directions may sometimes be the same and sometimes different. The X, Y, and Z directions can be mutually perpendicular.

[0108] Conductive layer 111 is used as one of the source and drain electrodes of transistor 50. Conductive layer 112 is used as the other of the source and drain electrodes of transistor 50. Insulating layer 105 is used as the gate insulating layer of transistor 50. Conductive layer 115 is used as the gate electrode of transistor 50.

[0109] In semiconductor layer 113, the entire area between the source electrode and the drain electrode, where the gate insulating layer overlaps with the gate electrode, is used as the channel formation region. Furthermore, in semiconductor layer 113, the region in contact with the source electrode is used as the source region, and the region in contact with the drain electrode is used as the drain region.

[0110] A conductive layer 111 is disposed on a substrate 101, an insulating layer 103 is disposed on the substrate 101 and the conductive layer 111, and a conductive layer 112 is disposed on the insulating layer 103. The insulating layer 103 can be used as an interlayer insulating layer. The conductive layers 111 and 112 have regions that overlap each other through the insulating layer 103. The thickness of the insulating layer 103 used as an interlayer insulating layer can be thicker than the thickness of the insulating layer 105 used as the gate insulating layer of the transistor 50.

[0111] The insulating layer 103 includes an opening 121 leading to the conductive layer 111. The conductive layer 112 includes an opening 123 leading to the opening 121. That is, the opening 123 has a region that overlaps with the opening 121.

[0112] Figure 4A1 The conductive layer 111, conductive layer 112, semiconductor layer 113, conductive layer 115, opening 121, and opening 123 are shown as components of transistor 50. Here, Figure 4A2 It was omitted. Figure 4A1 The diagram shows a structural example of the conductive layer 115 among the constituent elements. That is, Figure 4A2 The diagram shows conductive layer 111, conductive layer 112, semiconductor layer 113, opening 121, and opening 123. Additionally, Figure 4A3 It was omitted. Figure 4A2 The diagram shows a structural example of the semiconductor layer 113 among the constituent elements. That is, Figure 4A3 The conductive layer 111, conductive layer 112, opening 121, and opening 123 are shown.

[0113] like Figure 4A3 and Figure 4B As shown, conductive layer 112 includes an opening 123 in the region overlapping with conductive layer 111. For example... Figure 4A3 As shown, the conductive layer 112 may have a structure that covers the entire outer periphery of the opening 121 when viewed from a planar perspective. Preferably, the conductive layer 112 is not disposed inside the opening 121. That is, the conductive layer 112 preferably does not contact the side surface of the insulating layer 103 on the side of the opening 121.

[0114] Figure 4A1 , Figure 4A2 and Figure 4A3 An example is shown where both openings 121 and 123 are circular when viewed from a planar perspective. By making the planar shapes of openings 121 and 123 circular, the machining accuracy during their formation can be improved, allowing for the formation of finer openings 121 and 123. Note that in this specification, the circular shape is not limited to a perfect circle. Furthermore, the planar shapes of openings 121 and 123 may also be elliptical, for example.

[0115] Figure 4BAn example is shown where the end of the conductive layer 112 on the opening 123 side coincides with or substantially coincides with the end of the insulating layer 103 on the opening 121 side. The planar shape of the opening 123 can also be described as coinciding with or substantially coinciding with the planar shape of the opening 121. Note that in this specification, the end of the conductive layer 112 on the opening 123 side and the end of the opening 123 refer to the bottom surface end of the conductive layer 112 on the opening 123 side. The bottom surface of the conductive layer 112 refers to the surface on the insulating layer 103 side. The end of the insulating layer 103 on the opening 121 side and the end of the opening 121 refer to the top surface end of the insulating layer 103 on the opening 121 side. The top surface of the insulating layer 103 refers to the surface on the conductive layer 112 side. Furthermore, the planar shape of the opening 123 refers to the planar shape of the bottom surface end of the conductive layer 112 on the opening 123 side. The planar shape of the opening 121 refers to the planar shape of the top surface end of the insulating layer 103 on the opening 121 side.

[0116] Note that end alignment or approximate alignment can also be described as end-alignment or approximate alignment. In cases of end-alignment or approximate alignment, and in cases of consistent or approximate planar shapes, it can be said that, when viewed from a plane, at least a portion of the outline overlaps with each other between the stacked layers. For example, this includes cases where the upper and lower layers are processed from the same mask pattern or a portion thereof. However, strictly speaking, sometimes the outlines do not overlap and the upper layer is inside or outside the lower layer; in such cases, it can also be said that the ends are approximate or the planar shapes are approximate.

[0117] The opening 121 can be formed, for example, using a photoresist mask used to form the opening 123. Specifically, first, a conductive layer 111 is formed on a substrate 101. Then, an insulating layer 103, a conductive film on the insulating layer 103 that will become a conductive layer 112 in a later process, and a photoresist mask on the conductive film are formed on the substrate 101 and the conductive layer 111. The opening 123 is formed in the conductive film using the photoresist mask, and then the opening 121 is formed in the insulating layer 103 using the photoresist mask, thereby allowing the end of the opening 121 to coincide with or substantially coincide with the end of the opening 123. This structure simplifies the process.

[0118] Semiconductor layer 113 is disposed such that it covers openings 121 and 123 and has regions located inside openings 121 and 123. Semiconductor layer 113 has a shape along the top and side surfaces of conductive layer 112, the side surface of insulating layer 103, and the top surface of conductive layer 111. Semiconductor layer 113, for example, has regions that contact the top and side surfaces of conductive layer 112, the side surface of insulating layer 103, and the top surface of conductive layer 111.

[0119] The semiconductor layer 113 preferably covers the end of the conductive layer 112 on one side of the opening 123. For example, Figure 4B This illustrates a structure where the end of the semiconductor layer 113 is located on the conductive layer 112. Alternatively, the end of the semiconductor layer 113 can be described as being in contact with the top surface of the conductive layer 112.

[0120] For example, in Figure 4B In this embodiment, semiconductor layer 113 has a single-layer structure, but this is not the only aspect of the invention. Semiconductor layer 113 may also have a stacked structure of two or more layers.

[0121] An insulating layer 105, serving as the gate insulating layer of transistor 50, is disposed such that it covers openings 121 and 123 and has regions located inside openings 121 and 123. The insulating layer 105 is disposed on semiconductor layer 113, conductive layer 112, and insulating layer 103. The insulating layer 105 may have regions that contact the top and side surfaces of semiconductor layer 113, conductive layer 112, and insulating layer 103. The insulating layer 105 has a shape that extends along the top and side surfaces of insulating layer 103, conductive layer 112, and semiconductor layer 113.

[0122] A conductive layer 115, serving as the gate electrode of transistor 50, is disposed on insulating layer 105 and may have a region that contacts the top surface of insulating layer 105. The conductive layer 115 has a region that overlaps with semiconductor layer 113 across insulating layer 105.

[0123] For example, such as Figure 4B As shown, the conductive layer 115 is disposed in such a manner that it has a region located inside the opening 121 and a region located inside the opening 123, and has a region sandwiching the insulating layer 105 and the semiconductor layer 113 opposite each other. Furthermore, in Figure 4B In the example shown, conductive layer 115 has a region overlapping conductive layers 111 and 112, separated by insulating layer 105 and semiconductor layer 113. Furthermore, conductive layer 115 covers the entire semiconductor layer 113. By employing this structure, a gate electric field can be applied to the entire semiconductor layer 113, thereby improving the electrical characteristics of transistor 50, for example, increasing the transistor's on-state current. Additionally, by providing an insulating layer 103 between conductive layers 111 and 115, in addition to the insulating layer 105 serving as a gate insulating layer, the parasitic capacitance formed by conductive layers 111 and 115 is reduced, for example, compared to the case where only insulating layer 103 is provided between conductive layers 111 and 115.

[0124] Transistor 50 is a so-called top-gate transistor with a gate electrode above semiconductor layer 113. Furthermore, since the bottom surface of semiconductor layer 113 has a region that contacts the source electrode and the drain electrode, it can be described as a TGBC (Top Gate Bottom Contact) transistor.

[0125] Here, refer to Figure 5A and Figure 5B Explain the channel length and channel width of transistor 50. Figure 5A It is shown Figure 4A1 An enlarged plan view of the transistor 50 and its surrounding structure. Figure 5B yes Figure 5A The cross-sectional view of the dotted line A1-A2 shown.

[0126] In the semiconductor layer 113, the region in contact with the conductive layer 111 is used as one of the source region and the drain region, the region in contact with the conductive layer 112 is used as the other of the source region and the drain region, and the region between the source region and the drain region is used as the channel formation region.

[0127] The channel length of transistor 50 is the distance between the source and drain regions. Figure 5B The double arrow in the dashed line represents the channel length L50 of transistor 50. The channel length L50, when viewed in cross-section, is the distance between the end of the region of semiconductor layer 113 that contacts conductive layer 111 and the end of the region of semiconductor layer 113 that contacts conductive layer 112.

[0128] Here, the channel length L50 of transistor 50 is equivalent to the length of the side surface of the insulating layer 103 on the side of the opening 121 when viewed from the XZ plane. That is, the channel length L50 is determined by the thickness T103 of the insulating layer 103 and the angle θ103 formed by the side surface of the insulating layer 103 on the side of the opening 121 and the surface of the insulating layer 103 to which it is formed (here, the top surface of the conductive layer 111), and is not affected by the performance of the exposure apparatus used for transistor manufacturing. Therefore, the channel length L50 can be made smaller than the limiting resolution of the exposure apparatus, enabling the realization of micro-transistors. For example, the channel length L50 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, more preferably 0.10 μm or more and less than 3.0 μm, more preferably 0.15 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.0 μm, and more preferably 0.50 μm or more and less than 1.0 μm. Figure 5B In the diagram, the thickness T103 of the insulating layer 103 is indicated by a double arrow with a dotted line.

[0129] By reducing the channel length L50, the on-state current of transistor 50 can be increased. Therefore, by using transistor 50 as a transistor included in display device 10, such as the transistor included in pixel 21, display device 10 can be driven at high speed.

[0130] The channel length L50 can be controlled by adjusting the thickness T103 and angle θ103 of the insulating layer 103.

[0131] The thickness T103 of the insulating layer 103 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, more preferably 0.10 μm or more and less than 3.0 μm, more preferably 0.15 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.0 μm, and more preferably 0.50 μm or more and less than 1.0 μm.

[0132] The side surface of the insulating layer 103 with opening 121 preferably has a tapered shape. The angle θ103 formed between the side surface of the insulating layer 103 with opening 121 and the surface of the insulating layer 103 (here, the top surface of the conductive layer 111) is preferably less than 90 degrees. By reducing the angle θ103, the coverage of the layer (e.g., semiconductor layer 113) disposed on the insulating layer 103 can be improved. However, sometimes the contact area between the semiconductor layer 113 and the conductive layer 111 becomes smaller due to the reduction of the angle θ103, thus increasing the contact resistance between the semiconductor layer 113 and the conductive layer 111. The angle θ103 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, more preferably 55 degrees or more and less than 90 degrees, more preferably 60 degrees or more and less than 90 degrees, more preferably 60 degrees or more and less than 85 degrees, more preferably 65 degrees or more and less than 85 degrees, more preferably 65 degrees or more and less than 80 degrees, and more preferably 70 degrees or more and less than 80 degrees. By setting the angle θ103 within the aforementioned range, the coverage of the layers (e.g., semiconductor layer 113) formed on the conductive layer 111 and the insulating layer 103 can be improved while shortening the channel length of the transistor 50, thereby suppressing defects such as breaks or voids in the layers. Furthermore, the contact resistance between the semiconductor layer 113 and the conductive layer 111 can be reduced.

[0133] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected or broken due to the shape of the surface on which it is formed (e.g., a step).

[0134] Note, for example, in Figure 5B The diagram shows a structure in which the shape of the side surface of the insulating layer 103 on the side of the opening 121 is straight when viewed in cross-section, but one aspect of the invention is not limited to this. The shape of the side surface of the insulating layer 103 on the side of the opening 121 when viewed in cross-section may also be curved, and may include both a region with a straight side surface and a region with a curved side surface.

[0135] The channel width of transistor 50 is the width of the source region or the width of the drain region in a direction orthogonal to the channel length direction. That is, the channel width is the width of the region where semiconductor layer 113 contacts conductive layer 111 or the width of the region where semiconductor layer 113 contacts conductive layer 112 in a direction orthogonal to the channel length direction. Here, the channel width of transistor 50 will be described as the width of the region where semiconductor layer 113 contacts conductive layer 112 in a direction orthogonal to the channel length direction. Figure 5A and Figure 5B The solid double arrow in the middle represents the channel width W50 of transistor 50. The channel width W50, when viewed from the plane, is the length of the bottom end of the conductive layer 112 on the side of opening 123.

[0136] The channel width W50 is determined by the planar shape of the opening 123. Figure 5A and Figure 5B The width D123 of the opening 123 is represented by a double-headed arrow with double dots. The width D123 refers to the shorter side of the smallest rectangle that is circumscribed by the opening 123 when viewed from a plane. When the opening 123 is formed by photolithography, the width D123 of the opening 123 is above the limit resolution of the exposure device. The width D123 is preferably 0.20 μm or more and less than 5.0 μm, more preferably 0.20 μm or more and less than 4.5 μm, more preferably 0.20 μm or more and less than 4.0 μm, more preferably 0.20 μm or more and less than 3.5 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.0 μm, and more preferably 0.50 μm or more and less than 1.0 μm. Note that when the planar shape of the opening 123 is circular, the width D123 is equivalent to the diameter of the opening 123, and the channel width W50 can be equal to the length of the outer perimeter of the opening 123 when viewed from the plane, which can be calculated as "D123×π".

[0137] <Example 1 of pixel structure> Figure 6 It is shown Figure 1C The diagram shows a structural example of the pixel circuit 40A. Figure 7 yes Figure 6 The cross-sectional view shown by the dotted line B1-B2 illustrates a structural example of transistor 51 and capacitor 57. Figure 6 The diagram shows a two-row, two-column pixel circuit 40A (pixel circuit 40A[i, j], pixel circuit 40A[i, j+1], pixel circuit 40A[i+1, j], and pixel circuit 40A[i+1, j+1]). Here, i and j are integers greater than or equal to 1. Note that a two-row, two-column pixel circuit is also shown in other planar diagrams illustrating examples of pixel circuit structures.

[0138] exist Figure 6 and Figure 7 In the example shown, the structures of transistors 51 and 52 are similar to... Figure 4A1 and Figure 4B The structure of transistor 50 shown is the same. Here, the conductive layer 111, conductive layer 112, semiconductor layer 113, and conductive layer 115 included in transistor 51 are conductive layer 111a, conductive layer 112a, semiconductor layer 113a, and conductive layer 115a, respectively. Furthermore, the conductive layer 111, conductive layer 112, semiconductor layer 113, and conductive layer 115 included in transistor 52 are conductive layer 111b, conductive layer 112b, semiconductor layer 113b, and conductive layer 115b, respectively. Moreover, the openings 121 and 123 provided in transistor 51 are opening 121a and opening 123a, respectively, and the openings 121 and 123 provided in transistor 52 are opening 121b and opening 123b, respectively.

[0139] Capacitor 57 includes a conductive layer 112b on insulating layer 103, an insulating layer 105 on conductive layer 112b, and a conductive layer 115b disposed on insulating layer 105 and having a region overlapping with conductive layer 112b. That is, the other electrode of the source and drain electrodes of transistor 52 and the other electrode of capacitor 57 can use the same conductive layer. Furthermore, the gate electrode of transistor 52 and one electrode of capacitor 57 can use the same conductive layer.

[0140] The insulating layer 105 includes an opening 125 leading to the conductive layer 112a, through which the conductive layer 112a and the conductive layer 115b are electrically connected. Specifically, for example, the conductive layer 112a and the conductive layer 115b are in contact inside the opening 125.

[0141] exist Figure 6Although the opening 125 is circular when viewed from a plane, one aspect of the invention is not limited to this and may have the same shape as the opening 121 or opening 123 described above.

[0142] At least a portion of the conductive layer 111a is used as wiring 43 with signal line function, and is Figure 1A The signal line driving circuit 13 shown is electrically connected. At least a portion of the conductive layer 111b is used as wiring 45, which functions as a power line, and is connected to... Figure 1A The power supply circuit 15 shown is electrically connected. At least a portion of the conductive layer 115a is used as wiring 41 with scan line function, and is connected to... Figure 1A The scan line drive circuit 11 shown is electrically connected.

[0143] Conductive layer 115a has a region extending in the X direction. Additionally, conductive layers 111a and 111b have regions extending in the Y direction. Conductive layer 115a has a region overlapping with conductive layer 111a and a region overlapping with conductive layer 111b. Specifically, a portion of the region of conductive layer 115a extending in the X direction overlaps with a portion of the region of conductive layer 111a extending in the Y direction. Furthermore, a portion of the region of conductive layer 115a extending in the X direction overlaps with a portion of the region of conductive layer 111b extending in the Y direction.

[0144] Here, it can be said that the region of conductive layer 115a extending in the X direction is used as wiring 41, or it can be said that the entire conductive layer 115a is used as wiring 41. Similarly, it can be said that the region of conductive layer 111a extending in the Y direction is used as wiring 43, or it can be said that the entire conductive layer 111a is used as wiring 43. Furthermore, it can be said that the region of conductive layer 111b extending in the Y direction is used as wiring 45, or it can be said that the entire conductive layer 111b is used as wiring 45. Regarding the above, unless specifically described otherwise, the same applies to other conductive layers having regions used as wiring 41, wiring 43, or wiring 45.

[0145] exist Figure 6 and Figure 7In the example shown, in the region where conductive layers 111a and 115a overlap, an insulating layer 103 is provided on conductive layer 111a, an insulating layer 105 is provided on insulating layer 103, and a conductive layer 115a is provided on insulating layer 105. Therefore, for example, compared to the case where only insulating layer 105 is provided between conductive layers 111a and 115a, the parasitic capacitance formed by conductive layers 111a and 115a is smaller. Furthermore, in the region where conductive layers 111b and 115a overlap, an insulating layer 103 is provided on conductive layer 111b, an insulating layer 105 is provided on insulating layer 103, and a conductive layer 115a is provided on insulating layer 105. Thus, for example, compared to the case where only insulating layer 105 is provided between conductive layers 111b and 115a, the parasitic capacitance formed by conductive layers 111b and 115a is smaller. This shortens the time from when the scan line drive circuit 11 outputs a signal to the conductive layer 115a to when the signal is supplied to the pixel circuit 40A. Therefore, a display device according to one aspect of the present invention can be driven at high speed.

[0146] Figure 8A Yes Figure 6 The plan view shown includes a structural example of the pixel electrode 311 of the light-emitting element 60. Figure 8B It is along Figure 8A The cross-sectional view shown by the dotted lines B3-B4 illustrates, for example, a structural example of transistor 52. Figure 8B An example structure of, for example, the layer above transistor 52 is also shown. Note that in Figure 8A in, omit Figure 6 Part of the symbol shown.

[0147] An insulating layer 218 and an insulating layer 235 are provided on the insulating layer 218 to cover transistors 51, 52, and capacitor 57. A light-emitting element 60 is provided on the insulating layer 235, and a protective layer 331 is provided to cover the light-emitting element 60. A substrate 152 is attached to the protective layer 331 by an adhesive layer 142.

[0148] The light-emitting element 60 includes a pixel electrode 311 on an insulating layer 235, an island-shaped layer 313 on the pixel electrode 311, and a common electrode 315 on the island-shaped layer 313. Layer 313 includes at least a light-emitting layer. Note that layer 313 can be considered an EL layer. Additionally, the common electrode is also referred to as a counter electrode.

[0149] In this specification, etc., "island-like" refers to two or more layers formed in the same process and using the same material that are physically separated. For example, an island-like light-emitting layer means that the light-emitting layer is physically separated from the adjacent light-emitting layer.

[0150] Insulating layers 105, 218, and 235 include an opening 129 extending to the conductive layer 112b. A pixel electrode 311 is disposed to cover the opening 129. The pixel electrode 311 has a shape along the top and side surfaces of the insulating layer 235, the side surface of the insulating layer 218, the side surface of the insulating layer 105, and the top surface of the conductive layer 112b. The pixel electrode 311, for example, has a region that contacts the top and side surfaces of the insulating layer 235, the side surface of the insulating layer 218, the side surface of the insulating layer 105, and the top surface of the conductive layer 112b. The pixel electrode 311 can be electrically connected to the conductive layer 112b inside the opening 129.

[0151] An insulating layer 237 can be provided to cover the top end of the pixel electrode 311. The insulating layer 237 is used as a partition wall (also called a dike, dam, or spacer). By providing the insulating layer 237, short circuits in the light-emitting element 60 due to contact between the pixel electrode 311 and the common electrode 315 can be prevented.

[0152] In the pixel electrode 311, a recess is formed to cover the opening 129, and an insulating layer 237 is embedded in the recess. For example, after forming the insulating layer 237 covering the top end of the pixel electrode 311 and the opening 129, a fine metal mask (FMM) can be used to form layer 313.

[0153] Note that the pixel electrode 311 may have a region overlapping with the region of the conductive layer 111a extending in the Y direction, or it may have a region overlapping with the region of the conductive layer 115a extending in the X direction. This improves the pixel aperture ratio. Conversely, by eliminating the region of the pixel electrode 311 from overlapping with either the region of the conductive layer 111a extending in the Y direction or the region of the conductive layer 115a extending in the X direction, the propagation of noise from the signal supplied to the conductive layer 111a and the signal supplied to the conductive layer 115a to the pixel electrode 311 can be suppressed.

[0154] A light-shielding layer 317 can also be provided on the side of the adhesive layer 142 of the substrate 152. The light-shielding layer 317 can be provided between adjacent light-emitting elements 60. By providing the light-shielding layer 317, light emitted from adjacent sub-pixels 23 can be blocked. This can suppress color mixing. Note that a structure without the light-shielding layer 317 can also be used.

[0155] <Example 2 of pixel structure> The following describes the structure of a part of it. Figure 6 and Figure 7 Examples of different pixel circuit structures. Note that sometimes appropriate ellipses are omitted below. Figure 6 and Figure 7 Explanation of repeated parts.

[0156] Figure 9 This is a plan view showing an example of the structure of pixel circuit 40A, illustrating an example where at least a portion of transistor 51 is disposed in the region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction. Specifically, Figure 9 An example is shown below: a semiconductor layer 113a, an opening 121a, and an opening 123a are disposed in the region where wiring 41 and wiring 43 overlap, and a semiconductor layer 113b, an opening 121b, and an opening 123b are disposed in the region where wiring 45 extends in the Y direction. Furthermore, Figure 9 An example is shown where the semiconductor layer 113a, openings 121a and 123a overlap with the regions of the conductive layer 111a extending in the Y direction and the regions of the conductive layer 115a extending in the X direction. Furthermore, Figure 9 An example is shown where the semiconductor layer 113b, opening 121b, and opening 123b overlap with the extension of the conductive layer 111b in the Y direction.

[0157] By using as pixel circuit 40A Figure 9 The structure shown is similar to that used in pixel circuit 40A. Figure 6 Compared to the structure shown, pixel miniaturization can be achieved while ensuring the area of ​​capacitor 57. On the other hand, by employing [a specific method / mechanism] as the pixel circuit 40A... Figure 6 The structure shown is similar to that used in pixel circuit 40A. Figure 9 Compared to the structure shown, this increases the flexibility in the layout of the pixel circuit 40A.

[0158] Figure 10A This is a plan view showing an example of the structure of pixel circuit 40A, in which at least a portion of conductive layer 112a is shown as an example of wiring 43 functioning as a signal line. Figure 10B yes Figure 10A The cross-sectional view shown is along the dotted lines B5-B6. Figure 10A In the example shown, conductive layer 112a has a region extending in the Y direction, a portion of which overlaps with conductive layer 115a.

[0159] exist Figure 10B In the example shown, opening 125 is provided in insulating layers 103 and 105 such that it reaches conductive layer 111a. Conductive layer 111a and conductive layer 115b are electrically connected through opening 125. Specifically, for example, conductive layer 111a and conductive layer 115b are in contact inside opening 125.

[0160] exist Figure 10AIn the example shown, wiring 43 and wiring 45 are conductive layers disposed in different layers. Therefore, compared to the case where wiring 43 and wiring 45 are conductive layers disposed in the same layer, the distance between wiring 43 and wiring 45 can be shortened. Thus, a display device according to one aspect of the present invention can be a high-definition display device. On the other hand, as... Figure 6 As shown, by using conductive layer 111a as wiring 43, and... Figure 10A Compared to the structure shown, the parasitic capacitance formed in the overlapping area of ​​wiring 41 and wiring 43 can be reduced.

[0161] Here, in Figure 10A In the example shown, the distance between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112a extending in the Y direction, viewed from the plane, can be shorter than the width of the region of conductive layer 111b extending in the Y direction and can also be shorter than the width of the region of conductive layer 112a extending in the Y direction. In other words, the length in the X direction between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112a extending in the Y direction can be shorter than the length in the X direction of the region of conductive layer 111b extending in the Y direction and can also be shorter than the length in the X direction of the region of conductive layer 112a extending in the Y direction.

[0162] In addition, Figure 10A In the example shown, the distance between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112a extending in the Y direction, viewed from the plane, can be shorter than the distance between conductive layers 111a and 111b, and can also be shorter than the distance between conductive layers 112a and 112b. For example, the distance between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112a extending in the Y direction can be shorter than the shortest distance between conductive layers 111a and 111b in the X and Y directions, and can also be shorter than the shortest distance between conductive layers 112a and 112b in the X and Y directions.

[0163] Note that in Figure 10A In the example shown, there may be a region where conductive layer 111b and conductive layer 112a overlap. In this case, the distance between conductive layer 111b and conductive layer 112a when viewed from the plane can be considered to be 0.

[0164] Figure 11 yes Figure 10A The illustrated modified example shows an example where at least a portion of transistor 51 is disposed in the region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction. Specifically, Figure 11An example is shown below: a semiconductor layer 113a, an opening 121a, and an opening 123a are disposed in the region where wiring 41 and wiring 43 overlap, and a semiconductor layer 113b, an opening 121b, and an opening 123b are disposed in the region where wiring 45 extends in the Y direction. Furthermore, Figure 11 An example is shown where the semiconductor layer 113a, openings 121a and 123a overlap with the regions of the conductive layer 112a extending in the Y direction and the regions of the conductive layer 115a extending in the X direction. Furthermore, Figure 11 An example is shown where the semiconductor layer 113b, opening 121b, and opening 123b overlap with the extension of the conductive layer 111b in the Y direction.

[0165] Figure 12A yes Figure 2B A plan view of an example of the structure of pixel circuit 40C. Figure 12B yes Figure 12A The cross-sectional view shown by the dotted lines B7-B8 illustrates a structural example of transistor 53 and capacitor 57.

[0166] exist Figure 12A and Figure 12B In the example shown, the structures of transistors 51, 52, and 53 are similar to... Figure 4A1 and Figure 4B The structure shown is the same. Here, the conductive layer 111, conductive layer 112, semiconductor layer 113, and conductive layer 115 included in transistor 53 are conductive layer 111c, conductive layer 112b, semiconductor layer 113c, and conductive layer 115c, respectively. In addition, the openings 121 and 123 provided in transistor 53 are opening 121c and opening 123c, respectively.

[0167] Conductive layer 111c is used as one of the source and drain electrodes of transistor 53, and conductive layer 112b is used as the other of the source and drain electrodes of transistor 53. Figure 12A An example is shown where another of the source and drain electrodes of transistor 52, another of the source and drain electrodes of transistor 53, and another electrode of capacitor 57 use the same conductive layer 112b.

[0168] Although Figure 12B Not shown, but the insulating layer 105 includes an opening 125a leading to the conductive layer 112a, and the conductive layer 112a is electrically connected to the conductive layer 115b through the opening 125a. Specifically, for example, the conductive layer 112a contacts the conductive layer 115b inside the opening 125a.

[0169] exist Figure 12A and Figure 12BIn the example shown, conductive layer 115a is used as wiring 41a, and at least a portion of conductive layer 115c is used as wiring 41b. Additionally, conductive layer 131 is shown as wiring 48, and conductive layer 131 is connected to... Figure 2A The reference potential generation circuit 17 shown is electrically connected.

[0170] Insulating layers 103 and 105 include an opening 125b leading to conductive layer 111c and an opening 125c leading to conductive layer 131. Conductive layer 111c is electrically connected to conductive layer 119 through opening 125b, and conductive layer 131 is electrically connected to conductive layer 119 through opening 125c. Specifically, for example, conductive layer 111c contacts conductive layer 119 inside opening 125b, and conductive layer 131 contacts conductive layer 119 inside opening 125c. As described above, conductive layer 111c and conductive layer 131 can be electrically connected through conductive layer 119. When conductive layer 111c and conductive layer 131 are electrically connected through conductive layer 119, short circuits caused by contact between conductive layer 111c and conductive layer 111b can be prevented.

[0171] Conductive layer 131 can be disposed in the same layer as conductive layer 111, and conductive layer 119 can be disposed in the same layer as conductive layer 115. Therefore, conductive layer 131 can contain the same material as conductive layer 111 and can be formed through the same process. Furthermore, conductive layer 119 can contain the same material as conductive layer 115 and can be formed through the same process. For example, conductive layers 111 and 131 can be formed by processing the same conductive film, and conductive layers 115 and 119 can be formed by processing the same conductive film.

[0172] exist Figure 12A Although the openings 125a, 125b and 125c are circular when viewed from a plane, one aspect of the invention is not limited to this and they may have the same shape as the openings 121 or 123.

[0173] Conductive layers 115a and 115c have regions extending in the X direction. Conductive layer 131 has a region extending in the Y direction. Conductive layers 115a and 115c have regions overlapping with conductive layer 111a, conductive layer 111b, and conductive layer 131. Specifically, a portion of the region of conductive layer 115a extending in the X direction overlaps with portions of the regions of conductive layers 111a, 111b, and 131 extending in the Y direction. Furthermore, a portion of the region of conductive layer 115c extending in the X direction overlaps with portions of the regions of conductive layers 111a, 111b, and 131 extending in the Y direction.

[0174] Here, it can be said that the region of conductive layer 115a extending in the X direction is used as wiring 41a, or it can be said that the entire conductive layer 115a is used as wiring 41a. Similarly, it can be said that the region of conductive layer 115c extending in the X direction is used as wiring 41b, or it can be said that the entire conductive layer 115c is used as wiring 41b. Furthermore, it can be said that the region of conductive layer 131 extending in the Y direction is used as wiring 48, or it can be said that the entire conductive layer 131 is used as wiring 48. Regarding the above, unless specifically described, other conductive layers having regions used as wiring 41a, wiring 41b, or wiring 48 are also treated similarly.

[0175] exist Figure 12A In the example shown, conductive layers 111a, 111b, and 131 have regions overlapping with conductive layer 115a, separated by insulating layers 103 and 105. Furthermore, conductive layers 111a, 111b, and 131 also have regions overlapping with conductive layer 115b, separated by insulating layers 103 and 105. Therefore, compared to the case where the insulating layer disposed between conductive layers 111a, 111b, and 131 and conductive layer 115a, and where only insulating layer 105 exists between conductive layers 111a, 111b, and 131 and conductive layer 115b, the parasitic capacitance of conductive layers 115a and 115b is reduced. This shortens the time from when the scan line driving circuit 11 outputs a signal to conductive layer 115a or conductive layer 115b to when that signal is supplied to pixel circuit 40C. Therefore, a display device according to one aspect of the present invention can be driven at high speed.

[0176] Figure 13 yes Figure 12A The illustrated modified examples show an example where at least a portion of transistor 51 is disposed in the region where wiring 41a and wiring 43 overlap. Furthermore, an example is shown where at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction. And, an example is also shown where at least a portion of transistor 53 is disposed in the region where wiring 41b and wiring 48 overlap. Specifically, Figure 13 An example is shown where a semiconductor layer 113a, an opening 121a, and an opening 123a are disposed in the region where wiring 41a and wiring 43 overlap. Additionally, Figure 13 An example is shown where a semiconductor layer 113b, an opening 121b, and an opening 123b are disposed in a region along the Y direction of the extension of wiring 45. Additionally, Figure 13 An example is shown where a semiconductor layer 113c, an opening 121c, and an opening 123c are disposed in the area where wiring 41b and wiring 48 overlap. Additionally, Figure 13An example is shown where the semiconductor layer 113a, openings 121a and 123a overlap with the regions of the conductive layer 111a extending in the Y direction and the regions of the conductive layer 115a extending in the X direction. Additionally, Figure 13 An example is shown where the semiconductor layer 113b, opening 121b, and opening 123b overlap with the extension of the conductive layer 111b in the Y direction. Furthermore, Figure 13 An example is shown where the semiconductor layer 113c, opening 121c, and opening 123c overlap with the region of the extension of the conductive layer 111c in the Y direction and the region of the extension of the conductive layer 115c in the X direction.

[0177] Figure 14A This is a plan view showing an example of the structure of pixel circuit 40C, in which a conductive layer 112c is provided, which serves as another of the source and drain electrodes of transistor 53, and at least a portion of the conductive layer 112c is used as wiring 48. Figure 14B yes Figure 14A The cross-sectional view shown is the section along the dotted-dash line B7-B8. Figure 14A In the example shown, conductive layer 112c has a region extending in the Y direction, a portion of which overlaps with conductive layers 115a and 115c.

[0178] exist Figure 14B In the example shown, an opening 125d leading to the conductive layer 111c is provided in the insulating layer 103, and the conductive layer 111c is electrically connected to the conductive layer 112b through the opening 125d. Specifically, for example, the conductive layer 111c and the conductive layer 112b are in contact inside the opening 125d.

[0179] exist Figure 14A Although the shape of the opening 125d when viewed from a plane is circular, one aspect of the invention is not limited to this and may have the same shape as the opening 121 or the opening 123.

[0180] exist Figure 14A In the example shown, wiring 48 is a conductive layer disposed in a different layer than wiring 43 and wiring 45. Therefore, compared to the case where wiring 48 is a conductive layer disposed in the same layer as wiring 43 and wiring 45, the distance between wiring 43 and wiring 48, and the distance between wiring 45 and wiring 48, can be shortened. Therefore, a display device according to one aspect of the present invention can be a high-definition display device. On the other hand, as... Figure 12A As shown, by using conductive layer 131, which is disposed in the same layer as conductive layer 111, as wiring 48, and... Figure 14A Compared to the structure shown, the parasitic capacitance formed in the region where wiring 41a and wiring 48 overlap, as well as the parasitic capacitance formed in the region where wiring 41b and wiring 48 overlap, can be reduced.

[0181] Here, in Figure 14A In the example shown, the distance between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112c extending in the Y direction, viewed from the plane, can be shorter than the width of the region of conductive layer 111b extending in the Y direction and can also be shorter than the width of the region of conductive layer 112c extending in the Y direction. In other words, the length in the X direction between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112c extending in the Y direction can be shorter than the length in the X direction of the region of conductive layer 111b extending in the Y direction and can also be shorter than the length in the X direction of the region of conductive layer 112c extending in the Y direction.

[0182] Similarly, for example, the distance between the region of conductive layer 111a extending in the Y direction and the region of conductive layer 112c extending in the Y direction, viewed from a plane, can be shorter than the width of the region of conductive layer 111a extending in the Y direction and can also be shorter than the width of the region of conductive layer 112c extending in the Y direction. In other words, the length in the X direction between the region of conductive layer 111a extending in the Y direction and the region of conductive layer 112c extending in the Y direction can be shorter than the length in the X direction of the region of conductive layer 111a extending in the Y direction and can also be shorter than the length in the X direction of the region of conductive layer 112c extending in the Y direction.

[0183] In addition, Figure 14A In the example shown, the distance between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112c extending in the Y direction, when viewed from the plane, can be shorter than the distance between conductive layers 111a and 111b, shorter than the distance between conductive layers 111b and 111c, shorter than the distance between conductive layers 112a and 112b, and shorter than the distance between conductive layers 112b and 112c. For example, the distance between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112c extending in the Y direction can be shorter than the shortest distance between conductive layers 111a and 111b in the X and Y directions, shorter than the shortest distance between conductive layers 111b and 111c in the X and Y directions, shorter than the shortest distance between conductive layers 112a and 112b in the X and Y directions, and shorter than the shortest distance between conductive layers 112b and 112c in the X and Y directions.

[0184] Similarly, for example, the distance between the region of conductive layer 111a extending in the Y direction and the region of conductive layer 112c extending in the Y direction, when viewed from the plane, can be shorter than the distance between conductive layer 111a and conductive layer 111b, shorter than the distance between conductive layer 111b and conductive layer 111c, shorter than the distance between conductive layer 112a and conductive layer 112b, and shorter than the distance between conductive layer 112b and conductive layer 112c. For example, the distance between the region of conductive layer 111a extending in the Y direction and the region of conductive layer 112c extending in the Y direction can be shorter than the shortest distance between conductive layer 111a and conductive layer 111b in the X and Y directions, shorter than the shortest distance between conductive layer 111b and conductive layer 111c in the X and Y directions, shorter than the shortest distance between conductive layer 112a and conductive layer 112b in the X and Y directions, and shorter than the shortest distance between conductive layer 112b and conductive layer 112c in the X and Y directions.

[0185] Note that in Figure 14A In the example shown, there may also be an area where conductive layer 111b and conductive layer 112c overlap. In this case, the distance between conductive layer 111b and conductive layer 112c when viewed from the plane can be considered 0. Similarly, there may also be an area where conductive layer 111a and conductive layer 112c overlap. In this case, the distance between conductive layer 111a and conductive layer 112c when viewed from the plane can be considered 0.

[0186] Figure 15A yes Figure 14A The illustrated modified example shows an example where conductive layer 112b and conductive layer 111c are electrically connected by conductive layer 119 disposed in the same layer as conductive layer 115. Figure 15B yes Figure 15A The cross-sectional view shown by the dotted lines B7-B8 illustrates a structural example of transistor 53 and capacitor 57.

[0187] exist Figure 15B In the example shown, an opening 125d1 leading to the conductive layer 112b is provided in the insulating layer 105, and the conductive layer 112b is electrically connected to the conductive layer 119 through the opening 125d1. Specifically, for example, the conductive layer 112b contacts the conductive layer 119 inside the opening 125d1. Furthermore, an opening 125d2 leading to the conductive layer 111c is provided in both the insulating layers 103 and 105, and the conductive layer 111c is electrically connected to the conductive layer 119 through the opening 125d2. Specifically, for example, the conductive layer 111c contacts the conductive layer 119 inside the opening 125d2.

[0188] As described above, conductive layer 112b and conductive layer 111c can be electrically connected through conductive layer 119. A display device according to one aspect of the present invention has this structure, where opening 125d (opening 125d1 and opening 125d2) can be formed using the same process as opening 125a.

[0189] Figure 16 yes Figure 14A The illustrated modified example shows an example where at least a portion of transistor 51 is disposed in the region where wiring 41a and wiring 43 overlap. Furthermore, an example is shown where at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction. And, an example is also shown where at least a portion of transistor 53 is disposed in the region where wiring 41b extends in the X direction. Specifically, Figure 16 An example is shown where a semiconductor layer 113a, an opening 121a, and an opening 123a are disposed in the area where wiring 41 and wiring 43 overlap. Additionally, Figure 16 An example is shown where a semiconductor layer 113b, an opening 121b, and an opening 123b are disposed in a region along the Y direction of the extension of wiring 45. Additionally, Figure 16 An example is shown where a semiconductor layer 113c, an opening 121c, and an opening 123c are disposed in a region along the X direction extending from wiring 41b. Additionally, Figure 16 An example is shown where the semiconductor layer 113a, openings 121a and 123a overlap with the regions of the conductive layer 111a extending in the Y direction and the regions of the conductive layer 115a extending in the X direction. Additionally, Figure 16 An example is shown where the semiconductor layer 113b, opening 121b, and opening 123b overlap with the extension of the conductive layer 111b in the Y direction. Additionally, Figure 16 An example is shown where the semiconductor layer 113c, opening 121c, and opening 123c overlap with the extension of the conductive layer 115c in the X direction. Furthermore, Figure 16 An example is shown where the opening 125d overlaps with the conductive layer 115b.

[0190] By using, for example, pixel circuit 40C Figure 16 The structure shown is similar to that used in pixel circuit 40C. Figure 14A Compared to the structure shown, pixel miniaturization can be achieved while ensuring the area of ​​capacitor 57. On the other hand, by employing [a specific method / mechanism] as the pixel circuit 40C... Figure 14A The structure shown is similar to that used in pixel circuit 40C. Figure 16 Compared to the structure shown, this increases the flexibility in the layout of the pixel circuit 40C.

[0191] Figure 17 , Figure 18 and Figure 19They are Figure 14A , Figure 15A and Figure 16 The diagram shows a variation of the structure, in which two adjacent columns of pixel circuits 40C share a conductive layer 112c. Figure 17 , Figure 18 and Figure 19 An example is shown where the pixel circuit 40C in column j and the pixel circuit 40C in column j+1 share the conductive layer 112c. Additionally, Figure 17 , Figure 18 and Figure 19 An example is shown where a region of conductive layer 112c extending in the Y direction is provided between the region of conductive layer 111b extending in the Y direction of transistor 52 electrically connected to the region of conductive layer 111b extending in the Y direction of transistor 52 electrically connected to the region of conductive layer 111b extending in the Y direction of pixel circuit 40C in column j+1.

[0192] exist Figure 17 , Figure 18 and Figure 19 In the example shown, with Figure 14A , Figure 15A and Figure 16 Compared to the example shown, the number of conductive layers 112c disposed in a display device according to one aspect of the present invention can be reduced, thereby enabling a high-definition display device. On the other hand, in Figure 14A , Figure 15A and Figure 16 In the example shown, with Figure 17 , Figure 18 and Figure 19 Compared to the example shown, the load on the conductive layer 112c can be reduced. Therefore, a display device with high-speed driving can be realized.

[0193] Figure 20A , Figure 20B , Figure 21A and Figure 21B They are Figure 14A , Figure 14B , Figure 15A and Figure 15B The illustrated example of a modified structure shows an example where two adjacent columns of pixel circuits 40C share a conductive layer 111b. Figure 20A and Figure 21A An example is shown where the pixel circuit 40C in column j and the pixel circuit 40C in column j+1 share the conductive layer 111b. Additionally, Figure 20A and Figure 21AAn example is shown where the region of the conductive layer 112c extending in the Y direction, which is electrically connected to the region of the conductive layer 112c extending in the Y direction of the transistor 53 disposed in the pixel circuit 40C of the j-th column, is provided between the region of the conductive layer 111b extending in the Y direction, which is electrically connected to the region of the conductive layer 112c extending in the Y direction of the transistor 53 disposed in the pixel circuit 40C of the j+1-th column.

[0194] exist Figure 20A , Figure 20B , Figure 21A and Figure 21B In the example shown, with Figure 14A , Figure 14B , Figure 15A and Figure 15B Compared to the example shown, the number of conductive layers 111b disposed in a display device according to one aspect of the present invention can be reduced, thereby enabling a high-definition display device. On the other hand, in Figure 14A , Figure 14B , Figure 15A and Figure 15B In the example shown, with Figure 20A , Figure 20B , Figure 21A and Figure 21B Compared to the example shown, the load on the conductive layer 111b can be reduced. Therefore, a display device with high-speed driving can be realized.

[0195] Figure 22A yes Figure 6 The example shown is a variation of the structure, in which an example with a conductive layer 135 is provided is shown. Figure 22A An example of the structure of pixel circuit 40A is shown. Figure 22B yes Figure 22A The cross-sectional view shown by the dotted line C1-C2 illustrates an example of the structure of transistor 52.

[0196] The conductive layer 135 has a region extending in the X direction and a region overlapping with conductive layers 111a and 111b. Furthermore, the conductive layer 135 can be disposed in the same layer as the conductive layer 112. Therefore, the conductive layer 135 can contain the same material as the conductive layer 112 and can be formed by the same process. For example, the conductive layers 112 and 135 can be formed by processing the same conductive film.

[0197] exist Figure 22B In the example shown, an opening 127 leading to the conductive layer 111b is provided in the insulating layer 103, through which the conductive layer 111b is electrically connected to the conductive layer 135. Specifically, for example, the conductive layer 111b contacts the conductive layer 135 inside the opening 127.

[0198] exist Figure 22AAlthough the shape of the opening 127 when viewed from a plane is circular, one aspect of the invention is not limited to this, and it may have the same shape as the openings 121, 123 or 125.

[0199] By means of a display device as an embodiment of the present invention Figure 22A In the structure shown, besides the conductive layer 111b having a region extending in the Y direction, the conductive layer 135 having a region extending in the X direction is also used as wiring 45 functioning as a power line. Therefore, Figure 1A The power supply circuit 15 shown can supply power potential to transistor 52 through conductive layer 111b and conductive layer 135. Therefore, the decrease in power potential generated by power supply circuit 15 before being supplied to pixel circuit 40A can be suppressed. In particular, the decrease in power potential generated by power supply circuit 15 before being supplied to pixel circuit 40A, which has a long wiring distance from power supply circuit 15, can be appropriately suppressed.

[0200] Figure 23 yes Figure 22A The illustrated modified example shows an example in which at least a portion of transistor 51 is disposed in the region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction.

[0201] Figure 24A yes Figure 12A The example shown is a variation of the structure, in which an example with a conductive layer 135 is provided is shown. Figure 24A An example of the structure of pixel circuit 40C is shown. Figure 24B yes Figure 24A The cross-sectional view shown by the dotted lines C3-C4 illustrates a structural example of transistor 53.

[0202] The conductive layer 135 has a region extending in the X direction and has a region overlapping with conductive layers 111a, 111b and 131. Furthermore, as described above, the conductive layer 135 may be disposed in the same layer as the conductive layer 112.

[0203] exist Figure 24B In the example shown, with Figure 22B Similarly, in the example shown, an opening 127 leading to the conductive layer 111b is provided in the insulating layer 103, through which the conductive layer 111b is electrically connected to the conductive layer 135. Specifically, for example, the conductive layer 111b contacts the conductive layer 135 inside the opening 127.

[0204] By means of a display device as an embodiment of the present invention Figure 24A The structure shown can suppress Figure 2AThe power supply potential generated by the power supply circuit 15 shown decreases before being supplied to the pixel circuit 40C. In particular, the decrease in the power supply potential generated by the power supply circuit 15 before being supplied to the pixel circuit 40C, which is a long wiring distance away from the power supply circuit 15, can be appropriately suppressed.

[0205] Figure 25 yes Figure 24A The illustrated modified examples show an example where at least a portion of transistor 51 is disposed in the region where wiring 41a and wiring 43 overlap. Additionally, an example is shown where at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction. Furthermore, an example is shown where at least a portion of transistor 53 is disposed in the region where wiring 41b and wiring 48 overlap.

[0206] Figure 26A yes Figure 22A The illustrated modified example shows an example in which conductive layer 111b and conductive layer 135 are electrically connected by conductive layer 137 disposed in the same layer as conductive layer 115. Figure 26A An example of the structure of pixel circuit 40A is shown. Figure 26B yes Figure 26A The cross-sectional view shown by the dotted line C1-C2 illustrates an example of the structure of transistor 52.

[0207] exist Figure 26B In the example shown, an opening 127a leading to conductive layer 111b is provided in insulating layers 103 and 105, and conductive layer 111b is electrically connected to conductive layer 137 through opening 127a. Specifically, for example, conductive layer 111b contacts conductive layer 137 inside opening 127a. Additionally, an opening 127b leading to conductive layer 135 is provided in insulating layer 105, and conductive layer 135 is electrically connected to conductive layer 137 through opening 127b. Specifically, for example, conductive layer 135 contacts conductive layer 137 inside opening 127b.

[0208] As described above, conductive layer 111b and conductive layer 135 can be electrically connected through conductive layer 137. A display device according to one aspect of the present invention has this structure, where openings 127 (openings 127a and 127b) can be formed using the same process as opening 125.

[0209] Figure 27 yes Figure 26A The illustrated modified example shows an example in which at least a portion of transistor 51 is disposed in the region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction.

[0210] Figure 28A yes Figure 24AThe illustrated modified example shows an example in which conductive layer 111b and conductive layer 135 are electrically connected by conductive layer 137 disposed in the same layer as conductive layer 115. Figure 28A An example of the structure of pixel circuit 40C is shown. Figure 28B yes Figure 28A The cross-sectional view shown by the dotted lines C3-C4 illustrates a structural example of transistor 53.

[0211] Figure 28A An example is shown in which a region of conductive layer 115c extending in the X direction is disposed between transistors 52 and 53 to prevent conductive layer 115c from contacting conductive layer 137.

[0212] Figure 29 yes Figure 28A The illustrated modified example shows an example where at least a portion of transistor 51 is disposed in the region where wiring 41a and wiring 43 overlap, at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction, and at least a portion of transistor 53 is disposed in the region where wiring 41b and wiring 48 overlap.

[0213] Figure 30A yes Figure 22A The illustrated structure is a variation of the example in which the conductive layer 135 is disposed in the same layer as the conductive layer 115. Figure 30A An example of the structure of pixel circuit 40A is shown. Figure 30B yes Figure 30A The cross-sectional view shown by the dotted line C1-C2 illustrates an example of the structure of transistor 52.

[0214] Figure 31 yes Figure 30A The illustrated modified example shows an example in which at least a portion of transistor 51 is disposed in the region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction.

[0215] Figure 32A yes Figure 30A The illustrated modified example of the structure shows an example in which at least a portion of the conductive layer 112a is used as wiring 43 having the function of a signal line. Figure 32B yes Figure 32A The cross-sectional view shown is the dotted line C1-C2.

[0216] Figure 33 yes Figure 32AThe illustrated modified example shows an example in which at least a portion of transistor 51 is disposed in the region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is disposed in the region where wiring 45 extends in the Y direction.

[0217] Figure 34A , Figure 34B , Figure 35 , Figure 36A , Figure 36B and Figure 37 They are Figure 30A , Figure 30B , Figure 31 , Figure 32A , Figure 32B and Figure 33 The illustrated modified example shows an example where conductive layer 111b and conductive layer 135 are electrically connected by conductive layer 137 disposed in the same layer as conductive layer 112.

[0218] exist Figure 34A , Figure 34B , Figure 35 , Figure 36A , Figure 36B and Figure 37 In the example shown, an opening 127a leading to conductive layer 111b is provided in insulating layer 103, and conductive layer 111b is electrically connected to conductive layer 137 through opening 127a. Specifically, for example, conductive layer 111b contacts conductive layer 137 inside opening 127a. Additionally, an opening 127b leading to conductive layer 137 is provided in insulating layer 105, and conductive layer 137 is electrically connected to conductive layer 135 through opening 127b. Specifically, for example, conductive layer 137 contacts conductive layer 135 inside opening 127b. As described above, conductive layer 111b and conductive layer 135 can be electrically connected through conductive layer 137. Note that... Figure 34A , Figure 34B , Figure 35 , Figure 36A , Figure 36B and Figure 37 The structures of openings 127a and 127b shown can be applied to openings 125b and 125c. Furthermore, Figure 34A , Figure 34B , Figure 35 , Figure 36A , Figure 36B and Figure 37 The structure of the conductive layer 137 shown can be applied to the conductive layer 119.

[0219] Figure 38A yes Figure 34A The example of the deformed structure shown is similar to... Figure 34A The difference lies in the presence of a conductive layer 137. Figure 38A A pixel electrode 311 is shown, and an example is shown where a conductive layer 137 is disposed in the same layer as the pixel electrode 311. Thus, in Figure 38A In the example shown, the conductive layer 137 may contain the same material as the pixel electrode 311 and can be formed using the same process. For example, the pixel electrode 311 and the conductive layer 137 can be formed by processing the same conductive film. Furthermore, Figure 38B yes Figure 38A The cross-sectional view shown by the dotted lines C5-C6 illustrates, for example, a structural example of transistor 52. Figure 38B For example, an example of the structure of the layer above transistor 52 is also shown. Note that in Figure 38A in, omit Figure 34A Part of the symbol shown.

[0220] Although Figure 38A The diagram shows an example where the pixel electrode 311 does not overlap with the regions of conductive layer 111a, conductive layer 111b, conductive layer 115a, and conductive layer 135 extending in the X direction. However, the pixel electrode 311 may also have a region that overlaps with at least one of these regions. This improves the pixel aperture ratio. Furthermore, by employing a structure where the pixel electrode 311 does not overlap with the aforementioned regions, noise propagation from conductive layers 111a, 111b, 115a, and 135 to the pixel electrode 311 can be suppressed. In particular, by ensuring that the pixel electrode 311 does not overlap with the regions of conductive layer 111a (for supplying image signals) and conductive layer 115a (for supplying scan signals) extending in the X direction, noise propagation to the pixel electrode 311 can be effectively suppressed.

[0221] An insulating layer 218 and an insulating layer 235 on the insulating layer 218 are disposed such that they cover transistors 51, 52, and capacitor 57. The insulating layers 105, 218, and 235 include openings 129 extending to the conductive layer 112b. For an example, a description of the components disposed above the insulating layer 235 and the openings 129 can be found in [reference needed]. Figure 8B Explanation.

[0222] exist Figure 38B In the example shown, opening 127a leading to conductive layer 111b is provided in insulating layers 103, 105, 218, and 235. Additionally, opening 127b leading to conductive layer 135 is provided in insulating layers 218 and 235. Here, openings 127a and 127b can be formed using the same process as opening 129.

[0223] The conductive layer 137 is provided to cover openings 127a and 127b. The conductive layer 137 has a shape along the top and side surfaces of the insulating layer 235, the side surface of the insulating layer 218, the side surface of the insulating layer 105, the side surface of the insulating layer 103, the top surface of the conductive layer 111b, and the top surface of the conductive layer 135. The conductive layer 137 has areas that contact the top and side surfaces of the insulating layer 235, the side surface of the insulating layer 218, the side surface of the insulating layer 105, the side surface of the insulating layer 103, the top surface of the conductive layer 111b, and the conductive layer 135. The conductive layer 137 can be electrically connected to the conductive layer 111b inside the opening 127a and to the conductive layer 135 inside the opening 127b. Thus, the conductive layer 111b and the conductive layer 135 can be electrically connected through the conductive layer 137.

[0224] The insulating layer 237 can be provided in a manner that covers the top end of the conductive layer 137. By providing the insulating layer 237, for example, it is possible to prevent the conductive layer 137 from contacting the pixel electrode 311 and short-circuiting.

[0225] In the conductive layer 137, recesses are formed in a manner that cover opening 127a and opening 127b. An insulating layer 237 is embedded in these recesses.

[0226] in addition, Figure 38A and Figure 38B The structure of the openings 127a and 127b and the conductive layer 137 shown can also be used for Figure 34A and Figure 34B Other than the openings 127a and 127b and the conductive layer 137 shown in the accompanying drawings. For example, Figure 34A and Figure 34B The conductive layer 137 shown in the accompanying drawings, other than those shown, can be disposed in the same layer as the pixel electrode. Additionally, Figure 38A and Figure 38B The structures of openings 127a and 127b shown can also be used for openings 125b, 125c, 125d1, and 125d2. Furthermore, Figure 38A and Figure 38B The structure of the conductive layer 137 shown can also be used for the conductive layer 119. For example, the conductive layer 119 can be disposed in the same layer as the pixel electrode.

[0227] <Components of a Display Device> The following description includes the constituent elements of the display device in this embodiment.

[0228] [Semiconductor layer 113] There are no particular limitations on the semiconductor materials that can be used in semiconductor layer 113. For example, a single-material semiconductor or a compound semiconductor can be used. Examples of single-material semiconductors include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. Compound semiconductors can also be organic materials with semiconductor properties or metal oxides with semiconductor properties. Note that these semiconductor materials may also contain impurities as dopants.

[0229] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 113; amorphous semiconductors or crystalline semiconductors (single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or semiconductors in which a portion has crystalline regions) can be used. When using crystalline semiconductors, the degradation of transistor characteristics can be suppressed, so it is preferred.

[0230] Semiconductor layer 113 may be made of silicon. Examples of silicon include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS).

[0231] Transistors using amorphous silicon as the semiconductor layer 113 can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon as the semiconductor layer 113 have high field-effect mobility and can be driven at high speed. Furthermore, compared with transistors using amorphous silicon, transistors using microcrystalline silicon as the semiconductor layer 113 have high field-effect mobility and can be driven at high speed.

[0232] Semiconductor layer 113 preferably comprises a metal oxide (oxide semiconductor). Examples of metal oxides that can be used in semiconductor layer 113 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably comprises at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably comprises two or three elements selected from indium, element M, and zinc. Note that element M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, element M is preferably selected from one or more of aluminum, gallium, yttrium, and tin.

[0233] Semiconductor layer 113 may use, for example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also denoted as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), indium tin gallium oxide (In-Sn-Ga oxide), or indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. Alternatively, indium tin oxide containing silicon may be used. Alternatively, the above-mentioned oxides having an amorphous structure may be used. For example, indium oxide or indium tin oxide having an amorphous structure may be used.

[0234] In particular, element M is preferably selected from one or more of gallium, aluminum, yttrium, and tin. In particular, element M is preferably gallium.

[0235] Here, the composition of the metal oxide contained in the semiconductor layer 113 has a significant impact on the electrical characteristics and reliability of the transistor 50.

[0236] For example, by increasing the indium content in metal oxides, transistors with high on-state current can be achieved.

[0237] When using an In-Zn oxide as the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than or equal to that of zinc. For example, metal oxides with atomic ratios of In:Zn = 1:1, In:Zn = 2:1, In:Zn = 3:1, In:Zn = 4:1, In:Zn = 5:1, In:Zn = 7:1, In:Zn = 10:1, or similar ratios can be used.

[0238] When using an In-Sn oxide as the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than or equal to that of tin. For example, metal oxides with atomic ratios of In:Sn = 1:1, In:Sn = 2:1, In:Sn = 3:1, In:Sn = 4:1, In:Sn = 5:1, In:Sn = 7:1, In:Sn = 10:1 or similar can be used.

[0239] When using an In-M-Zn oxide as the semiconductor layer 113, a metal oxide in which the atomic ratio of indium relative to the atomic number of the metal element is higher than the atomic ratio of element M can be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M is more preferred. For example, the semiconductor layer 113 can use metal oxides with atomic ratios of In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. Metal oxides of the following types: Zn = 6:1:6, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10 or similar.

[0240] Note that when element M comprises multiple metallic elements, the total atomic ratio of these metallic elements can be the atomic ratio of element M. For example, when using an In-Ga-Al-Zn oxide comprising gallium and aluminum as element M, the total atomic ratio of gallium and aluminum can be the atomic ratio of element M. Furthermore, the atomic ratio of indium, element M, and zinc is preferably within the above-mentioned range.

[0241] Preferably, the metal oxide used has an indium atomic ratio relative to the number of atoms of the metal element that is 30 atomic% or more and 100 atomic% or less, preferably 30 atomic% or more and 95 atomic% or less, more preferably 35 atomic% or more and 95 atomic% or less, more preferably 35 atomic% or more and 90 atomic% or less, more preferably 40 atomic% or more and 90 atomic% or less, more preferably 45 atomic% or more and 90 atomic% or less, more preferably 50 atomic% or more and 80 atomic% or less, more preferably 60 atomic% or more and 80 atomic% or less, and more preferably 70 atomic% or more and 80 atomic% or less. For example, when an In-Ga-Zn oxide is used as the semiconductor layer 113, the indium atomic ratio relative to the total number of atoms of indium, element M, and zinc is preferably within the above-mentioned range.

[0242] In this specification and other materials, the ratio of the number of indium atoms to the number of atoms of the contained metallic elements is sometimes described as the indium content. The same applies to other metallic elements.

[0243] By increasing the indium content in metal oxides, transistors with high on-state current can be achieved. Using this transistor in applications requiring high on-state current can lead to display devices with excellent electrical characteristics.

[0244] The composition of metal oxides can be analyzed using methods such as energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple methods can be combined. Note that the actual content of elements with low concentrations can sometimes differ from the analytically obtained content due to variations in analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0245] In this specification, the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio of In:M:Zn = 4:2:3 or a near-near composition is described, it includes cases where the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Furthermore, when an atomic ratio of In:M:Zn = 5:1:6 or a near-near composition is described, it includes cases where the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2, and the atomic ratio of zinc is 5 or more and less than 7. Furthermore, when an atomic ratio of In:M:Zn = 1:1:1 or a near-near composition is described, it includes cases where the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2, and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0246] Metal oxides can be appropriately formed using sputtering or atomic layer deposition (ALD). Note that when forming metal oxides using sputtering, the atomic ratio of the target material sometimes differs from that of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes lower than that of zinc in the target material. Specifically, the atomic ratio of zinc in the metal oxide is sometimes about 40% to 90% of the atomic ratio of zinc in the target material.

[0247] Here, we will explain the reliability of transistors. One indicator of transistor reliability is the GBT (Gate Bias Temperature) stress test, which maintains an applied electric field on the gate. Specifically, the test that maintains a positive gate potential (positive bias) at high temperature relative to the source and drain potentials is called the PBTS (Positive Bias Temperature Stress) test, and the test that maintains a negative gate potential (negative bias) at high temperature is called the NBTS (Negative Bias Temperature Stress) test. Furthermore, the PBTS and NBTS tests performed under illumination are respectively called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test.

[0248] In an n-type transistor, a positive potential is applied to the gate when the transistor is in the turn-on state (the state in which current flows). Therefore, the variation in the threshold voltage of the PBTS test is one of the important factors to consider as a reliability indicator of the transistor.

[0249] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer 113, a transistor with high reliability under forward bias can be realized. In other words, a transistor with small fluctuations in the threshold voltage during PBTS testing can be achieved. Furthermore, when using a gallium-containing metal oxide, the gallium content is preferably lower than the indium content. This results in a transistor with high reliability.

[0250] One reason for the variation in threshold voltage during PBTS testing can be the presence of defect states at or near the interface between the semiconductor layer and the gate insulating layer. A higher defect state density results in more significant degradation during PBTS testing. The formation of these defect states can be suppressed by reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0251] One reason for suppressing threshold voltage variations in PBTS testing by using metal oxides containing little or no gallium in the semiconductor layer can be considered as follows: Gallium contained in metal oxides is more likely to draw oxygen than other metals (e.g., indium or zinc). Therefore, it can be inferred that at the interface between the metal oxide containing more gallium and the gate insulating layer, carrier (in this case, electron) trap sites are easily generated through gallium bonding with excess oxygen in the gate insulating layer. Thus, it can be assumed that when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing a change in the threshold voltage.

[0252] More specifically, when using an In-Ga-Zn oxide as the semiconductor layer 113, a metal oxide with an indium atomic ratio higher than that of gallium can be used in the semiconductor layer 113. Furthermore, a metal oxide with a zinc atomic ratio higher than that of gallium is more preferred. In other words, it is preferable to use a metal oxide in the semiconductor layer 113 where the atomic ratios of the metal elements satisfy In>Ga and Zn>Ga.

[0253] For example, in semiconductor layer 113, the atomic ratios of metal elements can be In:Ga:Zn = 2:1:3, In:Ga:Zn = 3:1:2, In:Ga:Zn = 4:2:3, In:Ga:Zn = 4:2:4.1, In:Ga:Zn = 5:1:3, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:7, In:Ga:Zn = 5:1:8, In: Metal oxides of Ga:Zn = 6:1:6, In:Ga:Zn = 10:1:3, In:Ga:Zn = 10:1:6, In:Ga:Zn = 10:1:7, In:Ga:Zn = 10:1:8, In:Ga:Zn = 5:2:5, In:Ga:Zn = 10:1:10, In:Ga:Zn = 20:1:10, In:Ga:Zn = 40:1:10 or similar.

[0254] Semiconductor layer 113 preferably uses a metal oxide with a gallium atomic ratio relative to the number of atoms of the contained metal element that is greater than 0 atomic% and less than 50 atomic%; preferably 0.1 atomic% or more and less than 40 atomic%; more preferably 0.1 atomic% or more and less than 35 atomic%; more preferably 0.1 atomic% or more and less than 30 atomic%; more preferably 0.1 atomic% or more and less than 25 atomic%; more preferably 0.1 atomic% or more and less than 20 atomic%; more preferably 0.1 atomic% or more and less than 15 atomic%; and more preferably 0.1 atomic% or more and less than 10 atomic%. By reducing the gallium content in the semiconductor layer, transistors with high tolerance to PBTS testing can be achieved. Note that by containing gallium in the metal oxide, it is less likely to generate oxygen vacancies (V0) in the metal oxide. O Effects such as Oxygen Vacancy.

[0255] As the semiconductor layer 113, a gallium-free metal oxide can also be used. For example, In-Zn oxide can be used as the semiconductor layer 113. In this case, when the atomic ratio of indium to the number of metal atoms in the metal oxide is increased, the field-effect mobility of the transistor can be improved. On the other hand, when the atomic ratio of zinc to the number of metal atoms in the metal oxide is increased, the metal oxide has high crystallinity, thus suppressing variations in the electrical characteristics of the transistor and improving reliability. Furthermore, indium oxide and other gallium- and zinc-free metal oxides can also be used as the semiconductor layer 113. By using a gallium-free metal oxide, the variation in the threshold voltage during PBTS testing can be made extremely small.

[0256] For example, an oxide containing indium and zinc can be used as the semiconductor layer 113. In this case, metal oxides with an atomic ratio of, for example, In:Zn = 2:3, In:Zn = 4:1, or similar can be used.

[0257] Note that gallium is typically used as an example, but this can also be applied to cases where element M is used instead of gallium. Preferably, a metal oxide with a higher atomic ratio of indium than element M is used as the semiconductor layer 113. Furthermore, a metal oxide with a higher atomic ratio of zinc than element M is preferred.

[0258] By using a metal oxide with a low content of element M as the semiconductor layer 113, a transistor with high reliability under forward bias can be realized. By using this transistor as a transistor that requires high reliability under forward bias, a display device with high reliability can be realized.

[0259] Next, the reliability of the transistor for light will be explained.

[0260] Because light strikes the transistor, its electrical characteristics sometimes change. Particularly preferred are transistors used in areas where light may strike, exhibiting minimal change in electrical characteristics under light irradiation and high reliability for light. Reliability for light can be evaluated, for example, by the amount of variation in the threshold voltage during NBTIS testing.

[0261] By increasing the content of element M in the metal oxide, transistors with high reliability against light can be achieved. In other words, transistors with small variations in threshold voltage during NBTIS testing can be realized. Specifically, metal oxides with a higher atomic ratio of element M than indium have a larger band gap, which reduces the variation in threshold voltage during NBTIS testing of the transistor. The band gap of the metal oxide included in the semiconductor layer 113 is preferably 2.0 eV or more, more preferably 2.5 eV or more, more preferably 3.0 eV or more, more preferably 3.2 eV or more, more preferably 3.3 eV or more, more preferably 3.4 eV or more, and more preferably 3.5 eV or more.

[0262] For example, the semiconductor layer 113 can be a metal oxide with an atomic ratio of In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4 or similar.

[0263] The semiconductor layer 113 may be suitably made of a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic% or more and 70 atomic% or less, preferably 30 atomic% or more and 70 atomic% or less, more preferably 30 atomic% or more and 60 atomic% or less, more preferably 40 atomic% or more and 60 atomic% or less, and more preferably 50 atomic% or more and 60 atomic% or less.

[0264] When using an In-Ga-Zn oxide as the semiconductor layer 113, a metal oxide with an indium atomic ratio relative to the number of metal elements that is less than or equal to the number of gallium atoms can be used. For example, metal oxides with an indium:Ga:Zn atomic ratio of 1:1:1, 1:1:1.2, 1:3:2, 1:3:3, 1:3:4, or similar ratios can be used.

[0265] The semiconductor layer 113 can be made of a metal oxide in particular in which the ratio of the number of gallium atoms to the number of atoms of the metal element contained therein is 20 atomic% or more and 60 atomic% or less, preferably 20 atomic% or more and 50 atomic% or less, more preferably 30 atomic% or more and 50 atomic% or less, more preferably 40 atomic% or more and 60 atomic% or less, and even more preferably 50 atomic% or more and 60 atomic% or less.

[0266] By using a metal oxide with a high content of element M in the semiconductor layer 113, a transistor with high reliability to light can be realized. By using this transistor as a transistor that requires high reliability to light, a display device with high reliability can be realized.

[0267] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used in the semiconductor layer 113. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, a display device with both excellent electrical characteristics and high reliability can be realized.

[0268] Semiconductor layer 113 may also have a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers comprising semiconductor layer 113 may also be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs.

[0269] The compositions of the two or more metal oxide layers included in the semiconductor layer 113 can also be different from each other. For example, a stacked structure can be used, consisting of a first metal oxide layer with an In:M:Zn ratio of 1:3:4 or similar, and a second metal oxide layer disposed on the first metal oxide layer with an In:M:Zn ratio of 1:1:1 or similar. Furthermore, gallium or aluminum is particularly preferred as element M. For example, a stacked structure selected from any one of indium oxide, indium gallium oxide, and IGZO, and any one of IAZO, IAGZO, and ITZO (registered trademark) can also be used.

[0270] A crystalline metal oxide layer is preferably used as the semiconductor layer 113. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nano-crystal (nc) structure can be used. By using a crystalline metal oxide layer as the semiconductor layer 113, the defect state density in the semiconductor layer 113 can be reduced, thereby enabling a display device with high reliability.

[0271] The higher the crystallinity of the metal oxide layer used for semiconductor layer 113, the lower the defect state density in semiconductor layer 113 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0272] When forming metal oxide layers using sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio relative to the overall deposition gas used during formation (also known as the oxygen flow rate ratio), the more crystalline the metal oxide layer can be formed.

[0273] Semiconductor layer 113 may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, wherein the second metal oxide layer may include regions with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may include regions with lower crystallinity than the first metal oxide layer. The compositions of the two or more metal oxide layers included in semiconductor layer 113 may also be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. For example, by using the same sputtering target and making different oxygen flow ratios, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the compositions of the two or more metal oxide layers included in semiconductor layer 113 may also be different from each other.

[0274] The thickness of the semiconductor layer 113 is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less, more preferably 20 nm or more and 40 nm or less, and more preferably 25 nm or more and 40 nm or less.

[0275] The substrate temperature for forming the semiconductor layer 113 is preferably above room temperature (25°C) and below 200°C, more preferably above room temperature and below 130°C. By using a substrate temperature within the above range, bending or distortion of the substrate can be suppressed when using a large-area glass substrate.

[0276] Here, oxygen vacancies that may form in semiconductor layer 113 will be explained.

[0277] When an oxide semiconductor is used in semiconductor layer 113, sometimes hydrogen in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, creating oxygen vacancies (V0) in the oxide semiconductor. O Furthermore, sometimes hydrogen enters the defects in oxygen vacancies (hereinafter referred to as V). O H is used as a donor to generate electrons as charge carriers. Additionally, sometimes electrons are generated as charge carriers due to the bonding of a portion of the hydrogen with oxygen atoms bonded to metal atoms. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics. Furthermore, because hydrogen in oxide semiconductors is easily moved by heat or electric fields, a large amount of hydrogen in the oxide semiconductor may lead to a decrease in transistor reliability.

[0278] V O H can be used as a donor in oxide semiconductors. However, it is difficult to quantitatively evaluate this defect. Therefore, in oxide semiconductors, evaluation is sometimes based on carrier concentration rather than donor concentration. Consequently, in this specification, etc., the carrier concentration under the assumption of no applied electric field is sometimes used as a parameter for oxide semiconductors instead of donor concentration. That is to say, the "carrier concentration" described in this specification, etc., may sometimes be referred to as "donor concentration".

[0279] Therefore, when an oxide semiconductor is used as the semiconductor layer 113, it is preferable to minimize the V in the semiconductor layer 113. O H is used to make it a high-purity intrinsic or substantially high-purity intrinsic. To obtain this V... O For oxide semiconductors with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen from the oxide semiconductor (sometimes described as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to repair oxygen vacancies (V O ). By V O Oxide semiconductors with sufficiently reduced impurities such as hydrogen (H) can impart stable electrical characteristics when used in the channel formation region of transistors. Note that sometimes oxygen is supplied to the oxide semiconductor to repair oxygen vacancies (V0). O The treatment of ) is called oxidation treatment.

[0280] When an oxide semiconductor is used as semiconductor layer 113, the carrier concentration of the oxide semiconductor in the region used as the channel formation region is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 Further optimization of less than 1×10 13 cm -3Further optimization of less than 1×10 12 cm -3 Note that there is no specific limit to the lower limit of the carrier concentration of the oxide semiconductor in the region used as the channel formation region; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0281] [Insulation layer 103] The insulating layer 103 can be made of inorganic or organic insulating materials. The insulating layer 103 can also have a laminated structure of inorganic and organic insulating materials.

[0282] Inorganic insulating materials can be appropriately used for insulating layer 103. One or more of oxides, oxynitrides, oxynitrides, and nitrides can be used as inorganic insulating materials. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon oxynitride, and aluminum nitride can be used for insulating layer 103.

[0283] Note that in this specification, etc., oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content in their composition. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content in their composition. For example, silicon oxynitride refers to materials in which the oxygen content is greater than the nitrogen content in their composition, while silicon oxynitride refers to materials in which the nitrogen content is greater than the oxygen content in their composition.

[0284] For example, the content of oxygen and nitrogen can be analyzed using analytical methods such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is preferred when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). Conversely, SIMS is preferred when the content of the target element is low (e.g., less than 1 atomic% or less or less than 0.5 atomic%. When comparing elemental contents, a combined analysis using both SIMS and XPS is more preferable.

[0285] The insulating layer 103 may also have a stacked structure of two or more layers. The cross-sectional view showing the structural example of the transistor 50 above illustrates a structure in which the insulating layer 103 has a stacked structure of insulating layer 103a and insulating layer 103b on insulating layer 103a. Both insulating layer 103a and insulating layer 103b can be made of materials suitable for the aforementioned insulating layer 103. Note that insulating layer 103a and insulating layer 103b may be made of the same material or different materials. Note that insulating layer 103a may also have a stacked structure of two or more layers. Insulating layer 103b may also have a stacked structure of two or more layers.

[0286] The thickness of insulating layer 103a can be greater than the thickness of insulating layer 103b. The deposition rate (also called deposition speed) of insulating layer 103a is preferably faster, for example, faster than the deposition rate of insulating layer 103b. In particular, when the thickness of insulating layer 103a is large, the deposition rate of insulating layer 103a is preferably faster. By increasing the deposition rate of insulating layer 103a, productivity can be increased. For example, increasing the power during the formation of insulating layer 103a can increase the deposition rate.

[0287] The stress in the insulating layer 103a is preferably low. When the thickness of the insulating layer 103a is large, the stress in the insulating layer 103a is high, which can sometimes cause substrate warping. By reducing the stress in the insulating layer 103a, problems in the process caused by stress such as substrate warping can be suppressed.

[0288] Insulating layer 103b serves as a barrier layer to suppress gas escaping from insulating layer 103a. Insulating layer 103b is preferably made of a material that does not readily diffuse the gas. Insulating layer 103b preferably includes regions with a higher film density than insulating layer 103a. Increasing the film density of insulating layer 103b improves its barrier properties. Insulating layer 103b can, for example, be made of a material with a higher nitrogen content than insulating layer 103a. Increasing the nitrogen content of insulating layer 103b improves its barrier properties.

[0289] The insulating layer 103b only needs to have a thickness that serves as a barrier layer to suppress gas escaping from the insulating layer 103a, and its thickness can be smaller than that of the insulating layer 103a. The deposition rate of the insulating layer 103b is preferably slower, for example, slower than that of the insulating layer 103a. By slowing down the deposition rate of the insulating layer 103b, its film density increases, thereby improving its barrier properties. Furthermore, by increasing the substrate temperature during the deposition of the insulating layer 103b, its film density increases, thus improving its barrier properties.

[0290] The evaluation of film density can be achieved, for example, using Rutherford backscattering spectrometry (RBS) or X-ray reflectance (XRR). Furthermore, differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observations, a high film density results in a darker (darker) TEM image, while a low film density results in a lighter (brighter) TEM image. Therefore, in TEM images, insulating layer 103b sometimes appears darker (darker) than insulating layer 103a. Note that even though insulating layers 103a and 103b use the same material, their different film densities can sometimes be observed as differences in contrast in cross-sectional TEM images.

[0291] The insulating layer 103b sometimes includes regions in the film with a lower hydrogen concentration than the insulating layer 103a. The difference in hydrogen concentration between the insulating layers 103a and 103b can be evaluated, for example, using secondary ion mass spectrometry (SIMS).

[0292] Here, taking the structure of semiconductor layer 113 using metal oxide as an example, the insulating layer 103 will be specifically explained.

[0293] When an oxide semiconductor is used in semiconductor layer 113, inorganic insulating materials can be appropriately used in insulating layers 103a and 103b.

[0294] The insulating layer 103a is preferably made of oxide or oxynitride. The insulating layer 103a is preferably made of a film that releases oxygen upon heating. For example, silicon oxide or silicon oxynitride may be suitably used for the insulating layer 103a.

[0295] Oxygen can be supplied from insulating layer 103a to semiconductor layer 113 by releasing oxygen from insulating layer 103a. By supplying oxygen from insulating layer 103a to semiconductor layer 113, especially to the channel formation region of semiconductor layer 113, the number of oxygen vacancies (V) in semiconductor layer 113 can be reduced. O ) and V O H. Therefore, transistor 50 can be a transistor exhibiting good electrical characteristics and high reliability. The insulating layer 103a preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient of the insulating layer 103a, oxygen can easily diffuse into the insulating layer 103a, allowing for efficient supply of oxygen from the insulating layer 103a to the semiconductor layer 113. Note that other methods for supplying oxygen to the semiconductor layer 113 include heating treatment in an oxygen-containing atmosphere and plasma treatment in an oxygen-containing atmosphere.

[0296] Preferably, the amount of impurities (e.g., water and hydrogen) released from the insulating layer 103a itself is minimal. By reducing the release of impurities from the insulating layer 103a, the diffusion of impurities into the semiconductor layer 113 can be suppressed. Consequently, the transistor 50 can be a transistor exhibiting good electrical characteristics and high reliability.

[0297] The insulating layer 103a can be, for example, silicon oxide or silicon oxynitride produced using plasma-enhanced chemical vapor deposition (PECVD). In this case, a mixture of silicon-containing and oxygen-containing gases is preferably used as the source gas. As the silicon-containing gas, one or more of silane, disilane, propane, and fluorinated silane can be used, for example. As the oxygen-containing gas, one or more of oxygen (O2), ozone (O3), nitrous oxide (N2O), nitric oxide (NO), and nitrogen dioxide (NO2) can be used, for example. Note that by increasing the power during the formation of the insulating layer 103a, the amount of impurities (e.g., water and hydrogen) released from the insulating layer 103a can be reduced.

[0298] The insulating layer 103b is preferably not permeable to oxygen. The insulating layer 103b serves as a barrier layer to inhibit oxygen from escaping from the insulating layer 103a. Furthermore, the insulating layer 103b is preferably not permeable to hydrogen. The insulating layer 103b serves as a barrier layer to inhibit hydrogen from diffusing from the outside of the transistor through the insulating layer 103 to the semiconductor layer 113. The film density of the insulating layer 103b is preferably high. By increasing the film density of the insulating layer 103b, the barrier properties against oxygen and hydrogen can be improved. The film density of the insulating layer 103b is preferably higher than that of the insulating layer 103a. When silicon oxide or silicon oxynitride is used as the insulating layer 103a, the insulating layer 103b can be, for example, suitably using silicon nitride, silicon oxynitride, or aluminum oxide. The insulating layer 103b preferably includes regions with a higher nitrogen content than the insulating layer 103a. The insulating layer 103b can, for example, use materials with a higher nitrogen content than the insulating layer 103a. The insulating layer 103b preferably uses nitrides or oxides of nitrogen. The insulating layer 103b may, for example, be made of silicon nitride or silicon oxynitride.

[0299] When oxygen contained in insulating layer 103a diffuses upward from a region of insulating layer 103a that is not in contact with semiconductor layer 113 (e.g., the top surface of insulating layer 103a), the amount of oxygen supplied from insulating layer 103a to semiconductor layer 113 may decrease. By providing insulating layer 103b on insulating layer 103a, the diffusion of oxygen contained in insulating layer 103a from the region of insulating layer 103a that is not in contact with semiconductor layer 113 can be suppressed. Therefore, the amount of oxygen supplied from insulating layer 103a to semiconductor layer 113 is increased, thereby reducing oxygen vacancies (V0) in semiconductor layer 113. O ) and V OH. Therefore, transistor 50 can be a transistor that exhibits good electrical characteristics and high reliability.

[0300] Sometimes, the conductive layer 112 is oxidized due to oxygen contained in the insulating layer 103a, resulting in increased resistance. Furthermore, sometimes the conductive layer 112 is oxidized due to oxygen contained in the insulating layer 103a, thus reducing the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113. By providing an insulating layer 103b on the insulating layer 103a, the oxidation of the conductive layer 112 and the resulting increase in resistance can be suppressed. Simultaneously, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 is increased, reducing the number of oxygen vacancies (V0) in the semiconductor layer 113. O ) and V O H. Thus, transistor 50 can be a transistor that exhibits good electrical characteristics and high reliability.

[0301] When hydrogen diffuses into semiconductor layer 113, it sometimes reacts with oxygen atoms contained in the oxide semiconductor to become water, forming oxygen vacancies (V). O Furthermore, sometimes a V-shape is formed. O H, thus increasing the carrier concentration. By providing an insulating layer 103b on top of the insulating layer 103a, the oxygen vacancies (V) in the semiconductor layer 113 can be reduced. O ) and V O H. Thus, transistor 50 can be a transistor that exhibits good electrical characteristics and high reliability.

[0302] The insulating layer 103b preferably has a thickness that serves as a barrier layer against oxygen and hydrogen. When the thickness of the insulating layer 103b is small, its function as a barrier layer is sometimes reduced. On the other hand, when the thickness of the insulating layer 103b is large, the area of ​​the semiconductor layer 113 in contact with the insulating layer 103a becomes narrower, and sometimes the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 decreases. The thickness of the insulating layer 103b can also be smaller than the thickness of the insulating layer 103a. The thickness of the insulating layer 103b is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 70 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 10 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less, and more preferably 20 nm or more and 40 nm or less. By keeping the thickness of the insulating layer 103b within the above range, the number of oxygen vacancies (V0) in the semiconductor layer 113, especially in the channel formation region, can be reduced. O ) and V O H. Therefore, transistor 50 can be a transistor that exhibits good electrical characteristics and high reliability.

[0303] Preferably, the amount of impurities (e.g., water and hydrogen) released from the insulating layer 103b itself is minimal. By reducing the release of impurities from the insulating layer 103b, impurity diffusion into the semiconductor layer 113 can be suppressed. Consequently, the transistor 50 can be a transistor exhibiting good electrical characteristics and high reliability.

[0304] In transistor 50, the region of semiconductor layer 113 in contact with insulating layer 103 can be used as a channel formation region. That is, oxygen is selectively supplied to the channel formation region, thereby reducing oxygen vacancies (V0). O ) and V O H. Therefore, transistor 50 can be a transistor that exhibits good electrical characteristics and high reliability.

[0305] [Conductive layer 111, conductive layer 112 and conductive layer 115] The conductive layers 111 and 112, used as source or drain electrodes, and the conductive layer 115, used as gate electrodes, can be formed using one or more of chromium, copper, aluminum, magnesium, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or alloys composed of one or more of the aforementioned metals. Conductive layers 111, 112, and 115 can suitably use low-resistance conductive materials containing one or more of copper, silver, gold, and aluminum. In particular, copper or aluminum has advantages in mass production and is therefore preferred.

[0306] Conductive layers 111, 112, and 115 may be made of metal oxides (also known as oxide conductors). Examples of oxide conductors (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0307] Here, oxide conductors (OC) will be explained. For example, an oxygen vacancy is formed in a metal oxide that has semiconductor properties, and hydrogen is added to this oxygen vacancy to form a donor level near the conduction band. As a result, the conductivity of the metal oxide increases, and it becomes a conductor. Metal oxides that can become conductors are called oxide conductors.

[0308] Conductive layers 111, 112, and 115 can also be constructed using a stacked structure of conductive layers containing the aforementioned oxide conductor (metal oxide) and conductive layers containing metal or alloy. By using conductive layers containing metal or alloy, wiring resistance can be reduced.

[0309] As conductive layers 111, 112, and 115, Cu-X alloys (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be used. By using Cu-X alloys, processing can be performed using a wet etching process, thereby reducing manufacturing costs.

[0310] Note that conductive layers 111, 112, and 115 may be made of the same or different materials.

[0311] Here, taking the structure in which a metal oxide is used as the semiconductor layer 113 as an example, the conductive layer 111 and the conductive layer 112 will be specifically described.

[0312] When an oxide semiconductor is used as the semiconductor layer 113, the resistance sometimes increases because the conductive layers 111 and 112 are oxidized due to the oxygen contained in the semiconductor layer 113. The resistance sometimes increases because the conductive layers 111 and 112 are oxidized due to the oxygen contained in the insulating layer 103a. Furthermore, the resistance sometimes increases because the oxygen vacancies (V0) in the semiconductor layer 113 are oxidized due to the oxygen contained in the semiconductor layer 113. O The amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may decrease due to the oxidation of conductive layers 111 and 112 caused by oxygen contained in the insulating layer 103a.

[0313] Both conductive layers 111 and 112 are preferably made of materials that are not easily oxidized. Both conductive layers 111 and 112 are preferably made of oxide conductors. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) can be suitably used. Both conductive layers 111 and 112 may also be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride. Conductive layers 111 and 112 may also have a laminated structure of the above materials.

[0314] By using materials that are not easily oxidized in conductive layers 111 and 112, the high resistance caused by oxidation of oxygen contained in semiconductor layer 113 or oxygen contained in insulating layer 103a can be suppressed. Furthermore, oxygen vacancies (V0) in semiconductor layer 113 can be utilized to reduce oxidation. O While suppressing the increase of oxygen vacancies, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 is increased. Therefore, the number of oxygen vacancies (V) in the semiconductor layer 113 can be reduced. O ) and V O H. Thus, transistor 50 can be a transistor exhibiting good electrical characteristics and high reliability. Note that conductive layers 111 and 112 can be made of the same material or different materials.

[0315] [Insulation layer 105] The defect density of the insulating layer 105, which serves as the gate insulating layer, is preferably low. When the defect density of the insulating layer 105 is low, a transistor exhibiting good electrical characteristics can be realized. Furthermore, the insulating layer 105 preferably has a high dielectric withstand voltage. Because the insulating layer 105 has a high dielectric withstand voltage, the transistor 50 can be a highly reliable transistor.

[0316] The insulating layer 105 may be one or more of the following: oxides, oxynitrides, oxynitrides, and nitrides, which have insulating properties. The insulating layer 105 may be one or more of the following: silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxides. The insulating layer 105 may also be a single layer or a stacked layer. The insulating layer 105 may also have a stacked structure of oxides and nitrides, for example.

[0317] Note that in micro-transistors, leakage current sometimes increases when the gate insulating layer is thin. By using a material with a relatively high permittivity (also known as a high-k material) in the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0318] Preferably, the amount of impurities (e.g., water and hydrogen) released from the insulating layer 105 itself is small. Because the amount of impurities released from the insulating layer 105 is small, impurity diffusion to the semiconductor layer 113 can be suppressed. Therefore, the transistor 50 can be a transistor exhibiting good electrical characteristics and high reliability.

[0319] Since the insulating layer 105 is formed on the semiconductor layer 113, it is preferable to form the film under conditions that minimize damage to the semiconductor layer 113. For example, it is preferable to form the film under conditions that are sufficiently slow in deposition rate, specifically slower than that of the insulating layer 103b. For example, when forming the insulating layer 105 using the PECVD method, forming it under low power conditions can minimize damage to the semiconductor layer 113.

[0320] Here, taking the structure of semiconductor layer 113 using metal oxide as an example, the insulating layer 105 will be specifically explained.

[0321] To improve the interface properties with the semiconductor layer 113, the insulating layer 105 preferably uses an oxide. For example, the insulating layer 105 may suitably use one or more of silicon oxide and silicon oxynitride. Furthermore, the insulating layer 105 more preferably uses a film that releases oxygen upon heating.

[0322] Note that the insulating layer 105 may also have a stacked structure. The insulating layer 105 may have a stacked structure of an oxide film contacting the semiconductor layer 113 and a nitride film contacting the conductive layer 115. For example, silicon oxide and silicon oxynitride, or one or more, can be suitably used as the oxide film. Silicon nitride can be suitably used as the nitride film. When the insulating layer 105 has a stacked structure, using an oxide on at least the side of the insulating layer 105 in contact with the semiconductor layer 113 can improve the interface characteristics with the semiconductor layer 113, and is therefore preferred.

[0323] [Substrate 101] While there are no particular restrictions on the material of substrate 101, it must at least possess heat resistance capable of withstanding subsequent heat treatment. For example, single-crystal or polycrystalline semiconductor substrates made of silicon or silicon carbide, compound semiconductor substrates such as silicon-germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as substrate 101. Alternatively, substrates with semiconductor elements disposed on the aforementioned substrates can also be used as substrate 101. Furthermore, printed circuit boards can also be used as substrate 101. Note that the semiconductor substrate and insulating substrate can be circular or angular in shape.

[0324] A flexible substrate can also be used as substrate 101, and transistor 50 can be formed directly on the flexible substrate, for example. Alternatively, a release layer can be provided between substrate 101 and transistor 50, etc. A release layer can be used when a part or all of the display device is manufactured on the release layer, and then it is separated from substrate 101 and transferred to another substrate. In this case, transistor 50, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0325] [Insulation layer 218] The insulating layer 218 is preferably made of a material that does not readily diffuse impurities. Therefore, the insulating layer 218 serves as a barrier layer to suppress the diffusion of impurities from the outside into the transistor. Examples of such impurities include water and hydrogen. By providing the insulating layer 218, the reliability of the display device can be improved.

[0326] The insulating layer 218 can be an insulating layer containing inorganic materials or an insulating layer containing organic materials. For example, inorganic materials such as oxides or nitrides can be suitably used for the insulating layer 218. More specifically, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, silicon oxynitride is suitable for use in the insulating layer 218 because it releases few impurities (e.g., water and hydrogen) and can be used as a barrier layer to suppress the diffusion of impurities from the top of the transistor to the transistor. For example, one or more of acrylic resin and polyimide resin can be used as organic materials. Photosensitive materials can also be used as organic materials. Furthermore, two or more of the above-described insulating films can be laminated. The insulating layer 218 can also have a laminated structure containing both inorganic and organic insulating layers.

[0327] [Insulation layer 235] The insulating layer 235 has the function of reducing the bumps and depressions caused by transistors 51, 52, and capacitor 57. In this specification, the insulating layer 235 is sometimes referred to as a planarization layer.

[0328] As the insulating layer 235, an insulating layer containing organic materials can be appropriately used. As the organic material, a photosensitive organic resin is preferred, for example, a photosensitive resin composition containing acrylic resin is preferred. Note that in this specification, etc., acrylic resin does not only refer to polymethacrylate or methacrylic resin, but sometimes also refers to acrylic polymers in a broader sense.

[0329] The insulating layer 235 can also be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins. Alternatively, the insulating layer 235 can also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Furthermore, photoresist can be used as the photosensitive resin. Both positive and negative photosensitive organic resins can be used.

[0330] The insulating layer 235 may also have a stacked structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 235 may have a stacked structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 235, the inorganic insulating layer can be used as an etching protection layer. As a result, the deterioration of the flatness of the insulating layer 235 can be suppressed when a portion of the insulating layer 235 is etched during the formation of the pixel electrode 311.

[0331] When the flatness of the top surface of the insulating layer 235 on which the light-emitting element 60 is formed is low, poor connection may occur, for example, due to the disconnection of the common electrode 315. Furthermore, when the flatness of the top surface of the insulating layer 235 is low, the thickness of the common electrode 315 may locally decrease, leading to an increase in resistance. Additionally, when the flatness of the top surface of the insulating layer 235 is low, the processing accuracy of the layers formed on the insulating layer 235 may decrease. By making the top surface of the insulating layer 235 flat, for example, the processing accuracy of the light-emitting element 60 provided on the insulating layer 235 is improved, thus enabling a display device with high resolution. Furthermore, poor connection due to the disconnection of the common electrode 315 and the increase in resistance due to localized thinning of the common electrode 315 can be suppressed, thus enabling a display device with high display quality.

[0332] Note that sometimes a portion of the insulating layer 235 is removed during the formation of the pixel electrode 311. The insulating layer 235 may also have recesses in areas that do not overlap with the pixel electrode 311.

[0333] [Insulation layer 237] Insulating layer 237 can be an insulating layer containing inorganic materials or an insulating layer containing organic materials. Insulating layer 237 can use materials that can be used in insulating layer 218 or insulating layer 235. Insulating layer 237 can also have a laminated structure containing insulating layers containing inorganic materials and insulating layers containing organic materials.

[0334] [Protective layer 331] The protective layer 331 can have a single-layer structure or a stacked structure of two or more layers. Furthermore, there are no limitations on the conductivity of the protective layer 331. The protective layer 331 can be at least one of an insulating film, a semiconductor film, and a conductive film.

[0335] By including an inorganic film in the protective layer 331, oxidation of the common electrode 315 and the entry of impurities (such as moisture and oxygen) into the light-emitting element 60 can be suppressed. Therefore, the deterioration of the light-emitting element 60 is suppressed, and the reliability of the display device can be improved.

[0336] The protective layer 331 can be, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or an oxynitride insulating film. The protective layer 331 can be an insulating layer containing inorganic materials. As the protective layer 331, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or an oxynitride insulating film can be used. The protective layer 331 can have a single-layer structure or a multilayer structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, indium gallium zinc oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, and tantalum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. In particular, the protective layer 331 preferably includes a nitrided insulating film or a nitrogen-oxidized insulating film, more preferably a nitrided insulating film.

[0337] Alternatively, an inorganic film comprising In-Sn oxide (ITO), In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or In-Ga-Zn oxide (IGZO) may be used for the protective layer 331. This inorganic film preferably has high resistance; specifically, it preferably has a higher resistance than the common electrode 315. The inorganic film may also contain nitrogen.

[0338] When the light emitted by the light-emitting element 60 is extracted through the protective layer 331, the visible light transmittance of the protective layer 331 is preferably high. For example, ITO, IGZO and alumina are inorganic materials with high visible light transmittance, so they are preferred.

[0339] As a protective layer 331, for example, a stacked structure of an alumina film and a silicon nitride film on the alumina film, or a stacked structure of an alumina film and an IGZO film on the alumina film can be used. By using this stacked structure, impurities (such as water and oxygen) can be suppressed from entering the EL layer side.

[0340] The protective layer 331 can also be made of organic materials. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of the above resins can be used as the protective layer 331. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used as the protective layer 331. Furthermore, the protective layer 331 can also comprise both inorganic and organic materials.

[0341] The protective layer 331 can also have a two-layer structure formed using different deposition methods. Specifically, the first layer of the protective layer 331 can be formed using the ALD method, while the second layer of the protective layer 331 can be formed using the sputtering method.

[0342] [Substrate 152] The substrate 152 can be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, or semiconductor, etc. The substrate on the side from which light from the light-emitting element 60 is extracted uses a material that allows the light to pass through. By using a flexible material for the substrate 152, the flexibility of the display device can be improved. A polarizer can also be used as the substrate 152. Furthermore, an adhesive film or a substrate film can also be used as the substrate 152.

[0343] The substrate 152 can be made of materials such as polyester resins (e.g., polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyethersulfone (PES) resins, polyamide resins (nylon or aramid, etc.), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, or cellulose nanofibers. Glass with a flexible thickness can also be used as the substrate 152.

[0344] When a thin film is used as a substrate, the display device may experience shape changes such as wrinkles due to water absorption. Therefore, it is preferable to use a thin film with low water absorption as a substrate. For example, it is preferable to use a thin film with a water absorption rate of 1% or less, more preferably a thin film with a water absorption rate of 0.1% or less, and even more preferably a thin film with a water absorption rate of 0.01% or less.

[0345] Furthermore, various optical components can be disposed on the outer side of the substrate 152. These optical components may include polarizers (e.g., circular polarizers), retardation plates, light diffusion layers (e.g., diffusion films), antireflective layers, and condensing films. Additionally, surface protective layers such as antistatic films to suppress dust adhesion, water-repellent films to prevent soiling, hard coatings to prevent damage during use, or impact-absorbing layers can also be disposed on the outer side of the substrate 152. For example, a glass layer or a silicon dioxide layer (SiO2) can be provided as a surface protective layer. x A protective layer (such as a diamond-like carbon layer) is preferred as it can prevent the surface from getting dirty or damaged. Alternatively, DLC (diamond-like carbon) and aluminum oxide (Al₂O₃) can also be used as surface protective layers. xMaterials such as polyester or polycarbonate can be used. Furthermore, materials with high visible light transmittance are preferred for the surface protective layer. Additionally, materials with high hardness are preferred for the surface protective layer.

[0346] When a circular polarizer is superimposed on a display device, it is preferable to use a substrate with high optical isotropy as the substrate included in the display device. A substrate with high optical isotropy has lower birefringence (or, in other words, less birefringence).

[0347] The absolute value of the retardation value of the substrate with high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0348] Examples of films with high optical isotropy include cellulose triacetate (also known as TAC) films, cyclic olefin polymer (COP) films, cyclic olefin copolymer (COC) films, and acrylic films.

[0349] [Adhesive layer 142] As the adhesive layer 142, various curing adhesives such as UV-curing adhesives, reactive curing adhesives, thermosetting adhesives, or anaerobic adhesives can be used. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins can also be used. Furthermore, adhesive sheets can also be used, for example.

[0350] [Light-shielding layer 317] Examples of materials that can be used for the light-shielding layer 317 include carbon black, titanium black, metals, metal oxides, and composite oxides containing solid solutions of multiple metal oxides. Alternatively, the light-shielding layer 317 can also be a structure consisting of multiple layers of material containing coloring layers. For example, the light-shielding layer 317 can be a stacked structure containing layers of material containing coloring layers for transmitting light of a certain color and layers containing coloring layers for transmitting light of other colors.

[0351] The above is an explanation of the constituent elements.

[0352] <Storage Unit> One aspect of the present invention can be applied not only to display devices but also to storage devices. Figure 39AThis is a block diagram illustrating a structural example of a storage device 400 to which one aspect of the present invention can be applied. The storage device 400 includes a storage unit 410, a word line driving circuit 411, a bit line driving circuit 413, and a power supply circuit 415. The storage unit 410 includes a plurality of storage cells 420 arranged in a matrix. Note that the power supply circuit 415 may also be disposed externally to the storage device 400.

[0353] The word line driving circuit 411 is electrically connected to the memory cell 420 via wiring 41. For example, similar to the display device 10 shown in FIG. 1, wiring 41 extends in the row direction of the aforementioned matrix. In the memory device 400, wiring 41 is used as a word line.

[0354] Bit line drive circuit 413 is electrically connected to memory cell 420 via wiring 43. For example, similar to display device 10 shown in FIG. 1, wiring 43 extends in the column direction of the aforementioned matrix. In memory device 400, wiring 41 is used as a bit line.

[0355] The power supply circuit 415 is electrically connected to the memory cell 420 via wiring 45. For example, all memory cells 420 can be electrically connected to the power supply circuit 415 via the same wiring 45. Wiring 45 serves as a power line.

[0356] The word line driver circuit 411 has the function of selecting the storage cell 420 for writing data row by row. Additionally, the word line driver circuit 411 also has the function of selecting the storage cell 420 for reading data row by row. Specifically, the word line driver circuit 411 can select either the storage cell 420 for writing data or the storage cell 420 for reading data by outputting a signal to the wiring 41.

[0357] The bit line driver circuit 413 has the function of writing data to the memory cell 420 selected by the word line driver circuit 411 via wiring 43. Furthermore, the bit line driver circuit 413 has the function of amplifying the data output from the memory cell 420 to the wiring 43, for example, outputting it to the outside of the memory device 400, thereby reading the data held in the memory cell 420. Moreover, the bit line driver circuit 413 has the function of pre-charging the wiring 43 before reading data from the memory cell 420.

[0358] The power supply circuit 415 has the function of generating a power supply potential and supplying it to the wiring 45. For example, the power supply circuit 415 has the function of generating a high potential or a low potential and supplying it to the wiring 45.

[0359] Figure 39B , Figure 39C , Figure 39D , Figure 39E and Figure 39F This is a circuit diagram illustrating an example of the structure of memory cell 420. Here, Figure 39B , Figure 39C , Figure 39D , Figure 39E and Figure 39F The storage units 420 shown are storage unit 420A, storage unit 420B, storage unit 420C, storage unit 420D and storage unit 420E.

[0360] The memory cell 420A includes a transistor 51 and a capacitor 57. That is to say, the memory cell 420A is a 1Tr1C type memory cell.

[0361] In memory cell 420A, one of the source and drain of transistor 51 is electrically connected to wiring 43. The other of the source and drain of transistor 51 is electrically connected to one electrode of capacitor 57. The gate of transistor 51 is electrically connected to wiring 41. The other electrode of capacitor 57 is electrically connected to wiring 45.

[0362] In memory cell 420A, when transistor 51 is turned on, data is written to memory cell 420A through wiring 43; when transistor 51 is turned off, the written data is retained. Alternatively, by turning transistor 51 on, the data held in memory cell 420A can be output to wiring 43, so the bit line drive circuit 413 can read the data.

[0363] Memory cell 420B includes transistor 51, transistor 52, and capacitor 57. That is to say, memory cell 420B is a 2Tr1C type memory cell.

[0364] Storage cell 420B is electrically connected to wirings 41a and 41d (as wiring 41) and wirings 43a and 43b (as wiring 43). Specifically, one of the source and drain of transistor 51 is electrically connected to wiring 43a. The other of the source and drain of transistor 51 is electrically connected to one electrode of capacitor 57. One electrode of capacitor 57 is electrically connected to the gate of transistor 52. The gate of transistor 51 is electrically connected to wiring 41a. The other electrode of capacitor 57 is electrically connected to wiring 41d. One of the source and drain of transistor 52 is electrically connected to wiring 43b. The other of the source and drain of transistor 52 is electrically connected to wiring 45.

[0365] In memory cell 420B, when transistor 51 is turned on, data is written to memory cell 420B through wiring 43a; when transistor 51 is turned off, the written data is retained. Therefore, in memory cell 420B, wiring 41a can be considered a write word line, and wiring 43a can be considered a write bit line. Furthermore, by controlling the potential of wiring 41d, the gate potential of transistor 52 changes due to capacitive coupling, thereby setting the potential of wiring 43b to correspond to the potential of the data held in memory cell 420B. Thus, the bit line drive circuit 413 can read the data held in memory cell 420B. Therefore, in memory cell 420B, wiring 41d can be considered a read word line, and wiring 43b can be considered a read bit line.

[0366] Storage cell 420C is a variation of storage cell 420B, wherein one of the source and drain terminals of transistor 52 is electrically connected to wiring 41d, and the other electrode of capacitor 57 is electrically connected to wiring 45. By controlling the potential of the other of the source and drain terminals of transistor 52 by word line drive circuit 411, storage cell 420C can output the data held in storage cell 420C to wiring 43b.

[0367] Memory cell 420D is a variation of memory cell 420C, the difference being that memory cell 420D includes transistor 53. Memory cell 420D is a 3Tr1C type memory cell.

[0368] The memory cell 420D is electrically connected to wirings 41a and 41b, which serve as wiring 41. Specifically, the gate of transistor 53 is electrically connected to wiring 41b. Additionally, one of the source and drain of transistor 52 is electrically connected to one of the source and drain of transistor 53. The other of the source and drain of transistor 52 is electrically connected to wiring 45. The other of the source and drain of transistor 53 is electrically connected to wiring 43b.

[0369] Transistor 53 is used as a switch, controlling the conduction and deconduction states of one of the source and drain terminals of transistor 52 with respect to wiring 43b based on the potential of wiring 41b. By turning transistor 53 on, the potential of wiring 43b can be set to the potential corresponding to the data held in memory cell 420D. Thus, bit line drive circuit 413 can read the data held in memory cell 420D. Therefore, in memory cell 420D, wiring 41b can be considered a read word line.

[0370] Memory cell 420E is a variation of memory cell 420D. The difference between memory cell 420E and memory cell 420D is that capacitor 57 is not provided. In memory cell 420E, wiring 45 is connected to another electrical connection between the source and drain of transistor 52.

[0371] For example, when the parasitic capacitance such as the gate capacitance of transistor 52 is sufficiently large, data can be retained in the memory cell even without capacitor 57.

[0372] As the transistor 51 included in memory cells 420A to 420E, an OS transistor is preferably used. As described above, the off-state current of an OS transistor is significantly small. Therefore, by using an OS transistor as transistor 51, the charge stored in capacitor 57 can be maintained for a long period of time. In addition, the gate potential of transistor 52 can be maintained for a long period of time. Therefore, data written to memory cell 420 can be maintained for a long period of time, so the frequency of refresh operations (writing data to memory cell 420 again) can be reduced. As a result, the power consumption of memory device 400 can be reduced.

[0373] Furthermore, transistors 52 and 53 are preferably OS transistors. As mentioned above, OS transistors have higher field-effect mobility, for example, compared to transistors using amorphous silicon. Therefore, by using OS transistors as transistors 51 to 53, the memory device 400 can be driven at high speed.

[0374] The memory cell 420A can be considered a DOSRAM (registered trademark). DOSRAM is short for "Dynamic Oxide Semiconductor Random Access Memory." DOSRAM indicates RAM including 1Tr1C type memory cells. DOSRAM is DRAM formed using OS transistors, and it is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current characteristic of OS transistors.

[0375] Storage cells 420B to 420E can be considered NOSRAM (a registered trademark). NOSRAM is short for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)". NOSRAM can be read without destroying the stored data (non-destructive read). Therefore, NOSRAM is suitable for computational processing that only involves a large number of repetitive data read operations.

[0376] <Structure Example of a Semiconductor Device 2> The following describes the structure of a part of it. Figure 4A1 and Figure 4B Examples of different transistor structures are shown below. Note that sometimes appropriate references to other transistors are omitted. Figure 4A1 and Figure 4B Explanation of repeated parts, etc.

[0377] exist Figure 4A1 In the present invention, when viewed from a planar perspective, both the Y-direction end and the -Y-direction end of the conductive layer 112 viewed from the opening 123 have regions overlapping with the conductive layer 111. That is, the Y-direction end of the conductive layer 112 viewed from the opening 123 is located inside the Y-direction end of the conductive layer 111 viewed from the opening 123, and the -Y-direction end of the conductive layer 112 viewed from the opening 123 is located inside the -Y-direction end of the conductive layer 111 viewed from the opening 123. However, one embodiment of the invention is not limited to this. Figure 40A In the example shown, when viewed from a plane, the end of conductive layer 112 in the Y-direction view from opening 123 does not overlap with conductive layer 111. That is, in Figure 40A In the example shown, the end of conductive layer 112 viewed from opening 123 in the Y direction is located outside the end of conductive layer 111 viewed from opening 123 in the Y direction. For example, in Figure 6 The transistor 52 shown has Figure 40A In the case of the structure shown, the end of the conductive layer 112b in the region that can be used as transistor 52 protrudes towards the conductive layer 115a side compared to the end of the conductive layer 111b.

[0378] exist Figure 40B In the example shown, when viewed from a plane, the end of the conductive layer 112 in the Y direction viewed from the opening 123 does not overlap with the conductive layer 111. That is, in Figure 40B In the example shown, the end of conductive layer 112 viewed from opening 123 in the Y direction is located outside the end of conductive layer 111 viewed from opening 123 in the Y direction. For example, in Figure 6 The transistor 51 shown has Figure 40B In the case of the structure shown, the end of the conductive layer 112a in the region that can be used as transistor 51 protrudes towards the region of the conductive layer 115a in the X direction compared to the end of the conductive layer 111a.

[0379] exist Figure 40C In the example shown, when viewed from a plane, both the Y-direction end and the -Y-direction end of the conductive layer 112 viewed from the opening 123 do not overlap with the conductive layer 111. That is, in Figure 40CIn the example shown, the end of the conductive layer 112 in the Y direction as viewed from the opening 123 is located outside the end of the conductive layer 111 in the Y direction as viewed from the opening 123, and the end of the conductive layer 112 in the -Y direction as viewed from the opening 123 is located outside the end of the conductive layer 111 in the -Y direction as viewed from the opening 123.

[0380] Note that regarding Figure 40A , Figure 40B and Figure 40C The cross-sectional view of the structure shown by the dashed lines A1-A2 can be referred to... Figure 4B .

[0381] Figure 41A yes Figure 4A1 The example of a deformed structure shown is as follows: Figure 41B yes Figure 41A The cross-sectional view of the dotted line A1-A2 shown. Figure 41A and Figure 41B An example is shown where the end of the conductive layer 115 in the X direction is located inside the end of the semiconductor layer 113, i.e., on the side of the opening 123. Figure 41A and Figure 41B In the example shown, semiconductor layer 113 has a region that does not overlap with conductive layer 115. By having this structure, the area of ​​the region where conductive layer 115 overlaps with conductive layer 112 can be reduced. This, in turn, reduces parasitic capacitance.

[0382] Figure 42A yes Figure 41A The example of a deformed structure shown is as follows: Figure 42B yes Figure 42A The cross-sectional view of the dotted line A1-A2 shown. Figure 42A and Figure 42B An example is shown where the end of the conductive layer 115 in the X direction is located inside the end of the conductive layer 112 on the side of the opening 123. Figure 42A and Figure 42B In the example shown, openings 121 and 123 have regions that do not overlap with conductive layer 115. This structure further reduces the area of ​​the region where conductive layer 115 overlaps with conductive layer 112. Consequently, parasitic capacitance can be further reduced.

[0383] Figure 43A yes Figure 4A1 The example of a deformed structure shown is as follows: Figure 43B1 yes Figure 43A The cross-sectional view of the dotted line A1-A2 shown. Figure 43A and Figure 43B1 An example is shown where, in the region where conductive layers 111 and 112 overlap, the end of conductive layer 115 in the X direction is located outside the end of conductive layer 112. Figure 43A and Figure 43B1In the example shown, conductive layer 115 covers the entire area where conductive layers 111 and 112 overlap. With this structure, for example, when forming conductive layer 115 using photolithography and etching, the alignment accuracy of the photomask can be reduced. Therefore, transistor 50 can be easily manufactured.

[0384] Figure 43B2 yes Figure 43B1 The illustrated modified example shows an instance where the top end of the insulating layer 105 coincides with or substantially coincides with the bottom end of the conductive layer 115. For example, when the conductive layer 115 is formed using photolithography and etching, sometimes a low etching selectivity between the conductive layer 115 and the insulating layer 105 results in… Figure 43B2 The structure shown.

[0385] Figure 43B3 yes Figure 43B2 The illustrated modified example shows an instance where the bottom end of the conductive layer 115 is located inside the top end of the insulating layer 105, i.e., on the side of the conductive layer 112. For example, when the etching rate of the conductive layer 115 in the X direction is faster than the etching rate of the insulating layer 105 in the X direction, sometimes this results in... Figure 43B3 The structure shown.

[0386] Note that regarding Figure 43B2 and Figure 43B3 The plan view of the structure shown can be referred to. Figure 43A .

[0387] Figure 44A and Figure 44B yes Figure 4A1 The illustrated example of a modified structure, wherein openings 121 and 123 are rectangles with rounded corners when viewed from a plane. Figure 44A This illustrates an example where the length of opening 121 and opening 123 in the X direction is longer than its length in the Y direction. Figure 44B Examples are shown where the length of openings 121 and 123 in the X direction is shorter than their length in the Y direction. Note that regarding... Figure 44A and Figure 44B The cross-sectional view of the structure shown can be referred to Figure 4B .

[0388] exist Figure 44A and Figure 44BIn the example shown, the sides of the insulating layer 103 in opening 121 and the sides of the conductive layer 112 in opening 123 have planar areas instead of curved surfaces. Therefore, the coverage of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 can be improved inside opening 121 and opening 123. Note that when viewed from a planar perspective, the corners of opening 121 and opening 123 may not be rounded; for example, the planar shapes of opening 121 and opening 123 may be rectangular, rhomboid, or square. Furthermore, the planar shapes of opening 121 and opening 123 may also be triangular or triangular with rounded corners. Moreover, the planar shapes of opening 121 and opening 123 may also be polygonal, such as pentagons, or polygons with rounded corners. The above can be applied to all structures shown in this specification, etc.

[0389] Figure 45A1 yes Figure 4A1 The illustrated modified example of the structure, wherein when viewed from a plane, the conductive layer 112 covers a portion of the outer periphery of the opening 121 but not the entirety. Figure 45A2 yes Figure 45A1 The illustrated modified example of the structure shows an end of the conductive layer 112 in contact with a point on the outer periphery of the opening 121 when viewed from a planar perspective. Figure 45A2 In the example shown, the opening 121 is circular when viewed from a plane, and one end of the extension of the conductive layer 112 in the Y direction is a tangent to the opening 121. Figure 45B yes Figure 45A1 and Figure 45A2 The cross-sectional view of the dotted line A1-A2 shown.

[0390] exist Figure 45A1 , Figure 45A2 and Figure 45B In the example shown, the area of ​​the region where conductive layer 112 and conductive layer 115 overlap can be reduced. This reduces parasitic capacitance. On the other hand, in Figure 4A1 and Figure 4B In the example shown, the width of the other region can be increased, either the source region or the drain region.

[0391] Figure 46A yes Figure 45A1 and Figure 45A2 The illustrated modified example of the structure is in which the conductive layer 112 does not cover the opening 121 when viewed from a plane, and the conductive layer 112 does not contact the opening 121. Figure 46B yes Figure 46A The cross-sectional view of the dotted line A1-A2 shown.

[0392] exist Figure 46A and Figure 46BIn the example shown, the area of ​​the region where conductive layer 112 overlaps with conductive layer 115 can be further reduced. This can further reduce parasitic capacitance.

[0393] Figure 47A yes Figure 4A1 The illustrated structure is a variation, in which the conductive layer 111 does not overlap entirely with the opening 121 but overlaps only with a portion of the opening 121. Figure 47B yes Figure 47A The cross-sectional view shown is the dotted-dotted line A1-A2. Figure 47A and Figure 47B In the example shown, the semiconductor layer 113 in the opening 121 has a region that does not overlap with the conductive layer 111.

[0394] exist Figure 47A and Figure 47B In the example shown, for instance, the parasitic capacitance formed between conductive layer 111 and conductive layer 115 can be reduced. On the other hand, in Figure 4A1 and Figure 4B In the example shown, the width of either the source region or the drain region can be increased.

[0395] Figure 48A yes Figure 47A The illustrated example of a modified structure, wherein openings 121 and 123 are rectangles with rounded corners when viewed from a plane. Figure 48B yes Figure 48A The cross-sectional view of the dotted line A1-A2 shown.

[0396] exist Figure 48A In the example shown, the sides of the insulating layer 103 in opening 121 and the sides of the insulating layer 103 in opening 123 have planar regions that are not curved. Therefore, the coverage of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 can be improved inside opening 121 and opening 123. Note that... Figure 48A An example is shown where the length of opening 121 and opening 123 in the X direction is longer than the length in the Y direction, but the length of opening 121 and opening 123 in the X direction may also be shorter than the length in the Y direction.

[0397] Figure 49A1 yes Figure 47A The illustrated modified example of the structure, wherein when viewed from a plane, the conductive layer 112 covers a portion of the outer periphery of the opening 121 but not the entirety. Figure 49A2 yes Figure 49A1 The illustrated modified example of the structure shows an end of the conductive layer 112 in contact with a point on the outer periphery of the opening 121 when viewed from a planar perspective. Figure 49A2In the example shown, the opening 121 is circular when viewed from a plane, and one end of the extension of the conductive layer 112 in the Y direction is a tangent to the opening 121. Figure 49B yes Figure 49A1 and Figure 49A2 The cross-sectional view of the dotted line A1-A2 shown.

[0398] exist Figure 49A1 , Figure 49A2 and Figure 49B In the example shown, the area of ​​the region where conductive layer 112 and conductive layer 115 overlap can be reduced. This reduces parasitic capacitance. On the other hand, in Figure 47A and Figure 47B In the example shown, the width of the other region can be increased, either the source region or the drain region.

[0399] Figure 50A yes Figure 49A1 and Figure 49A2 The illustrated example shows a variation of the structure in which the conductive layer 112 does not overlap with the opening 121. Figure 50B yes Figure 50A The cross-sectional view of the dotted line A1-A2 shown.

[0400] exist Figure 50A and Figure 50B In the example shown, the area of ​​the region where conductive layer 112 overlaps with conductive layer 115 can be further reduced. This can further reduce parasitic capacitance.

[0401] Figure 51A yes Figure 48A The illustrated modified example of the structure is shown in which a portion of one side of the opening 121 contacts the end of the conductive layer 112 when viewed from a plane, and the length of the opening 121 in the X direction is shorter than its length in the Y direction. Figure 51B yes Figure 51A The cross-sectional view of the dotted line A1-A2 shown.

[0402] exist Figure 51A and Figure 51B In the example shown, the area of ​​the region where conductive layer 112 and conductive layer 115 overlap can be reduced. This reduces parasitic capacitance. On the other hand, in Figure 48A and Figure 48B In the example shown, the width of the other region can be increased, either the source region or the drain region.

[0403] Figure 52A yes Figure 51A The illustrated example shows a variation of the structure, where the length of opening 121 in the X direction is longer than its length in the Y direction. Figure 52A In the example shown, when viewed from a plane, the entire side of opening 121 can contact the end of conductive layer 112.

[0404] Figure 52B yes Figure 52A The illustrated variation of the structure shows an example where, when viewed from the plane, a portion of one of the three sides of opening 121 contacts the end of conductive layer 112. Figure 52B In the example shown, when viewed from the plane, the entire side of the opening 121 on the side of the conductive layer 112 extending in the Y direction and a portion of the side extending in the X direction are covered by the conductive layer 112.

[0405] exist Figure 52B In the example shown, the width of the other region can be increased, either the source region or the drain region. On the other hand, in Figure 52A In the example shown, the area of ​​the overlapping region between conductive layer 112 and conductive layer 115 can be reduced, thereby reducing parasitic capacitance. Note that regarding Figure 52A and Figure 52B The cross-sectional view of the dotted line A1-A2 shown can be referred to... Figure 51B .

[0406] Figure 53A1 yes Figure 51A The illustrated modified example shows an example in which the conductive layer 112 does not cover the opening 121 when viewed from a plane, and the conductive layer 112 does not contact the opening 121. Figure 53A2 yes Figure 53A1 The illustrated example of a modified structure shows an example where the length of the opening 121 in the X direction is longer than the length in the Y direction. Figure 53B yes Figure 53A1 and Figure 53A2 The cross-sectional view of the dotted line A1-A2 shown.

[0407] exist Figure 53A1 , Figure 53A2 and Figure 53B In the example shown, the area of ​​the region where conductive layer 112 overlaps with conductive layer 115 can be further reduced. This can further reduce parasitic capacitance.

[0408] Figure 54A yes Figure 4A1 The illustrated example shows a variation of the structure, where the planar shape of opening 121 differs from that of opening 123. Figure 54A In the example shown, the planar shape of opening 123 is a circle with a radius greater than that of opening 121. Note that one or both of the planar shapes of opening 121 and opening 123 may not be circular. Specifically, one or both of the planar shapes of opening 121 and opening 123 may be a rectangle or other shapes with rounded corners. Figure 54B1 yes Figure 54A The cross-sectional view of the dotted line A1-A2 shown.

[0409] For example, when openings 121 and 123 are formed through different processes, openings 121 and 123 are sometimes... Figure 54A and Figure 54B1 The shape shown. Furthermore, even when openings 121 and 123 are formed using the same process, for example, when the etching rates of the conductive layer 112 in the X and Y directions differ from those of the insulating layer 103 in the X and Y directions, openings 121 and 123 may sometimes be... Figure 54A and Figure 54B1 The shape shown. For example, when the etching rate of the conductive layer 112 in the X and Y directions is faster than the etching rate of the insulating layer 103 in the X and Y directions, even if the openings 121 and 123 are formed through the same process, the openings 121 and 123 may sometimes be... Figure 54A and Figure 54B1 The shape shown.

[0410] Figure 54B2 yes Figure 54B1 The illustrated modified example shows an example of a region where the top surface of the semiconductor layer 113 contacts the conductive layer 112. For example, after forming an opening 121 in the insulating layer 103, the semiconductor layer 113 is formed, and then a film is deposited to form the conductive layer 112, in which the opening 123 is formed, thereby forming... Figure 54B2 The structure shown.

[0411] As described above, the channel width of transistor 50 can be equal to the length of the outer perimeter of opening 123 when viewed from a plane. Therefore, for example, when the area of ​​opening 123 is larger than the area of ​​opening 121, the channel width of transistor 50 can sometimes be extended. On the other hand, for example, when the area of ​​opening 123 is equal to the area of ​​opening 121, transistor 50 can sometimes be miniaturized.

[0412] Figure 55A It is shown Figure 54B1 An enlarged view of transistor 50 and an example of its surrounding structure. Figure 55B It is shown Figure 54B2 An enlarged view of transistor 50 and its surrounding structure. (See example.) Figure 55A and Figure 55B As shown, the side of the insulating layer 103a with opening 121 has a tapered portion 161a, and the side of the insulating layer 103b with opening 121 has a tapered portion 161b.

[0413] like Figure 55A and Figure 55BAs shown, the top end of the insulating layer 103a on the side of the opening 121 can be made to coincide with or substantially coincide with the bottom end of the insulating layer 103b on the side of the opening 121. Additionally, the cone angle of the tapered portion 161a can be equal to or substantially equal to the cone angle of the tapered portion 161b. Here, the cone angle of the side surface of the conductive layer 112 on the side of the opening 123 can be greater than or less than the cone angles of the tapered portions 161a and 161b. Furthermore, the cone angle of the side surface of the conductive layer 112 on the side of the opening 123 can be equal to or substantially equal to the cone angles of the tapered portions 161a and 161b.

[0414] Figure 56A and Figure 56B They are Figure 55A and Figure 55B The illustrated example shows a variation of the structure, where the cone angle of the tapered portion 161a differs from that of the tapered portion 161b. Figure 56A and Figure 56B In the diagram, a dashed line represents the straight line extending from the tapered portion 161b to one side of the insulating layer 103a. For example, if the materials of the insulating layer 103a and the insulating layer 103b are different, and thus the processability of the insulating layer 103a and the insulating layer 103b are different, the cone angle of the tapered portion 161a may be different from that of the tapered portion 161b.

[0415] Figure 56A and Figure 56B An example is shown where the cone angle of tapered portion 161a is smaller than that of tapered portion 161b. The cone angle of tapered portion 161a may also be larger than that of tapered portion 161b. Here, the cone angle of the side surface of the conductive layer 112 on the side of the opening 123 may be larger or smaller than the cone angle of tapered portion 161a, and may be larger or smaller than the cone angle of tapered portion 161b. Furthermore, the cone angle of the side surface of the conductive layer 112 on the side of the opening 123 may be equal to or approximately equal to the cone angle of tapered portion 161a, and may be equal to or approximately equal to the cone angle of tapered portion 161b.

[0416] Figure 57A and Figure 57B They are Figure 55A and Figure 55B The illustrated modified example shows an instance where the top end of the insulating layer 103a does not coincide with the bottom end of the insulating layer 103b. Specifically, it shows an instance where the end of the insulating layer 103b on the side of the opening 121 is located outside the end of the insulating layer 103a on the side of the opening 121. Figure 57A and Figure 57B In the insulating layer 103a, the opening 121 is called opening 121a, and the opening 121 in the insulating layer 103b is called opening 121b.

[0417] For example, when the etching rate in the X direction of insulating layer 103a differs from that of insulating layer 103b, sometimes the top end of insulating layer 103a and the bottom end of insulating layer 103b are not aligned. Specifically, when the etching rate in the X direction of insulating layer 103b is faster than that of insulating layer 103a, sometimes... Figure 57A and Figure 57B The structure shown. Here, the cone angle of the cone portion 161a and the cone angle of the cone portion 161b can be equal or approximately equal, or they can be different. Furthermore, the cone angle of the side surface of the conductive layer 112 on the side of the opening 123 can be greater or less than the cone angle of the cone portion 161a, and can be greater or less than the cone angle of the cone portion 161b. Moreover, the cone angle of the side surface of the conductive layer 112 on the side of the opening 123 can be equal or approximately equal to the cone angle of the cone portion 161a, and can also be equal or approximately equal to the cone angle of the cone portion 161b.

[0418] Reference Figures 55A to 57B The cone angles of the tapered portions 161a and 161b and the side of the conductive layer 112, as well as the positional relationships of the ends of the insulating layers 103a, 103b and the conductive layer 112, described herein can be applied to all structures shown in this specification.

[0419] Figure 58A yes Figure 4A1 The illustrated modified example of the structure shows an example in which the semiconductor layer 113 extends in the X direction beyond the end of the conductive layer 112 that is not facing the opening 123. Figure 58B yes Figure 58A The cross-sectional view of the dotted line A1-A2 shown.

[0420] exist Figure 58B In the example shown, when viewed from the XZ plane, the semiconductor layer 113 covers the end of the conductive layer 112 that does not face the opening 123. Additionally, the semiconductor layer 113 may have a region that contacts the top surface of the insulating layer 103.

[0421] Figure 59A yes Figure 4A1 A modified example of the structure is shown, in which the end of the semiconductor layer 113 in the Y direction is located outside the end of the conductive layer 112 and inside the end of the conductive layer 111. Figure 59A In the example shown, the end of the semiconductor layer 113 in the Y direction overlaps with the conductive layer 111 but not with the conductive layer 112.

[0422] Figure 59B yes Figure 4A1 The illustrated modified example shows an instance where the end of the semiconductor layer 113 in the Y direction is located outside the ends of the conductive layer 112 and the conductive layer 111. Figure 59B In the example shown, the end of semiconductor layer 113 in the Y direction does not overlap with conductive layers 111 and 112. Note that regarding... Figure 59A and Figure 59B The cross-sectional view of the dotted line A1-A2 shown can be referred to... Figure 4B .

[0423] Figure 60A yes Figure 4A1 The illustrated modified example of the structure shows an example in which transistor 50 includes two openings 121 and two openings 123, and they are arranged in the X direction. Figure 60B yes Figure 60A The cross-sectional view shown is along the dotted line A1-A2. In this description of a transistor 50 including a plurality of openings 121 and a plurality of openings 123, the X direction is sometimes referred to as the row direction, and the Y direction as the column direction.

[0424] exist Figure 60A and Figure 60B In this context, the two openings 121 are distinguished by being labeled as opening 121_1 and opening 121_2, respectively, and the two openings 123 are distinguished by being labeled as opening 123_1 and opening 123_2, respectively. Additionally, Figure 60A and Figure 60B Examples are shown where the semiconductor layer 113 disposed inside openings 121_1 and 123_1 differs from the semiconductor layer 113 disposed inside openings 121_2 and 123_2. These two semiconductor layers 113 are distinguished by being referred to as semiconductor layer 113_1 and semiconductor layer 113_2, respectively. The same description is sometimes used for the following figures.

[0425] Figure 61A yes Figure 60A The diagram shows a variation of the structure, in which two openings 121 and 123 are arranged in the Y direction. Figure 61B yes Figure 61A The illustrated structure is a variation, showing an example where an opening 121 and opening 123 are arranged to the right of two openings 121 and opening 123 arranged in the Y direction. Here, the two openings 121 and opening 123 arranged in the Y direction are placed in the first column, and one opening 121 and opening 123 is placed in the second column. In this case, for example, the center of the opening 121 and opening 123 in the second column can be located between the center of the upper opening 121 and opening 123 in the first column and the center of the lower opening 121 and opening 123 in the first column in the Y direction.

[0426] Figure 61C yes Figure 61AThe illustrated variation of the structure shows an example where two openings 121 and 123 arranged in the Y direction are provided on the left and right sides, with one opening 121 and one opening 123 on each side. Here, one opening 121 and one opening 123 are provided in the first and third columns, and two openings 121 and one opening 123 arranged in the Y direction are provided in the second column. In this case, for example, the center of the openings 121 and 123 in the first column and the center of the openings 121 and 123 in the third column can be located between the center of the upper opening 121 and one opening 123 in the second column and the center of the lower opening 121 and one opening 123 in the second column in the Y direction.

[0427] Figure 62A yes Figure 4A1 The example shown is a variation of the structure, in which four openings 121 and 123 are arranged in a matrix of two rows and two columns. Figure 62B yes Figure 60A The illustrated structure is a variation, showing an example where an opening 121 and opening 123 are positioned below two openings 121 and opening 123 arranged in the X direction. Here, the two openings 121 and opening 123 arranged in the X direction are placed in the first row, and one opening 121 and opening 123 is placed in the second row. In this case, for example, the center of the opening 121 and opening 123 in the second row can be located between the center of the opening 121 and opening 123 on the left side of the first row in the X direction and the center of the opening 121 and opening 123 on the right side of the first row.

[0428] Figure 62C yes Figure 62A The illustrated example of a modified structure shows two openings 121 and 123 on the lower side. Figure 62A Compared to the example closer to the right. In Figure 62C In the structure shown, the four openings 121 and 123 are arranged in a zigzag shape.

[0429] Figure 63A yes Figure 4A1 The example shown is a variation of the structure, in which nine openings 121 and 123 are arranged in a matrix of three rows and three columns. Figure 63B yes Figure 63A The illustrated example shows a variation of the structure, where two openings 121 and 123 are provided in the central center. Figure 63B In the example shown, the upward openings 121 and 123 are arranged in a zigzag pattern with the central openings 121 and 123. Additionally, in Figure 63B In the example shown, the downward openings 121 and 123 are arranged in a zigzag pattern with the central openings 121 and 123.

[0430] By increasing the number of openings 121 and 123 provided in transistor 50, the sum of the outer perimeters of openings 121 and 123 as viewed from a plane can sometimes be extended. As described above, the channel width of transistor 50 can, for example, be equal to the length of the outer perimeter of opening 123 as viewed from a plane. Thus, by providing multiple openings 121 and 123 in transistor 50, the channel width of transistor 50 can sometimes be extended. On the other hand, by reducing the number of openings 121 and 123 provided in transistor 50, transistor 50 can sometimes be manufactured more easily and miniaturized.

[0431] Figure 64A yes Figure 60A The illustrated modified example shows an example where the semiconductor layer 113 disposed inside openings 121_1 and 123_1 is the same as the semiconductor layer 113 disposed inside openings 121_2 and 123_2. That is, Figure 64A An example is shown where transistor 50 includes two openings 121, two openings 123, and a semiconductor layer 113. Figure 64B yes Figure 64A The cross-sectional view of the dotted line A1-A2 shown.

[0432] exist Figure 64A and Figure 64B In the structure shown, for example, when the semiconductor layer 113 is formed using photolithography and etching, the positional alignment accuracy of the photomask can be reduced. Therefore, the transistor 50 can be easily manufactured. On the other hand, in Figure 60A and Figure 60B In the structure shown, because the surface area of ​​the semiconductor layer 113 can be reduced, it is sometimes possible to suppress the incorporation of impurities into the semiconductor layer 113. Note that in Figures 61A to 63B In the structure shown, the semiconductor layer 113 can also be a single layer.

[0433] Figure 65A yes Figure 4A1 The illustrated modified example shows an example where conductive layer 112 extends in a direction parallel to conductive layer 115 and in a direction perpendicular to conductive layer 111. That is, in Figure 65A In the example shown, conductive layers 112 and 115 extend in the X direction, and conductive layer 111 extends in the Y direction. Figure 65B yes Figure 65A The cross-sectional view shown is the dotted-dash line A3-A4.

[0434] Figure 66 Is Figure 6 The illustrated structure is a modified example and is used as transistor 51 and transistor 52. Figure 65A The diagram shows an example of the structure of transistor 50. In Figure 66 In the example shown, the conductive layer 112a has a first region overlapping with openings 121a and 123a, a second region overlapping with opening 125a, and a region extending in the Y direction from the first region to the second region. On the other hand, in Figure 6 In the example shown, the conductive layer 112a has a region extending in the X direction from the first region to the second region.

[0435] exist Figure 65A In the present invention, when viewed from a planar perspective, both the Y-direction end of the conductive layer 115 viewed from the opening 123 and the -Y-direction end of the conductive layer 115 have regions overlapping with the conductive layer 112. That is, the Y-direction end of the conductive layer 115 viewed from the opening 123 is located inside the Y-direction end of the conductive layer 112 viewed from the opening 123, and the -Y-direction end of the conductive layer 115 viewed from the opening 123 is located inside the -Y-direction end of the conductive layer 112 viewed from the opening 123. However, one embodiment of the invention is not limited to this. Figure 67A In the example shown, when viewed from a plane, the end of the conductive layer 115 in the Y-direction view from the opening 123 does not overlap with the conductive layer 112. That is, in Figure 67A In the example shown, the end of the conductive layer 115 in the Y direction as viewed from the opening 123 is located outside the end of the conductive layer 112 in the Y direction as viewed from the opening 123.

[0436] exist Figure 67B In the example shown, when viewed from a plane, the end of the conductive layer 115 in the Y direction viewed from the opening 123 does not overlap with the conductive layer 112. That is, in Figure 67B In the example shown, the end of the conductive layer 115 in the Y direction as viewed from the opening 123 is located outside the end of the conductive layer 112 in the Y direction as viewed from the opening 123.

[0437] exist Figure 67C In the example shown, when viewed from a plane, both the Y-direction end and the -Y-direction end of the conductive layer 115 viewed from the opening 123 do not overlap with the conductive layer 112. That is, in Figure 67C In the example shown, the end of the conductive layer 115 in the Y direction as viewed from the opening 123 is located outside the end of the conductive layer 112 in the Y direction as viewed from the opening 123, and the end of the conductive layer 115 in the -Y direction as viewed from the opening 123 is located outside the end of the conductive layer 112 in the -Y direction as viewed from the opening 123.

[0438] Figure 68A yes Figure 65A Examples of variations of the structure shown. Figure 68A An example is shown where the end of the conductive layer 115 in the Y direction is located inside the end of the semiconductor layer 113, i.e., on the side of the opening 123. Figure 68A In the example shown, semiconductor layer 113 has a region that does not overlap with conductive layer 115. By having this structure, the area of ​​the region where conductive layer 115 overlaps with conductive layer 112 can be reduced. This, in turn, reduces parasitic capacitance.

[0439] Figure 68B yes Figure 68A Examples of variations of the structure shown. Figure 68B An example is shown where the end of the conductive layer 115 in the Y direction is located inside the end of the conductive layer 112 on the side of the opening 123. Figure 68B In the example shown, openings 121 and 123 have regions that do not overlap with conductive layer 115. This structure further reduces the area of ​​the region where conductive layer 115 overlaps with conductive layer 112. Consequently, parasitic capacitance can be further reduced.

[0440] Note, regarding Figure 67A , Figure 67B , Figure 67C , Figure 68A and Figure 68B The cross-sectional view of the dotted-dash line A3-A4 shown can be referenced. Figure 65B .

[0441] Figure 69A yes Figure 65A The illustrated structure is a variation, in which the conductive layer 111 does not overlap entirely with the opening 121 but overlaps only with a portion of the opening 121. Figure 69B yes Figure 69A The cross-sectional view shown is along the dashed-dot line A3-A4. Figure 69A and Figure 69B In the example shown, the semiconductor layer 113 in the opening 121 has a region that does not overlap with the conductive layer 111.

[0442] exist Figure 69A and Figure 69B In the example shown, for instance, the parasitic capacitance formed between conductive layer 111 and conductive layer 115 can be reduced. On the other hand, in Figure 65A and Figure 65B In the example shown, the width of either the source region or the drain region can be increased.

[0443] Figure 70A1 yes Figure 69A The illustrated example of a modified structure shows an example in which the conductive layer 112 covers a portion of the outer periphery of the opening 121 but not the entirety when viewed from a plane. Figure 70A2 yes Figure 70A1 The illustrated modified example of the structure shows an end of the conductive layer 112 in contact with a point on the outer periphery of the opening 121 when viewed from a planar perspective. Figure 70A2In the example shown, when viewed from a plane, the opening 121 is circular and one end of the conductive layer 112 extending in the Y direction is the tangent of the opening 121. Figure 70B yes Figure 70A1 and Figure 70A2 The cross-sectional view shown is the dotted-dash line A3-A4.

[0444] exist Figure 70A1 , Figure 70A2 and Figure 70B In the example shown, the area of ​​the region where conductive layer 112 and conductive layer 115 overlap can be reduced. This reduces parasitic capacitance. On the other hand, in Figure 69A and Figure 69B In the example shown, the width of the other region can be increased, either the source region or the drain region.

[0445] Figure 71A yes Figure 70A1 and Figure 70A2 The illustrated example shows a variation of the structure in which the conductive layer 112 does not overlap with the opening 121. Figure 71B yes Figure 71A The cross-sectional view shown is the dotted-dash line A3-A4.

[0446] exist Figure 71A and Figure 71B In the example shown, the area of ​​the region where conductive layer 112 overlaps with conductive layer 115 can be further reduced. This can further reduce parasitic capacitance.

[0447] Figure 72A yes Figure 65A The illustrated modified example of the structure shows an example in which the semiconductor layer 113 extends in the X direction beyond the end of the conductive layer 112 that is not facing the opening 123. Figure 72B yes Figure 72A The cross-sectional view shown is the dotted-dash line A3-A4.

[0448] exist Figure 72B In the example shown, when viewed from the XZ plane, the semiconductor layer 113 covers the end of the conductive layer 112 that does not face the opening 123. Additionally, the semiconductor layer 113 may have a region that contacts the top surface of the insulating layer 103.

[0449] Figure 73A yes Figure 65A The illustrated modified example of the structure shows an example in which transistor 50 includes two openings 121 and two openings 123, and they are arranged in the X direction. Figure 73B yes Figure 73A The cross-sectional view shown is the dotted-dash line A3-A4.

[0450] Figure 74A yes Figure 73AThe diagram shows a variation of the structure, in which two openings 121 and 123 are arranged in the Y direction. Figure 74B yes Figure 74A The illustrated structure is a variation, showing an example where an opening 121 and opening 123 are arranged to the right of two openings 121 and opening 123 arranged in the Y direction. Here, the two openings 121 and opening 123 arranged in the Y direction are placed in the first column, and one opening 121 and opening 123 is placed in the second column. In this case, for example, the center of the opening 121 and opening 123 in the second column can be located between the center of the upper opening 121 and opening 123 in the first column and the center of the lower opening 121 and opening 123 in the first column in the Y direction.

[0451] Figure 74C yes Figure 74A The illustrated modified example of the structure shows two openings 121 and 123 arranged in the Y direction, with one opening 121 and one opening 123 respectively provided on the left and right sides. Here, one opening 121 and one opening 123 are provided in the first and third columns, and the two openings 121 and one opening 123 arranged in the Y direction are provided in the second column. In this case, for example, the center of the openings 121 and 123 in the first column and the center of the openings 121 and 123 in the third column can be located between the center of the upper opening 121 and one opening 123 in the second column in the Y direction and the center of the lower opening 121 and one opening 123 in the second column.

[0452] Figure 75A yes Figure 65A The example shown is a variation of the structure, in which four openings 121 and 123 are arranged in a matrix of two rows and two columns. Figure 75B yes Figure 73A The illustrated structure is a variation, showing an example where an opening 121 and opening 123 are positioned below two openings 121 and opening 123 arranged in the X direction. Here, the two openings 121 and opening 123 arranged in the X direction are placed in the first row, and one opening 121 and opening 123 is placed in the second row. In this case, for example, the center of the opening 121 and opening 123 in the second row can be located between the center of the opening 121 and opening 123 on the left side of the first row in the X direction and the center of the opening 121 and opening 123 on the right side of the first row.

[0453] Figure 75C yes Figure 75A The illustrated example of a modified structure shows two openings 121 and 123 on the lower side. Figure 75A Compared to the example closer to the right. In Figure 75C In the structure shown, the four openings 121 and 123 are arranged in a zigzag shape.

[0454] Figure 76A yes Figure 65A The example shown is a variation of the structure, in which nine openings 121 and 123 are arranged in a matrix of three rows and three columns. Figure 76B yes Figure 76A The illustrated example shows a variation of the structure, where two openings 121 and 123 are provided in the central center. Figure 76B In the example shown, the upward openings 121 and 123 are arranged in a zigzag pattern with the central openings 121 and 123. Additionally, in Figure 76B In the example shown, the downward openings 121 and 123 are arranged in a zigzag pattern with the central openings 121 and 123.

[0455] As described above, by increasing the number of openings 121 and 123 provided in the transistor 50, the total length of the outer perimeter of the openings 121 and 123 as viewed from a planar surface can sometimes be extended. As described above, the channel width of the transistor 50 can, for example, be equal to the length of the outer perimeter of the openings 123 as viewed from a planar surface; thus, by providing multiple openings 121 and 123 in the transistor 50, the channel width of the transistor 50 can sometimes be extended. On the other hand, by reducing the number of openings 121 and 123 provided in the transistor 50, the transistor 50 can sometimes be manufactured more easily and miniaturized.

[0456] Figure 77A yes Figure 73A The illustrated modified example shows an example where the semiconductor layer 113 disposed inside openings 121_1 and 123_1 is the same as the semiconductor layer 113 disposed inside openings 121_2 and 123_2. That is, Figure 77A An example is shown where transistor 50 includes two openings 121, two openings 123, and a semiconductor layer 113. Figure 77B yes Figure 77A The cross-sectional view shown is the dotted-dash line A3-A4.

[0457] exist Figure 77A and Figure 77B In the structure shown, for example, when the semiconductor layer 113 is formed using photolithography and etching, the positional alignment accuracy of the photomask can be reduced. Therefore, the transistor 50 can be easily manufactured. On the other hand, in Figure 73A and Figure 73B In the structure shown, because the surface area of ​​the semiconductor layer 113 can be reduced, it is sometimes possible to suppress the incorporation of impurities into the semiconductor layer 113. Note that in Figures 74A to 76B In the structure shown, the semiconductor layer 113 can also be a single layer.

[0458] <Example 1 of a manufacturing method for a display device> Hereinafter, a method for manufacturing a display device according to one aspect of the present invention will be described with reference to the accompanying drawings. Herein, it is used to describe a method for manufacturing a display device according to one aspect of the present invention. Figure 4A1 and Figure 4B The manufacturing method of the display device with the transistor 50 shown is described using an example.

[0459] Note that the thin films (insulating films, semiconductor films, and conductive films, etc.) constituting the display device can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), or algebraic laser deposition (ALD). CVD methods include PECVD and thermal CVD. Furthermore, as a type of thermal CVD, metal-organic chemical vapor deposition (MOCVD) is also used.

[0460] In addition, the thin films (insulating films, semiconductor films, and conductive films, etc.) constituting the display device can sometimes be formed using methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor knife coating.

[0461] In the processing of the aforementioned thin films, for example, the film can be etched according to the pattern of the photoresist mask after forming it using photolithography. Alternatively, the film can be processed using nanoimprint lithography, sandblasting, or lift-off methods. Furthermore, island-shaped thin films can be directly formed using deposition methods that employ masking techniques such as metal masks. Additionally, photosensitive thin films can be processed by exposure and development. In other words, photosensitive thin films can be processed using photolithography.

[0462] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be used. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferred because they allow for extremely fine processing. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0463] As a method for etching thin films, dry etching or wet etching can be used.

[0464] Figures 78A1 to 81B2 The figures shown are for illustration. Figure 4A1 and Figure 4B The diagram shows the manufacturing method of the structure. A1 and B1 in each figure are plan views, and A2 and B2 in each figure are cross-sectional views of the dashed line A1-A2 shown in each plan view.

[0465] [Formation of conductive layer 111] A conductive film, serving as a conductive layer 111, is formed on a substrate 101. This conductive film can be formed, for example, by sputtering. After forming a photoresist mask on the conductive film using a photolithography process, the conductive film is processed to form an island-shaped conductive layer 111 that serves as one of the source and drain electrodes. Figure 78A1 and Figure 78A2 When processing this conductive film, one or both of wet etching and dry etching methods can be used.

[0466] [Formation of insulating layer 103a and insulating layer 103b] Next, insulating layers 103a and 103b are formed on substrate 101 and conductive layer 111. Figure 78B1 and Figure 78B2 The insulating layers 103a and 103b can be formed, for example, by PECVD. Preferably, after the formation of insulating layer 103a, insulating layer 103b is continuously formed in a vacuum in a manner that prevents the surface of insulating layer 103a from being exposed to the atmosphere. By continuously forming insulating layers 103a and 103b, impurities originating from the atmosphere that adhere to the surface of insulating layer 103a can be suppressed. Examples of such impurities include water and organic matter.

[0467] The substrate temperature during the formation of insulating layers 103a and 103b is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. By keeping the substrate temperature during the formation of insulating layers 103a and 103b within the above range, the release of impurities (e.g., water and hydrogen) from the insulating layers 103a and 103b themselves can be reduced, thereby suppressing the diffusion of impurities into the semiconductor layer 113 to be formed in subsequent processes. Therefore, transistors exhibiting good electrical characteristics and high reliability can be manufactured.

[0468] As described above, insulating layers 103a and 103b are formed before semiconductor layer 113 is formed. Therefore, there is no need to worry about oxygen being removed from semiconductor layer 113 due to the heat applied during the formation of insulating layers 103a and 103b.

[0469] Alternatively, heat treatment can be performed after the insulating layers 103a and 103b are formed. By performing heat treatment, water and hydrogen can be removed from the surface and film of the insulating layers 103a and 103b.

[0470] The heat treatment temperature is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more rare gases, nitrogen, and oxygen. Dry air (CDA) can also be used as a nitrogen-containing or oxygen-containing atmosphere. Note that the content of hydrogen and water in this atmosphere is preferably as low as possible. As this atmosphere, a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is preferred. By using an atmosphere with the lowest possible content of hydrogen and water, the absorption of hydrogen and water by insulating layers 103a and 103b can be prevented as much as possible. The heat treatment can be performed using an oven or a rapid thermal annealing (RTA) apparatus. By using an RTA apparatus, the heat treatment time can be shortened.

[0471] [Formation of conductive film 112f] Next, a conductive film 112f, which will become the conductive layer 112 in subsequent processes, is formed on the insulating layer 103b. Figure 79A1 and Figure 79A2 The conductive film 112f can be formed, for example, by sputtering.

[0472] [The formation of openings 121 and 123] Next, a portion of the conductive film 112f in the region overlapping with the conductive layer 111 is removed to form a conductive layer 112A including the opening 123. Figure 79B1 and Figure 79B2 The opening 123 can be formed using one or both of wet etching and dry etching, wherein wet etching may be used appropriately.

[0473] Next, a portion of the insulating layer 103 (insulating layer 103a and insulating layer 103b) in the region overlapping with the conductive layer 111 is removed. This forms an opening 121 in the insulating layer 103. Figure 79B1 and Figure 79B2 The opening 121 can be formed using one or both of wet etching and dry etching, wherein dry etching may be used appropriately.

[0474] The opening 123 can be formed, for example, using the same photoresist mask used to form the opening 121. Specifically, a photoresist mask is formed on the conductive film 112f, and the conductive film 112f can be removed using the photoresist mask to form the opening 123. The insulating layer 103 can also be removed using the same photoresist mask to form the opening 121. Note that by processing the width of the opening 123 to be larger than the width of the photoresist mask, it is possible to manufacture... Figure 54A and Figure 54B1 The transistor 50 shown has an opening 123 with a width greater than the opening 121. Here, for example, in the case of manufacturing a transistor 50 where the width of the opening 123 is different from the width of the opening 121, the opening 121 may also be formed using a resist mask different from the resist mask used to form the opening 123.

[0475] [Formation of conductive layer 112] Next, the conductive layer 112A is processed into the desired shape, thereby forming the conductive layer 112. Figure 80A1 and Figure 80A2 The conductive layer 112 can be formed using one or both of wet etching and dry etching, wherein wet etching may be used appropriately.

[0476] [Formation of semiconductor layer 113] Next, a semiconductor film 113f is formed as a semiconductor layer 113 in a manner that covers openings 121 and 123. Figure 80B1 and Figure 80B2 The semiconductor film 113f can be disposed in such a manner that it has a region in contact with the top and side surfaces of the conductive layer 112, the top and side surfaces of the insulating layer 103, and the top surface of the conductive layer 111.

[0477] The semiconductor film 113f is preferably formed by sputtering using a metal oxide target.

[0478] The semiconductor film 113f is preferably a dense film with as few defects as possible. The purity of the semiconductor film 113f is preferably high, wherein hydrogen-containing impurities are minimized. In particular, a crystalline metal oxide film is preferably used as the semiconductor film 113f.

[0479] Oxygen gas is preferably used when forming the semiconductor film 113f. By using oxygen gas when forming the semiconductor film 113f, oxygen can be appropriately supplied to the insulating layer 103. For example, when an oxide is used in the insulating layer 103a, oxygen can be appropriately supplied to the insulating layer 103a by using oxygen gas when forming the semiconductor film 113f.

[0480] By supplying oxygen to the insulating layer 103a and then to the semiconductor layer 113 in a subsequent process, the oxygen vacancies (V) in the semiconductor layer 113 can be reduced.O ) and V O H.

[0481] When depositing the semiconductor film 113f, oxygen gas and inactive gases (e.g., helium, argon, or xenon) can also be mixed. Note that the higher the proportion of oxygen gas in the overall deposition gas (oxygen flow ratio) during semiconductor film 113f deposition, the higher the crystallinity of the semiconductor film 113f can be, enabling the realization of transistors with high reliability. Conversely, the lower the oxygen flow ratio, the lower the crystallinity of the semiconductor film 113f, enabling the realization of transistors with high on-state current.

[0482] When the substrate temperature is high during the formation of the semiconductor film 113f, a semiconductor film 113f with higher crystallinity and greater density can be formed. On the other hand, when the substrate temperature is low, a semiconductor film 113f with lower crystallinity and higher conductivity can be formed.

[0483] The substrate temperature for forming the semiconductor film 113f is above room temperature and below 250°C, preferably above room temperature and below 200°C, and more preferably above room temperature and below 140°C. For example, the substrate temperature is preferably above room temperature and below 140°C, which improves productivity. In addition, by depositing the semiconductor film 113f at room temperature or without heating the substrate, crystallinity can be reduced.

[0484] Before depositing the semiconductor film 113f, it is preferable to perform at least one of a treatment to remove water, hydrogen, organic matter, etc., adsorbed on the surface of the insulating layer 103 and a treatment to supply oxygen to the insulating layer 103. For example, a heating treatment can be performed at a temperature of 70°C or higher and 200°C or lower under a reduced pressure atmosphere. Alternatively, a plasma treatment in an oxygen-containing atmosphere can be performed. Alternatively, oxygen can be supplied to the insulating layer 103 by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). When performing a plasma treatment containing nitrous oxide gas, organic matter on the surface of the insulating layer 103 can be appropriately removed and oxygen can be supplied to the insulating layer 103. Preferably, after such treatment, the semiconductor film 113f is continuously deposited in a manner that does not expose the surface of the insulating layer 103 to the atmosphere.

[0485] Note that when the semiconductor layer 113 has a stacked structure, it is preferable to deposit the upper metal oxide film continuously after depositing the lower metal oxide film in a manner that does not expose its surface to the atmosphere.

[0486] Next, the semiconductor film 113f is processed into islands to form the semiconductor layer 113. Figure 81A1 and Figure 81A2 ).

[0487] The semiconductor layer 113 can be formed using one or both of wet etching and dry etching, with wet etching being a suitable method. In this case, sometimes a portion of the conductive layer 112 in a region that does not overlap with the semiconductor layer 113 is etched, resulting in a reduced thickness. Similarly, sometimes a portion of the insulating layer 103 in a region that does not overlap with either the semiconductor layer 113 or the conductive layer 112 is etched, resulting in a reduced thickness. For example, sometimes the insulating layer 103b in the insulating layer 103 disappears due to etching, exposing the surface of the insulating layer 103a. Note that by using a material with a high etch selectivity ratio to the semiconductor film 113f as the insulating layer 103b, the reduction in the thickness of the insulating layer 103b can be suppressed.

[0488] Preferably, heat treatment is performed after depositing the semiconductor film 113f or processing the semiconductor film 113f into a semiconductor layer 113. Heat treatment can remove hydrogen and water contained in or adsorbed on the surface of the semiconductor film 113f or semiconductor layer 113. Furthermore, heat treatment can sometimes improve the film quality of the semiconductor film 113f or semiconductor layer 113; for example, it can sometimes reduce defects in the semiconductor film 113f or semiconductor layer 113 and improve the crystallinity of the semiconductor film 113f or semiconductor layer 113.

[0489] Oxygen can be supplied from the insulating layer 103a to the semiconductor film 113f or the semiconductor layer 113 through heat treatment. More preferably, the heat treatment is performed before processing into the semiconductor layer 113. Details regarding the heat treatment can be found above, so further explanation is omitted.

[0490] Note that this heat treatment can be omitted if not required. Alternatively, the heat treatment performed in a later step can be used instead of this step. Sometimes, for example, the high-temperature treatment in a later step such as a deposition process can be used as this heat treatment.

[0491] [Formation of insulating layer 105] Next, an insulating layer 105 is formed in such a manner that it covers the semiconductor layer 113, the conductive layer 112, and the insulating layer 103. Figure 81B1 and Figure 81B2 The insulating layer 105 can be formed using the PECVD method.

[0492] When an oxide semiconductor is used in the semiconductor layer 113, the insulating layer 105 is preferably used as a barrier film to suppress oxygen diffusion. By giving the insulating layer 105 the function of suppressing oxygen diffusion, oxygen can be prevented from diffusing from the top of the insulating layer 105 to the conductive layer 115 formed in a subsequent process, thus preventing the conductive layer 115 from being oxidized. As a result, transistors exhibiting good electrical characteristics and high reliability can be manufactured.

[0493] By increasing the formation temperature of the insulating layer 105, which serves as the gate insulating layer, an insulating layer with fewer defects can be formed. However, when the formation temperature of the insulating layer 105 is high, oxygen escapes from the semiconductor layer 113, and sometimes oxygen vacancies (V) in the semiconductor layer 113... O ) and V O H increases. The substrate temperature during the formation of the insulating layer 105 is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and even more preferably 300°C or higher and 400°C or lower. By keeping the substrate temperature during the formation of the insulating layer 105 within the above range, defects in the insulating layer 105 can be reduced while oxygen detachment from the semiconductor layer 113 can be suppressed. Therefore, transistors exhibiting good electrical characteristics and high reliability can be manufactured.

[0494] Plasma treatment can be performed on the surface of the semiconductor layer 113 before forming the insulating layer 105. This plasma treatment reduces impurities such as water adsorbed on the surface of the semiconductor layer 113. Therefore, impurities at the interface between the semiconductor layer 113 and the insulating layer 105 can be reduced, resulting in a transistor with high reliability. In particular, plasma treatment is preferred when the surface of the semiconductor layer 113 is exposed to the atmosphere between the formation of the semiconductor layer 113 and the formation of the insulating layer 105. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, the plasma treatment and the deposition of the insulating layer 105 are preferably performed continuously without exposure to the atmosphere.

[0495] [Formation of conductive layer 115] Next, a conductive film, which becomes a conductive layer 115, is formed on the insulating layer 105. This conductive film can be formed, for example, by sputtering. After forming a resist mask on the conductive film using a photolithography process, the conductive film is processed, thereby forming an island-shaped conductive layer 115 that serves as a gate electrode.

[0496] Through the above processes, it is possible to manufacture Figure 4A1 and Figure 4B The transistor 50 shown.

[0497] <Example 2 of a manufacturing method for a display device> A manufacturing method different from the manufacturing method of the transistor 50 shown in <Example 1 of the manufacturing method of the display device> will be described. Note that descriptions that are repeated above are omitted, and the different content will be described.

[0498] Figure 82A1 , Figure 82A2 , Figure 82B1 and Figure 82B2 This is an explanation Figure 4A1 and Figure 4B A diagram illustrating the manufacturing method of the structure shown. Figure 82A1 and Figure 82B1 It's a floor plan. Figure 82A2 and Figure 82B2 They are Figure 82A1 and Figure 82B1 The cross-sectional view of the dotted line A1-A2 shown.

[0499] First, the formation of the conductive film 112f is performed in the same manner as in <Example 1 of the manufacturing method of the display device>. Since the formation of the conductive film 112f can be referred to... Figures 78A1 to 79A2 The explanation is omitted here.

[0500] Next, conductive film 112f is processed to form conductive layer 112B. Figure 82A1 and Figure 82A2 Alternatively, the opening 123 may not be formed in the conductive layer 112B. The conductive layer 112B may be formed using, for example, one or both of wet etching and dry etching, wherein wet etching may be suitably used.

[0501] Next, at least a portion of the conductive layer 112B in the region overlapping with the conductive layer 111 is removed to form a conductive layer 112 including the opening 123.

[0502] Next, at least a portion of the insulating layer 103 (insulating layer 103a and insulating layer 103b) in the region overlapping with the conductive layer 111 is removed. This forms an opening 121 in the insulating layer 103. Figure 82B1 and Figure 82B2 ).

[0503] Since the formation of openings 121 and 123 can be referred to in <Example 1 of the manufacturing method of display device>, their detailed descriptions are omitted.

[0504] Next, a semiconductor film 113f is formed as a semiconductor layer 113 in a manner that covers openings 121 and 123. Figure 80B1 and Figure 80B2 Regarding the processes following the formation of the semiconductor film 113f, please refer to the description in <Example 1 of the Manufacturing Method of Display Device> above, so detailed explanations are omitted.

[0505] Through the above processes, it is possible to manufacture Figure 4A1 and Figure 4B The transistor 50 shown has the following structure.

[0506] The various structural examples shown in this embodiment can be appropriately combined. Furthermore, this embodiment can be appropriately combined with other embodiments.

[0507] (Implementation Method 2) In this embodiment, refer to Figures 83A to 83G and Figures 84A to 84K This invention describes a display device according to one aspect of the present invention.

[0508] There are no particular restrictions on the arrangement of subpixels, and various methods can be used. Examples of subpixel arrangements include stripe arrangements, S-stripes, matrix arrangements, Delta arrangements, Bayer arrangements, and Pentile arrangements.

[0509] The planar shape of the sub-pixel shown in the accompanying drawings in this embodiment corresponds to the planar shape of the light-emitting area (or light-receiving area).

[0510] In addition, the planar shapes of sub-pixels can include, for example, triangles, quadrilaterals (including rectangles and squares), pentagons and other polygonal shapes, the aforementioned polygonal shapes with rounded corners, ellipses or circles, etc.

[0511] The circuit layout constituting the sub-pixel is not limited to the range of the sub-pixel shown in the attached figure, and can also be arranged outside of it.

[0512] Figure 83A The pixel 21 shown is arranged in an S-strip pattern. Figure 83A The pixel 21 shown is composed of three sub-pixels: sub-pixel 23a, sub-pixel 23b, and sub-pixel 23c.

[0513] Figure 83B The pixel 21 shown includes sub-pixels 23a and 23b, which have planar shapes with rounded corners and approximate trapezoidal or triangular shapes, and sub-pixel 23c, which has planar shapes with rounded corners and approximate quadrilateral or hexagonal shapes. Furthermore, the light-emitting area of ​​sub-pixel 23b is larger than that of sub-pixel 23a. Thus, the shape and size of each sub-pixel can be determined independently. For example, the size of a sub-pixel including a highly reliable light-emitting element can be smaller.

[0514] Figure 83C Pixels 21a and 21b shown are arranged in a Pentile pattern. Figure 83C Examples are shown of pixel 21a, which includes sub-pixels 23a and 23b, and pixel 21b, which includes sub-pixels 23b and 23c, with alternating configurations.

[0515] Figures 83D to 83FPixels 21a and 21b are arranged in a Delta pattern. Pixel 21a includes two sub-pixels (sub-pixels 23a and 23b) in the upper row (first row) and one sub-pixel (sub-pixel 23c) in the lower row (second row). Pixel 21b includes one sub-pixel (sub-pixel 23c) in the upper row (first row) and two sub-pixels (sub-pixels 23a and 23b) in the lower row (second row).

[0516] Figure 83D It is an example of a planar shape where each sub-pixel has an approximately quadrilateral shape with rounded corners. Figure 83E This is an example where each sub-pixel has a circular planar shape. Figure 83F It is an example of a planar shape in which each sub-pixel has an approximately hexagonal shape with rounded corners.

[0517] exist Figure 83F In this configuration, each subpixel is positioned inside the densest hexagonal region. Each subpixel is arranged such that it is surrounded by six subpixels when focusing on one of them. Furthermore, subpixels that emit the same color of light are not adjacent to each other. For example, each subpixel is arranged such that three subpixels 23b and three subpixels 23c are alternately arranged around subpixel 23a when focusing on it.

[0518] Figure 83G An example is shown where the subpixels of each color are configured in a jagged shape. Specifically, when viewed from a plane, the upper positions of two subpixels arranged in the column direction (e.g., subpixels 23a and 23b, or subpixels 23b and 23c) are offset.

[0519] exist Figures 83A to 83G In the pixels shown, preferably, sub-pixel 23a is a sub-pixel R emitting red light, sub-pixel 23b is a sub-pixel G emitting green light, and sub-pixel 23c is a sub-pixel B emitting blue light. Note that the structure of the sub-pixels is not limited to this, and the color emitted and the arrangement order of the sub-pixels can be appropriately determined. For example, sub-pixel 23b could also be a sub-pixel R emitting red light, and sub-pixel 23a could also be a sub-pixel G emitting green light.

[0520] In photolithography, the finer the pattern being processed, the more significant the effect of light diffraction becomes. Therefore, when transferring the photomask pattern through exposure, its fidelity decreases, making it difficult to process the resist mask into the desired shape. Consequently, even if the photomask pattern is rectangular, it is easy to form a pattern with rounded corners. Thus, the planar shape of subpixels sometimes exhibits rounded corners, polygonal shapes, ellipses, or circles, etc.

[0521] To ensure that the planar shape of the subpixels is the desired shape, a technique for pre-correcting the mask pattern (OPC (Optical Proximity Correction) technique) can be used, in which the design pattern and the transfer pattern are consistent. Specifically, in the OPC technique, for example, correction patterns are added to the corners of the pattern on the mask pattern.

[0522] like Figures 84A to 84I As shown, a pixel can include four types of sub-pixels.

[0523] Figures 84A to 84C The pixel 21 shown is arranged in stripes.

[0524] Figure 84A This is an example where each sub-pixel has a rectangular planar shape. Figure 84B This is an example where each sub-pixel has a planar shape connecting two semicircles and a rectangle. Figure 84C This is an example where each sub-pixel has an elliptical planar shape.

[0525] Figures 84D to 84F The pixels 21 shown are arranged in a matrix.

[0526] Figure 84D This is an example where each sub-pixel has a square planar shape. Figure 84E This is an example of a planar shape where each sub-pixel has a rounded corner and is approximately square. Figure 84F This is an example where each sub-pixel has a circular planar shape.

[0527] Figure 84G and Figure 84H This shows an example of a pixel 21 arranged in two rows and three columns.

[0528] Figure 84G The pixel 21 shown includes three sub-pixels (sub-pixels 23a, 23b, and 23c) in the top row (first row) and one sub-pixel (sub-pixel 23d) in the bottom row (second row). In other words, pixel 21 includes sub-pixel 23a in the left column (first column), sub-pixel 23b in the middle column (second column), sub-pixel 23c in the right column (third column), and sub-pixel 23d spanning these three columns.

[0529] Figure 84H The pixel 21 shown includes three sub-pixels (sub-pixels 23a, 23b, and 23c) in the top row (first row) and three sub-pixels 23d in the bottom row (second row). In other words, pixel 21 includes sub-pixels 23a and 23d in the left column (first column), sub-pixels 23b and 23d in the middle column (second column), and sub-pixels 23c and 23d in the right column (third column). Figure 84HAs shown, by employing a structure that aligns the configuration of the up and down subpixels, dust that may be generated during the manufacturing process can be efficiently removed, for example. Therefore, a display device with high display quality can be provided.

[0530] Figure 84I This shows an example of a pixel 21 arranged in three rows and two columns.

[0531] Figure 84I The pixel 21 shown includes sub-pixel 23a in the top row (first row), sub-pixel 23b in the middle row (second row), sub-pixel 23c spanning from the first row to the second row, and sub-pixel 23d in the bottom row (third row). In other words, pixel 21 includes sub-pixels 23a and 23b in the left column (first column), sub-pixel 23c in the right column (second column), and sub-pixel 23d spanning both columns.

[0532] Figures 84A to 84I The pixel 21 shown is composed of four sub-pixels: sub-pixels 23a, 23b, 23c, and 23d.

[0533] Subpixels 23a, 23b, 23c, and 23d may include light-emitting elements that emit light of different colors from each other. Examples of subpixels 23a, 23b, 23c, and 23d include: subpixels of four colors: R, G, B, and white (W); subpixels of four colors: R, G, B, and Y; or subpixels of R, G, B, and infrared (IR); etc.

[0534] exist Figures 84A to 84I In each of the pixels 21 shown, preferably, for example, sub-pixel 23a is sub-pixel R emitting red light, sub-pixel 23b is sub-pixel G emitting green light, sub-pixel 23c is sub-pixel B emitting blue light, and sub-pixel 23d is sub-pixel W emitting white light, sub-pixel Y emitting yellow light, or sub-pixel IR emitting near-infrared light. When employing the above structure, in Figure 84G and Figure 84H In pixel 21 shown, the R, G, and B pixels are arranged in a stripe pattern, which improves display quality. Additionally, in Figure 84I In the pixel 21 shown, the layout of R, G, and B is a so-called S-striped arrangement, which can improve the display quality.

[0535] Pixel 21 may also include sub-pixels with light-receiving elements.

[0536] exist Figures 84A to 84I In each of the pixels 21 shown, any one of the sub-pixels 23a to 23d can also be a sub-pixel that includes a light-receiving element.

[0537] exist Figures 84A to 84I In each of the pixels 21 shown, preferably, for example, sub-pixel 23a is a sub-pixel R emitting red light, sub-pixel 23b is a sub-pixel G emitting green light, sub-pixel 23c is a sub-pixel B emitting blue light, and sub-pixel 23d is a sub-pixel S including a light-receiving element. When the above structure is adopted, in Figure 84G and Figure 84H In pixel 21 shown, the R, G, and B pixels are arranged in a stripe pattern, which improves display quality. Additionally, in Figure 84I In the pixel 21 shown, the layout of R, G, and B is a so-called S-striped arrangement, which can improve the display quality.

[0538] There are no particular limitations on the wavelength of light detected by the sub-pixel S, which includes the light-receiving element. The sub-pixel S can detect one or both of the visible light and infrared light.

[0539] like Figure 84J and Figure 84K As shown, a pixel can include five sub-pixels.

[0540] Figure 84J This shows an example of a pixel 21 arranged in two rows and three columns.

[0541] Figure 84J The pixel 21 shown includes three sub-pixels (sub-pixels 23a, 23b, and 23c) in the top row (first row) and two sub-pixels (sub-pixels 23d and 23e) in the bottom row (second row). In other words, pixel 21 includes sub-pixels 23a and 23d in the left column (first column), sub-pixel 23b in the middle column (second column), sub-pixel 23c in the right column (third column), and sub-pixel 23e spanning from the second to the third column.

[0542] Figure 84K This shows an example of a pixel 21 arranged in three rows and two columns.

[0543] Figure 84K The pixel 21 shown includes sub-pixel 23a in the top row (first row), sub-pixel 23b in the middle row (second row), sub-pixel 23c spanning from the first row to the second row, and two sub-pixels (sub-pixel 23d and sub-pixel 23e) in the bottom row (third row). In other words, pixel 21 includes sub-pixels 23a, 23b, and 23d in the left column (first column) and sub-pixels 23c and 23e in the right column (second column).

[0544] exist Figure 84J and Figure 84KIn each of the pixels 21 shown, preferably, for example, sub-pixel 23a is sub-pixel R emitting red light, sub-pixel 23b is sub-pixel G emitting green light, and sub-pixel 23c is sub-pixel B emitting blue light. When the above structure is adopted, in Figure 84J In pixel 21 shown, the R, G, and B pixels are arranged in a stripe pattern, which improves display quality. Additionally, in Figure 84K In the pixel 21 shown, the layout of R, G, and B is a so-called S-striped arrangement, which can improve the display quality.

[0545] exist Figure 84J and Figure 84K Of the pixels 21 shown, it is preferable, for example, that at least one of sub-pixels 23d and 23e uses a sub-pixel S including a light-receiving element. When both sub-pixels 23d and 23e use light-receiving elements, the structures of the light-receiving elements can also be different. For example, at least a portion of the wavelength region of the detected light can also be different from each other. Specifically, one of sub-pixels 23d and 23e may include a light-receiving element that primarily detects visible light, and the other may include a light-receiving element that primarily detects infrared light.

[0546] exist Figure 84J and Figure 84K In each of the pixels 21 shown, for example, one of sub-pixels 23d and 23e uses a sub-pixel S that includes a light-receiving element, and the other uses a sub-pixel that includes a light-emitting element that can be used as a light source. For example, it is preferable that one of sub-pixels 23d and 23e uses a sub-pixel IR that emits infrared light, and the other uses a sub-pixel S that includes a light-receiving element that detects infrared light.

[0547] Among the pixels including sub-pixels R, G, B, IR, and S, sub-pixels R, G, and B can be used to display images, and sub-pixel IR can be used as a light source while sub-pixel S detects the reflected infrared light emitted by sub-pixel IR.

[0548] As described above, in one aspect of the display device of the present invention, various layouts can be adopted for pixels composed of sub-pixels including light-emitting elements. Furthermore, one aspect of the display device of the present invention can employ a structure in which both light-emitting elements and light-receiving elements are included in the pixel. In this case, various layouts can also be adopted.

[0549] The various structural examples shown in this embodiment can be appropriately combined. Furthermore, this embodiment can be appropriately combined with other embodiments.

[0550] (Implementation Method 3) In this embodiment, a display device according to one aspect of the present invention will be described.

[0551] The display device in this embodiment can be a high-definition display device. Therefore, for example, the display device in this embodiment can be used as the display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, as well as the display unit of wearable devices that can be worn on the head, such as head-mounted displays (HMDs) for VR devices and glasses-type AR devices.

[0552] [Display device 10A] Figure 85 This is a perspective view showing an example of the structure of the display device 10A. Figure 86 This is a cross-sectional view showing an example of the structure of the display device 10A. The display device 10A can utilize the structure of the display device 10 shown in Embodiment 1 above.

[0553] The display device 10A has a structure that bonds substrate 152 and substrate 101. Figure 85 In the image, substrate 152 is represented by a dashed line.

[0554] The display device 10A includes a display unit 20, a connection unit 140, a circuit 164, and wiring 165, etc. Figure 85 An example is shown where display device 10A is equipped with IC173 and FPC172. Therefore, it is also possible to... Figure 85 The structure shown is called a display module including display device 10A, IC (integrated circuit) and FPC.

[0555] In this specification and the like, the substrate of a display device on which a connector such as an FPC is mounted, or the substrate on which an IC is mounted, is referred to as a display module.

[0556] The connecting portion 140 is disposed on the outer side of the display portion 20. The connecting portion 140 may be disposed along one or more edges of the display portion 20. There may also be one or more connecting portions 140. Figure 85 An example is shown where the connecting portions 140 are arranged around the four sides of the display section. In the connecting portions 140, the common electrode of the light-emitting element is electrically connected to the conductive layer, through which a potential can be supplied to the common electrode.

[0557] Circuit 164 may include the implementation method 1 Figure 1A and Figure 2A The scan line drive circuit 11, signal line drive circuit 13, power supply circuit 15, and shown are... Figure 2A At least one of the reference potential generation circuits 17 shown.

[0558] Wiring 165 has the function of supplying signals and power to display unit 20 and circuit 164. The signals and power are input to wiring 165 from the outside via FPC 172 or from IC 173.

[0559] Figure 85An example is shown where IC173 is disposed on substrate 101 using methods such as COG (Chip On Glass) or COF (Chip On Film). IC173 may include the IC173 described in Embodiment 1. Figure 1A and Figure 2A The scan line drive circuit 11, signal line drive circuit 13, power supply circuit 15, and shown are... Figure 2A At least one of the reference potential generation circuits 17 shown. Note that the display device 10A and the display module may also omit the IC. Alternatively, the IC may be mounted on the FPC using a COF method, for example.

[0560] Figure 86 An example of a cross-section is shown when a portion of the display device 10A including the FPC 172, a portion of the circuit 164, a portion of the display section 20, a portion of the connection section 140, and a portion of the region including the end are cut off.

[0561] Figure 86 The display device 10A shown includes transistors 201, 205R, 205G, and 205B, as well as light-emitting elements 60R, 60G, and 60B, between substrates 101 and 152. Light-emitting elements 60R, 60G, and 60B may, for example, have the same characteristics as in Embodiment 1. Figure 8B The light-emitting element 60 shown has the same structure. Here, the pixel electrode 311 and layer 313 included in the light-emitting element 60R are pixel electrode 311R and layer 313R, respectively. Similarly, the pixel electrode 311 and layer 313 included in the light-emitting element 60G are pixel electrode 311G and layer 313G, respectively. Furthermore, the pixel electrode 311 and layer 313 included in the light-emitting element 60B are pixel electrode 311B and layer 313B, respectively. A common electrode 315 is provided on layers 313R, 313G, and 313B. The common electrode 315 is shared by the light-emitting elements 60R, 60G, and 60B. Figure 86 In the example shown, the conductive layer 112 of transistor 205R is electrically connected to pixel electrode 311R, the conductive layer 112 of transistor 205G is electrically connected to pixel electrode 311G, and the conductive layer 112 of transistor 205B is electrically connected to pixel electrode 311B.

[0562] An ins...

Claims

1. A display device, comprising: Pixels; Power supply circuit; as well as Scan line driver circuit, The pixel includes a first transistor, a second transistor and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer and a second insulating layer. The first insulating layer is disposed on the first conductive layer, The first insulating layer comprises a first opening reaching the first conductive layer, The first conductive layer is electrically connected to the power circuit, The second conductive layer is disposed on the first insulating layer, the second conductive layer includes a second opening having an area overlapping the first opening, The first semiconductor layer is provided so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer and a region located inside the first opening and a region located inside the second opening. The second insulating layer is provided on the first semiconductor layer in a manner of having a region located inside the first opening and a region located inside the second opening, The third conductive layer is provided so as to have a region located inside the first opening and a region located inside the second opening and to have a region facing the first semiconductor layer with the second insulating layer interposed therebetween. The second transistor includes the second insulating layer, a second semiconductor layer under the second insulating layer, and a fourth conductive layer on the second insulating layer. The fourth conductive layer has a region overlapping with the second semiconductor layer, The fourth conductive layer is electrically connected to the scan line driving circuit. Furthermore, the fourth conductive layer has a region overlapping the first conductive layer via the first insulating layer and the second insulating layer.

2. The display device according to claim 1, wherein the second transistor comprises a fifth conductive layer in contact with the second semiconductor layer, And the fifth conductive layer is electrically connected to the third conductive layer.

3. The display device according to claim 2, The display device comprises a signal line driving circuit. The second transistor includes a sixth conductive layer in contact with the second semiconductor layer, And the sixth conductive layer is electrically connected to the signal line driving circuit.

4. The display device according to any one of claims 1 to 3, The first semiconductor layer and the second semiconductor layer include metal oxide.

5. The display device according to claim 4, The metal oxide comprises indium, zinc and M (M is one or more selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium and hafnium).

6. The display device according to any one of claims 1 to 3, wherein the pixel comprises a display element, And the pixel electrode of the display element is electrically connected to the second conductive layer.

7. The display device according to claim 6, The display device includes a reference potential generating circuit. The pixel comprises a third transistor, The third transistor includes a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a third semiconductor layer and the second insulating layer, The first insulating layer is disposed on the seventh conductive layer, The first insulating layer comprises a third opening reaching the seventh conductive layer, The seventh conductive layer is electrically connected to the pixel electrode, The eighth conductive layer is disposed on the first insulating layer, The eighth conductive layer includes a fourth opening having an area overlapping the third opening, The eighth conductive layer is electrically connected to the reference potential generating circuit. The third semiconductor layer is provided so as to have a region in contact with the seventh conductive layer and a region in contact with the eighth conductive layer and a region located inside the third opening and a region located inside the fourth opening, The second insulating layer is provided on the third semiconductor layer in a manner of having a region located inside the third opening and a region located inside the fourth opening, The ninth conductive layer is provided so as to have a region located inside the third opening and a region located inside the fourth opening and to have a region facing the third semiconductor layer with the second insulating layer interposed therebetween. The ninth conductive layer is electrically connected to the scan line driving circuit. And the eighth conductive layer has a region overlapping with the fourth conductive layer and a region overlapping with the ninth conductive layer.

8. The display device according to claim 7, The third semiconductor layer comprises a metal oxide.

9. The display device according to claim 8, The metal oxide comprises indium, zinc and M (M is one or more selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium and hafnium).

10. A display device, comprising: Pixels; Scan line driving circuit; as well as Power supply circuit, The pixel includes a first transistor, a second transistor and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer and a second insulating layer. The first insulating layer is disposed on the first conductive layer, The first insulating layer comprises a first opening reaching the first conductive layer, The second conductive layer is disposed on the first insulating layer, the second conductive layer includes a second opening having an area overlapping the first opening, The first semiconductor layer is provided so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer and a region located inside the first opening and a region located inside the second opening. The second insulating layer is provided on the first semiconductor layer in a manner of having a region located inside the first opening and a region located inside the second opening, The third conductive layer is provided so as to have a region located inside the first opening and a region located inside the second opening and to have a region facing the first semiconductor layer with the second insulating layer interposed therebetween. The third conductive layer is electrically connected to the scan line driving circuit. The second transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a second semiconductor layer and the second insulating layer, The first insulating layer is disposed on the fourth conductive layer, The first insulating layer comprises a third opening reaching the fourth conductive layer, The fourth conductive layer is electrically connected to the power circuit, The fifth conductive layer is disposed on the first insulating layer, the fifth conductive layer includes a fourth opening having an area overlapping the third opening, The second semiconductor layer is provided so as to have a region in contact with the fourth conductive layer and a region in contact with the fifth conductive layer and a region located inside the third opening and a region located inside the fourth opening, The second insulating layer is provided on the second semiconductor layer in a manner of having a region located inside the third opening and a region located inside the fourth opening, The sixth conductive layer is provided so as to have a region located inside the third opening and a region located inside the fourth opening and to have a region facing the second semiconductor layer with the second insulating layer interposed therebetween. Furthermore, the third conductive layer includes a region overlapping the fourth conductive layer via the first insulating layer and the second insulating layer.

11. The display device according to claim 10, The display device comprises a signal line driving circuit. The first conductive layer is electrically connected to the signal line driving circuit. And the first conductive layer has a region overlapping with the third conductive layer.

12. The display device according to claim 10 or 11, The second conductive layer is electrically connected to the sixth conductive layer.

13. The display device according to claim 10 or 11, The first semiconductor layer and the second semiconductor layer include metal oxide.

14. The display device according to claim 13, The metal oxide comprises indium, zinc and M (M is one or more selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium and hafnium).

15. The display device according to claim 10 or 11, wherein the pixel comprises a display element, And the pixel electrode of the display element is electrically connected to the fifth conductive layer.

16. The display device according to claim 15, The display device includes a reference potential generating circuit. The pixel comprises a third transistor, The third transistor includes a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a third semiconductor layer and the second insulating layer, The first insulating layer is disposed on the seventh conductive layer, The first insulating layer comprises a fifth opening reaching the seventh conductive layer, The seventh conductive layer is electrically connected to the pixel electrode, The eighth conductive layer is disposed on the first insulating layer, The eighth conductive layer includes a sixth opening having an area overlapping the fifth opening, The eighth conductive layer is electrically connected to the reference potential generating circuit. The third semiconductor layer is provided so as to have a region in contact with the seventh conductive layer and a region in contact with the eighth conductive layer and a region located inside the fifth opening and a region located inside the sixth opening, The second insulating layer is provided on the third semiconductor layer in a manner of having a region located inside the fifth opening and a region located inside the sixth opening, The ninth conductive layer is provided so as to have a region located inside the fifth opening and a region located inside the sixth opening and to have a region facing the third semiconductor layer with the second insulating layer interposed therebetween. The ninth conductive layer is electrically connected to the scan line driving circuit. And the eighth conductive layer has a region overlapping with the third conductive layer and a region overlapping with the ninth conductive layer.

17. The display device according to claim 16, The third semiconductor layer comprises a metal oxide.

18. The display device according to claim 17, The metal oxide comprises indium, zinc and M (M is one or more selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium and hafnium).

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