Quick starting circuit suitable for band-gap reference circuit

Abstract

The invention discloses a quick starting circuit suitable for a band-gap reference circuit. A source electrode of a first PMOS switch tube, one end of a first control switch, one end of a capacitor and a source electrode of a second PMOS switch tube are all connected with power supply voltage; the grid electrode of the first PMOS switch tube is respectively connected with the other end of the first control switch, one end of the second control switch and the drain electrode of the second PMOS switch tube, the other end of the second control switch is grounded, the drain electrode of the first PMOS switch tube is connected to the NMOS current mirror, and the drain electrode of the second PMOS switch tube is connected to the NMOS current mirror. The output end of the NMOS current mirror and the grid electrode of the second PMOS switch tube are jointly used as the output end of the quick start circuit and are connected to a current copy node of the band-gap reference circuit; the other end of the capacitor is respectively connected with one end of a third control switch, the control end of the first control switch and the control end of the second control switch, the other end of the third control switch is grounded, and the control end of the third control switch is connected with one end of a first single-pole single-throw switch; and the other end of the first single-pole single-throw switch is connected with the output end of the band-gap reference circuit.

Description

Technical Field

[0001] The invention relates to the fields of analog circuit technology and semiconductor integration technology, and in particular to a fast start-up circuit suitable for a bandgap reference circuit. Background Art

[0002] The bandgap reference circuit provides stable reference current and voltage for each module of the chip. When the chip is powered on or off, the bandgap reference circuit needs to respond in time and quickly and reliably turn on or off the reference current and voltage. As an important part of the bandgap reference circuit, the startup circuit needs to allow the bandgap reference to quickly leave the degeneracy point when the chip is powered on to avoid circuit lock. After power-on is completed, the startup circuit needs to shut down automatically to avoid affecting the normal operation of the bandgap reference circuit.

[0003] In the prior art, a part of the startup circuit uses the threshold voltages of two groups of MOS tubes as the thresholds of the startup circuit. When the chip power-on voltage exceeds the threshold voltage of the first group of MOS tubes, the MOS tubes are turned on, and the bias node of the bandgap reference is pulled down to leave the degenerate point. When the bandgap reference circuit is started up, the output voltage exceeds the threshold voltage of the second group of MOS tubes, and the startup circuit is turned off. The advantage of this technology is that the startup circuit only works during the startup of the bandgap reference circuit, and there is no static power consumption after the startup is completed. However, the disadvantage is that the threshold voltage of the MOS tube varies greatly with the process and temperature. The startup speed is significantly reduced in slow processes or low temperatures. If there is residual voltage when the chip is powered off, the startup speed will also be slowed down due to the residual charge inside the startup circuit when it is powered on again. Another part of the startup circuit uses the voltage drop of the large resistor as the control voltage of the startup circuit. When the chip starts to power on, there is no current in the large resistor, so its voltage drop is approximately 0. The P-type current source controlled by the voltage drop is turned on, and the bias node of the bandgap reference is pulled down to leave the degenerate point. When the bandgap reference circuit is started, the voltage drop on the large resistor is close to the power supply voltage, and the current source is turned off to complete the startup. The advantage of this technology is that the startup threshold is not affected by the MOS tube, so the startup speed will not be significantly reduced in slow processes or low temperatures. However, the disadvantage is that after the startup is completed, the large resistor needs to have a static current in order to maintain the voltage drop, and reducing the static current requires increasing the resistance of the resistor, resulting in an increase in the area of ​​the resistor, which is not conducive to low power consumption and low-cost design. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a fast startup circuit suitable for a bandgap reference circuit, which can realize fast startup of the bandgap reference circuit under various voltages, processes and temperatures, has basically no static current, and occupies a small chip area.

[0005] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme: a fast start-up circuit suitable for a bandgap reference circuit, comprising: a first PMOS switch tube, an NMOS current mirror, a second PMOS switch tube, a capacitor, a first control switch, a second control switch, a third control switch and a first single-pole single-throw switch, wherein the source of the first PMOS switch tube, one end of the first control switch, one end of the capacitor, and the source of the second PMOS switch tube are all connected to a power supply voltage VDD, and the gate of the first PMOS switch tube is respectively connected to the other end of the first control switch, one end of the second control switch, and the drain of the second PMOS switch tube. , the other end of the second control switch is grounded, the drain of the first PMOS switch tube is connected to the NMOS current mirror, the output end of the NMOS current mirror and the gate of the second PMOS switch tube are connected to the current replication node A of the bandgap reference circuit as the output end of the fast start circuit; the other end of the capacitor is respectively connected to one end of the third control switch, the control end of the first control switch, and the control end of the second control switch, the other end of the third control switch is grounded, the control end of the third control switch is connected to one end of the first single-pole single-throw switch, and the other end of the first single-pole single-throw switch is connected to the output end BG of the bandgap reference circuit OUT connect.

[0006] Furthermore, the NMOS current mirror includes: a first NMOS switch tube and a second NMOS switch tube, the drain and the gate of the first NMOS switch tube are respectively connected to the drain of the first PMOS switch tube and the gate of the second NMOS switch tube, the source of the first NMOS switch tube and the source of the second NMOS switch tube are both grounded, and the drain of the second NMOS switch tube and the gate of the second PMOS switch tube are jointly connected to the current replication node A of the bandgap reference circuit as the output end of the fast start-up circuit.

[0007] Furthermore, an inverter is included, wherein the input end of the inverter is connected to the other end of the capacitor and is used to control the control end of the second control switch, and the output end of the inverter is used to control the control end of the first control switch.

[0008] Furthermore, the first control switch is a third PMOS switch tube, the source of the third PMOS switch tube is connected to the power supply voltage VDD, the gate of the third PMOS switch tube is connected to the other end of the capacitor, and the drain of the third PMOS switch tube is respectively connected to one end of the second control switch, the gate of the first PMOS switch tube, and the drain of the second PMOS switch tube.

[0009] Furthermore, the second control switch is a third NMOS switch tube, the gate of the third NMOS switch tube is connected to the other end of the capacitor, the source of the third NMOS switch tube is grounded, and the drain of the third NMOS switch tube is respectively connected to the drain of the second PMOS switch tube, the drain of the third PMOS switch tube, and the gate of the first PMOS switch tube.

[0010] Furthermore, the third control switch is a fourth NMOS switch tube, a gate of the fourth NMOS switch tube is connected to one end of the first single-pole single-throw switch, a source of the fourth NMOS switch tube is grounded, and a drain of the fourth NMOS switch tube is connected to the other end of the capacitor.

[0011] Furthermore, it also includes: a fourth control switch and a quantization inverter, one end of the fourth control switch and the input end of the quantization inverter are both connected to the power supply voltage VDD, the output end of the quantization inverter is used to control the control end of the fourth control switch, and the other end of the fourth control switch is connected to the other end of the capacitor.

[0012] Further, the fourth control switch is a fifth NMOS switch tube, and the quantized inverter includes: a fourth PMOS switch tube, a sixth NMOS switch tube, a second single-pole single-throw switch and a third single-pole single-throw switch, one end of the third single-pole single-throw switch, the gate of the sixth NMOS switch tube, the source of the fourth PMOS switch tube, and the drain of the fifth NMOS switch tube are all connected to the power supply voltage VDD, the other end of the third single-pole single-throw switch and one end of the second single-pole single-throw switch are all connected to the gate of the fourth PMOS switch tube, the drain of the fourth PMOS switch tube is respectively connected to the drain of the sixth NMOS switch tube and the gate of the fifth NMOS switch tube, the source of the sixth NMOS switch tube is grounded, the other end of the second single-pole single-throw switch is connected to the current replication node A of the bandgap reference circuit, and the substrate and source of the fifth NMOS switch tube are both connected to the other end of the capacitor.

[0013] Furthermore, it also includes a level shifter, the level shifter is connected in parallel with the first single-pole single-throw switch, and the input end of the level shifter is connected to the output end BG of the bandgap reference circuit. OUT The output end of the level shifter is used to control the gate voltage of the fourth NMOS switch tube.

[0014] Further, the level shifter includes: a seventh NMOS switch tube and a fifth PMOS switch tube, the drain of the seventh NMOS switch tube is connected to the power supply voltage VDD, the source of the seventh NMOS switch tube and the source of the fifth PMOS switch tube are both connected to the gate of the fourth NMOS switch tube and one end of the first single-pole single-throw switch, the gate of the seventh NMOS switch tube, the other end of the first single-pole single-throw switch, and the gate of the fifth PMOS switch tube are all connected to the output end BG of the bandgap reference circuit. OUT Connection; the drain of the fifth PMOS switch tube is grounded.

[0015] Compared with the prior art, the present invention has the following beneficial effects: the fast startup circuit of the bandgap reference circuit of the present invention has basically no static current and no resistors occupying a large area after the startup is completed, and has the characteristics of low power consumption and low cost; in addition, the present invention introduces a fourth control switch and a quantized inverter to discharge the charge of the residual voltage in the capacitor in view of the situation that there is a residual voltage when the chip is powered off, which can improve the next startup speed and make the applicable scenarios more extensive; in addition, the present invention introduces a level shifter to improve the shutdown threshold of the startup circuit in view of the situation that the start-up circuit is closed prematurely due to the low turn-on threshold of the third control switch under fast process or high temperature conditions, thereby improving the startup speed of the bandgap reference circuit. In summary, the fast startup circuit of the bandgap reference circuit of the present invention can enable the bandgap reference circuit to start quickly under various voltages, processes and temperatures, and the circuit is also applicable to other situations where a startup circuit is required. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the realization principle of the bandgap reference circuit;

[0017] Figure 2 The schematic diagram of the principle of the fast start-up circuit applicable to the bandgap reference circuit of the present invention;

[0018] Figure 3 The figure is a schematic diagram of a specific circuit structure of a quick start circuit applicable to a bandgap reference circuit of the present invention. DETAILED DESCRIPTION

[0019] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0020] like Figure 11 is a schematic diagram of the implementation principle of a bandgap reference circuit, which includes: a first PMOS current mirror tube 101, a second PMOS current mirror tube 102, a first NPN bipolar transistor 103, a second NPN bipolar transistor 104, a first resistor 105, a second resistor 106 and a start-up circuit 107, the source of the first PMOS current mirror tube 101 and the source of the second PMOS current mirror tube 102 are both connected to a power supply voltage VDD, the gate of the first PMOS current mirror tube 101, the drain of the first PMOS current mirror tube 101, the gate of the second PMOS current mirror tube 102, the first NPN bipolar transistor 105, the second resistor 106 and the start-up circuit 107. The collector of the first NPN bipolar transistor 103 is connected to the output end of the start-up circuit as the current replica node A of the bandgap reference circuit, the emitter of the first NPN bipolar transistor 103 is connected to one end of the first resistor 105, the other end of the first resistor 105 is respectively connected to one end of the second resistor 106 and the emitter of the second NPN bipolar transistor 104, the other end of the second resistor 106 is grounded, the base of the first NPN bipolar transistor 103, the base of the second NPN bipolar transistor 104, the collector of the second NPN bipolar transistor 104 and the drain of the second PMOS current mirror tube 102 are connected to the output end BG of the bandgap reference circuit. OUT Connect to the starter circuit.

[0021] When the chip is powered on, there are two solutions to the state of the bandgap reference circuit. The first solution is the correct solution, that is, the voltage of the current replication node A is lower than the power supply voltage VDD, and each branch of the bandgap reference circuit has current, then the output voltage BG of the output terminal of the bandgap reference circuit is OUT The expression is as follows:

[0022]

[0023] Wherein, R1 is the resistance value of the first resistor 105, R2 is the resistance value of the second resistor 106, ΔV BE is the difference between the base-emitter voltage of the first NPN bipolar transistor 103 and the base-emitter voltage of the second NPN bipolar transistor 104, V BE2 is the base-emitter voltage of the second NPN bipolar transistor 104 .

[0024] The second solution is a degenerate solution, that is, the voltage of the current replica node A is equal to the power supply voltage VDD, and the output voltage BG of the output terminal of the bandgap reference circuit is OUT=0, each branch of the bandgap reference circuit is turned off, and there is no current. Therefore, in order to prevent the bandgap reference circuit from entering the second solution state during power-on, the startup circuit needs to quickly pull down the voltage of the current copy node A to leave the power supply voltage VDD during power-on. At this time, the first PMOS current mirror tube 101 and the second PMOS current mirror tube 102 are turned on, and each branch in the bandgap reference circuit will generate current, and the circuit will leave the degenerate state. Then, the connection between the startup circuit and the current copy node A is disconnected, and the bandgap reference circuit will stabilize to the correct solution state.

[0025] From the working principle of the above-mentioned bandgap reference circuit, it can be seen that the startup circuit needs to pull down the voltage of the current replication node A until the first PMOS current mirror tube 101 is turned on, and the faster the voltage of the current replication node A is pulled down and the lower the voltage value, the faster the startup speed of the bandgap reference circuit. After the startup is completed, the startup circuit needs to be disconnected from the current replication node A, otherwise there will not only be static power consumption, but also the voltage of the current replication node A will be too low and the circuit state will be abnormal. In addition, in actual applications, there may be residual voltage when the chip is powered off, that is, the power supply voltage VDD is greater than 0, and the residual voltage cannot affect the startup of the bandgap reference circuit when it is powered on next time.

[0026] In order to meet the design requirements of the above-mentioned startup circuit, the present invention provides a fast startup circuit suitable for a bandgap reference circuit, the principle of which is as follows: Figure 2As shown, the fast start-up circuit includes: a first PMOS switch tube 201, an NMOS current mirror, a second PMOS switch tube 204, a capacitor 205, a first control switch 207, a second control switch 208, a third control switch 211 and a first single-pole single-throw switch 213, the source of the first PMOS switch tube 201, one end of the first control switch 207, one end of the capacitor 205, and the source of the second PMOS switch tube 204 are all connected to the power supply voltage VDD, the gate of the first PMOS switch tube 201 is respectively connected to the other end of the first control switch 207, one end of the second control switch 208, and the drain of the second PMOS switch tube 204, and the second control The other end of the switch 208 is grounded, the drain of the first PMOS switch tube 201 is connected to the NMOS current mirror, and the output end of the NMOS current mirror and the gate of the second PMOS switch tube 204 are connected to the current replication node A of the bandgap reference circuit as the output end of the fast start-up circuit; the other end B of the capacitor 205 is respectively connected to one end of the third control switch 211, the control end of the first control switch 207, and the control end of the second control switch 208, the other end of the third control switch 211 is grounded, the control end of the third control switch 211 is connected to one end of the first single-pole single-throw switch 213, and the other end of the first single-pole single-throw switch 213 is connected to the output end of the bandgap reference circuit. In order to ensure that the second control switch 208 is disconnected when the first control switch 207 is turned on or the second control switch 208 is turned on when the first control switch 207 is turned off, an inverter 206 is provided, the input end of the inverter 206 is connected to the other end of the capacitor 205 for controlling the control end of the second control switch 208, and the output end of the inverter 206 is used to control the control end of the first control switch 207; and in the quick start circuit, the first single-pole single-throw switch 213 is closed by default.

[0027] When the chip is powered on, due to the conservation of charge across the capacitor 205, the other end B of the capacitor 205 rises along with the power supply voltage VDD. When the voltage at the other end B of the capacitor 205 rises to the turn-on threshold of the second control switch 208, the second control switch 208 is closed, and at the same time the output of the inverter 206 is low, and the first control switch 207 is turned off, so the gate of the first PMOS switch tube 201 is grounded and turned on, and the generated current passes through the NMOS current mirror to provide a current path to the current replication node A, so that the voltage of the current replication node A is pulled down, and the bandgap reference circuit leaves the degenerate point and enters the normal establishment process. At the same time, in the default state, the first single-pole single-throw switch 213 is closed, and when the bandgap reference circuit is established, its output voltage BG OUTThe turn-on threshold of the third control switch 211 is exceeded, so the third control switch 211 is controlled to be closed, so that the other end B of the capacitor 205 is pulled down to 0, the second control switch 208 is turned off, and the first control switch 207 is closed. At this time, the first PMOS switch tube 201 is turned off, there is no current on the NMOS current mirror, the entire startup circuit is turned off, and no static power consumption is generated.

[0028] The NMOS current mirror in the present invention includes: a first NMOS switch tube 202 and a second NMOS switch tube 203, wherein the drain and the gate of the first NMOS switch tube 202 are respectively connected to the drain of the first PMOS switch tube 201 and the gate of the second NMOS switch tube 203, the source of the first NMOS switch tube 202 and the source of the second NMOS switch tube 203 are both grounded, and the drain of the second NMOS switch tube 203 and the gate of the second PMOS switch tube 204 are connected to the current replication node A of the bandgap reference circuit as the output end of the fast start-up circuit.

[0029] like Figure 3 In the present invention, the first control switch 207 is a third PMOS switch tube 301, the source of the third PMOS switch tube 301 is connected to the power supply voltage VDD, the gate of the third PMOS switch tube 301 is connected to the other end of the capacitor 205, and the drain of the third PMOS switch tube 301 is respectively connected to one end of the second control switch 208, the gate of the first PMOS switch tube 201, and the drain of the second PMOS switch tube 204.

[0030] In the present invention, the second control switch 208 is a third NMOS switch tube 302, the gate of the third NMOS switch tube 302 is connected to the other end of the capacitor 205, the source of the third NMOS switch tube 302 is grounded, and the drain of the third NMOS switch tube 302 is respectively connected to the drain of the second PMOS switch tube 204, the drain of the third PMOS switch tube 301, and the gate of the first PMOS switch tube 201.

[0031] In the present invention, the third control switch 211 is a fourth NMOS switch tube 308 , the gate of the fourth NMOS switch tube 308 is connected to one end of the first single-pole single-throw switch 213 , the source of the fourth NMOS switch tube 308 is grounded, and the drain of the fourth NMOS switch tube 308 is connected to the other end of the capacitor 205 .

[0032] In actual applications, there may be a residual voltage V on the power supply voltage VDD after the chip is powered off. RES , while the voltage at the other end B of capacitor 205 is still 0, so the capacitor 205 stores a voltage equal to the residual voltage V RES When the power is turned on again, the voltage at the other end B of the capacitor 205 increases by the voltage of the power supply voltage VDD and the residual voltage V RESIn a slow process or at a low temperature, the turn-on threshold of the second control switch 208 is high. If the power supply voltage VDD is low, the voltage at the other end B of the capacitor 205 may not be enough to turn on the second control switch 208 or delay the turn-on of the second control switch 208, resulting in failure to start or slow start-up when powered on again. To solve this problem, the fourth control switch 209 and the quantized inverter 210 are introduced, such as Figure 2 , one end of the fourth control switch 209 and the input end of the quantization inverter 210 are connected to the power supply voltage VDD, the output end of the quantization inverter 210 is used to control the control end of the fourth control switch 209, and the other end of the fourth control switch 209 is connected to the other end of the capacitor 205. The judgment threshold of the quantization inverter 210 is half of the normal power supply voltage VDD. When the chip is powered on normally, the power supply voltage VDD is high and higher than the judgment threshold, then the quantization inverter outputs 0, so the fourth control switch 209 is turned off, and the other end B of the capacitor 205 remains in a low state; when the chip is powered off, the power supply voltage VDD is reduced to the residual voltage V RES , is lower than the judgment threshold, the quantized inverter output V RES , so the fourth control switch 209 is turned on, raising the voltage at the other end B of the capacitor 205 to V RES , thereby discharging the charge stored in the capacitor 205, and the voltage increase at the other end B of the capacitor 205 can be restored to the power supply voltage VDD when the power is turned on next time, thereby improving the power-on startup speed.

[0033] Specifically, Figure 3 , the fourth control switch 209 is a fifth NMOS switch tube 303, the quantized inverter 210 includes: a fourth PMOS switch tube 304, a sixth NMOS switch tube 305, a second single-pole single-throw switch 306 and a third single-pole single-throw switch 307, one end of the third single-pole single-throw switch 307, the gate of the sixth NMOS switch tube 305, the source of the fourth PMOS switch tube 304, and the drain of the fifth NMOS switch tube 303 are all connected to the power supply voltage VDD, and the other end of the third single-pole single-throw switch 307 and one end of the second single-pole single-throw switch 306 are all connected to The gate of the fourth PMOS switch tube 304 is connected, the drain of the fourth PMOS switch tube 304 is respectively connected to the drain of the sixth NMOS switch tube 305 and the gate of the fifth NMOS switch tube 303, the source of the sixth NMOS switch tube 305 is grounded, the other end of the second single-pole single-throw switch 306 is connected to the current replication node A of the bandgap reference circuit, the substrate and the source of the fifth NMOS switch tube 303 are connected to the other end of the capacitor 205, the second single-pole single-throw switch 306 is closed, and the second single-pole single-throw switch 307 is opened. When the chip is powered off, there is a residual voltage V RES When the output voltage BG of the bandgap reference circuit OUTIt is often connected to a large filter capacitor, so the output voltage BG of the bandgap reference circuit OUT Close to the residual voltage V RES , so that there is still a little current in the first NPN bipolar transistor 103 and the second NPN bipolar transistor 104 of the bandgap reference circuit. In order to maintain this current, the first PMOS current mirror tube 101 and the second PMOS current mirror tube 102 in the bandgap reference circuit are slightly turned on, so the voltage of the current copy node A is close to 0. At this time, the gate-source voltages of the fourth PMOS switch tube 304 and the sixth NMOS switch tube 305 are both approximately the residual voltage V RES By adjusting the relative driving capabilities of the fourth PMOS switch tube 304 and the sixth NMOS switch tube 305, so that the pull-up capability of the fourth PMOS switch tube 304 is stronger, the voltage of the node D will be close to the residual voltage V RES ; and the source and substrate of the fifth NMOS switch tube 303 are short-circuited, the threshold voltage is reduced, and the pull-down capability is improved, so the voltage of the other end B of the capacitor 205 can be pulled up, and the charge stored in the capacitor 205 is discharged. When the power is on next time, the voltage of the other end B of the capacitor 205 can be raised to be closer to the power supply voltage VDD, thereby improving the power-on startup speed. After the normal power-on is completed, the gate-source voltage of the fourth PMOS switch tube 304 is equal to the gate-source voltage of the first PMOS current mirror tube 101 in the bandgap reference main circuit, and the gate-source voltage of the sixth NMOS switch tube 305 is the power supply voltage VDD, so the pull-down capability of the sixth NMOS switch tube 305 is stronger than the pull-up capability of the fourth PMOS switch tube 304, and the voltage of the node D formed by the drain of the fourth PMOS switch tube 304 and the drain of the sixth NMOS switch tube 305 is 0, so that the fifth NMOS switch tube 303 is turned off, which does not affect the normal operation of the bandgap reference circuit. In addition, reducing the width-to-length ratio of the fourth PMOS switch tube 304 and the sixth NMOS switch tube 305 as a whole can reduce the static current of the branch after power-on.

[0034] In a fast process or at a high temperature, the turn-on threshold of the third control switch 211 is reduced. When the chip is powered off, BG OUT With V RES is approximately equal, the third control switch 211 is slightly turned on; when powered on again, BG OUT Only a slight rise will cause the third control switch 211 to be fully turned on, and the other end B of the capacitor 205 will be pulled down to 0 too early, and the startup circuit will be turned off. Therefore, the current replication node A of the bandgap reference circuit cannot be pulled down quickly, resulting in a slow startup speed. In order to solve this problem, it is necessary to increase the turn-on threshold of the third control switch 211, so a level shifter 212 is introduced, such as Figure 2 The level shifter 212 is connected in parallel with the first single-pole single-throw switch 213, and the input end of the level shifter 212 is connected to the output end BG of the bandgap reference circuit.OUT , the output end of the level shifter 212 is used to control the gate voltage of the fourth NMOS switch tube 308. At this time, the first single-pole single-throw switch 213 is disconnected, and the output of the level shifter 212 is lower than the threshold voltage of the input MOS tube by about one MOS tube, that is, the control voltage of the third control switch 211 is BG OUT Subtract the threshold voltage, so the output of the bandgap reference circuit BG OUT When a higher voltage is established, the third control switch 211 is turned on and pulls down the voltage at the other end B of the capacitor 205 .

[0035] Specifically, Figure 3 , the level shifter 212 includes: a seventh NMOS switch tube 309 and a fifth PMOS switch tube 310, the drain of the seventh NMOS switch tube 309 is connected to the power supply voltage VDD, the source of the seventh NMOS switch tube 309 and the source of the fifth PMOS switch tube 310 are connected to the gate of the fourth NMOS switch tube 308 and one end of the first single-pole single-throw switch 213 as a node E, the gate of the seventh NMOS switch tube 309, the other end of the first single-pole single-throw switch 213, and the gate of the fifth PMOS switch tube 310 are connected to the output end of the bandgap reference circuit; the drain of the fifth PMOS switch tube 310 is grounded. When the chip is powered down to the residual voltage V RES When the chip is powered off from the residual voltage V RES When the power is turned on again, the voltage of node E is pushed down to the output terminal BG of the bandgap reference circuit. OUT The difference between the gate-source voltage of the seventh NMOS switch tube 309 and the gate-source voltage of the seventh NMOS switch tube 309, so the turn-on time of the fourth NMOS switch tube 308 is delayed, the voltage at the other end B of the capacitor 205 will not be pulled down prematurely, and the startup circuit will continue to work until the voltage at the node E exceeds the threshold of the fourth NMOS switch tube 308, effectively improving the startup speed.

[0036] When the chip is powered on, due to the charge conservation at both ends of the capacitor 205, the other end B of the capacitor 205 increases along with the power supply voltage VDD. When the voltage at the other end B of the capacitor 205 increases to the turn-on threshold of the third NMOS switch tube 302, the third NMOS switch tube 302 is turned on, and the gate of the first PMOS switch tube 201, the drain of the third PMOS switch tube 301, the drain of the second PMOS switch tube 204 and the drain of the third NMOS switch tube 302 are used as node C, and the voltage of node C is pulled down to 0. The first PMOS switch tube 201 is turned on, and the generated current passes through the NMOS current mirror to provide a current path to the current copy node A of the bandgap reference circuit, so that the voltage of the current copy node A is pulled down, and the bandgap reference circuit leaves the degenerate point and enters the normal establishment process. When the chip is powered off and there is no residual voltage V RES When the third single-pole single-throw switch 307 is closed, the gate of the fourth PMOS switch tube 304 is connected to the power supply voltage VDD, and the gate-source voltage of the sixth NMOS switch tube 305 is also the power supply voltage VDD, so the voltage of the node D is 0, the fifth NMOS switch tube 303 is turned off, the voltage of the other end B of the capacitor 205 is not affected, and the branches of the fifth NMOS switch tube 303, the fourth PMOS switch tube 304 and the sixth NMOS switch tube 305 have no static power consumption. When the bandgap reference is established, because the first single-pole single-throw switch 213 is closed, when the output voltage BG of the bandgap reference circuit is OUT When the turn-on threshold of the fourth NMOS switch tube 308 is exceeded, the fourth NMOS switch tube 308 is turned on, the other end B of the capacitor 205 is pulled down to 0, the third NMOS switch tube 302 is turned off, and the third PMOS switch tube 301 is turned on, pulling the voltage of the node C to the power supply voltage VDD, the first PMOS switch tube 201 is turned off, and the entire startup circuit is closed, and no static power consumption is generated.

[0037] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A fast start-up circuit suitable for a bandgap reference circuit, characterized in that: include: A first PMOS switch tube (201), an NMOS current mirror, a second PMOS switch tube (204), a capacitor (205), a first control switch (207), a second control switch (208), a third control switch (211) and a first single-pole single-throw switch (213); the source of the first PMOS switch tube (201), one end of the first control switch (207), one end of the capacitor (205) and the source of the second PMOS switch tube (204) are all connected to a power supply voltage VDD; the gate of the first PMOS switch tube (201) is respectively connected to the other end of the first control switch (207), one end of the second control switch (208) and the drain of the second PMOS switch tube (204); the second control switch (2 The other end of the capacitor (205) is connected to ground, the drain of the first PMOS switch tube (201) is connected to an NMOS current mirror, and the output end of the NMOS current mirror and the gate of the second PMOS switch tube (204) are connected to the current replication node A of the bandgap reference circuit as the output end of the fast start circuit; the other end of the capacitor (205) is respectively connected to one end of the third control switch (211), the control end of the first control switch (207), and the control end of the second control switch (208), the other end of the third control switch (211) is grounded, the control end of the third control switch (211) is connected to one end of the first single-pole single-throw switch (213), and the other end of the first single-pole single-throw switch (213) is connected to the output end BG of the bandgap reference circuit. OUT connect.

2. A fast start-up circuit suitable for a bandgap reference circuit according to claim 1, characterized in that: The NMOS current mirror comprises: a first NMOS switch tube (202) and a second NMOS switch tube (203); the drain and the gate of the first NMOS switch tube (202) are respectively connected to the drain of the first PMOS switch tube (201) and the gate of the second NMOS switch tube (203); the source of the first NMOS switch tube (202) and the source of the second NMOS switch tube (203) are both grounded; the drain of the second NMOS switch tube (203) and the gate of the second PMOS switch tube (204) are connected to the current replication node A of the bandgap reference circuit as the output end of the fast start-up circuit.

3. A fast start-up circuit suitable for a bandgap reference circuit according to claim 2, characterized in that: It also includes an inverter (206), the input end of the inverter (206) is connected to the other end of the capacitor (205) and is used to control the control end of the second control switch (208), and the output end of the inverter (206) is used to control the control end of the first control switch (207).

4. A fast start-up circuit suitable for a bandgap reference circuit according to claim 2, characterized in that: The first control switch (207) is a third PMOS switch tube (301), the source of the third PMOS switch tube (301) is connected to a power supply voltage VDD, the gate of the third PMOS switch tube (301) is connected to the other end of the capacitor (205), and the drain of the third PMOS switch tube (301) is respectively connected to one end of the second control switch (208), the gate of the first PMOS switch tube (201), and the drain of the second PMOS switch tube (204).

5. A fast start-up circuit suitable for a bandgap reference circuit according to claim 4, characterized in that: The second control switch (208) is a third NMOS switch tube (302), the gate of the third NMOS switch tube (302) is connected to the other end of the capacitor (205), the source of the third NMOS switch tube (302) is grounded, and the drain of the third NMOS switch tube (302) is respectively connected to the drain of the second PMOS switch tube (204), the drain of the third PMOS switch tube (301), and the gate of the first PMOS switch tube (201).

6. A fast start-up circuit suitable for a bandgap reference circuit according to claim 5, characterized in that: The third control switch (211) is a fourth NMOS switch tube (308), the gate of the fourth NMOS switch tube (308) is connected to one end of the first single-pole single-throw switch (213), the source of the fourth NMOS switch tube (308) is grounded, and the drain of the fourth NMOS switch tube (308) is connected to the other end of the capacitor (205).

7. A fast start-up circuit suitable for a bandgap reference circuit according to claim 6, characterized in that: Also includes: A fourth control switch (209) and a quantization inverter (210), one end of the fourth control switch (209) and an input end of the quantization inverter (210) are both connected to a power supply voltage VDD, an output end of the quantization inverter (210) is used to control a control end of the fourth control switch (209), and the other end of the fourth control switch (209) is connected to the other end of the capacitor (205).

8. A fast start-up circuit suitable for a bandgap reference circuit according to claim 7, characterized in that: The fourth control switch (209) is a fifth NMOS switch tube (303), and the quantized inverter (210) comprises: a fourth PMOS switch tube (304), a sixth NMOS switch tube (305), a second single-pole single-throw switch (306), and a third single-pole single-throw switch (307), one end of the third single-pole single-throw switch (307), the gate of the sixth NMOS switch tube (305), the source of the fourth PMOS switch tube (304), and the drain of the fifth NMOS switch tube (303) are all connected to the power supply voltage VDD, and the third single-pole single-throw switch (307) is connected to the power supply voltage VDD. ) and one end of the second single-pole single-throw switch (306) are both connected to the gate of the fourth PMOS switch tube (304); the drain of the fourth PMOS switch tube (304) is respectively connected to the drain of the sixth NMOS switch tube (305) and the gate of the fifth NMOS switch tube (303); the source of the sixth NMOS switch tube (305) is grounded; the other end of the second single-pole single-throw switch (306) is connected to the current replication node A of the bandgap reference circuit; the substrate and source of the fifth NMOS switch tube (303) are both connected to the other end of the capacitor (205).

9. A fast start-up circuit suitable for a bandgap reference circuit according to claim 8, characterized in that: The device also includes a level shifter (212), wherein the level shifter (212) is connected in parallel to the first single-pole single-throw switch (213), and the input end of the level shifter (212) is connected to the output end BG of the bandgap reference circuit. OUT The output end of the level shifter (212) is used to control the gate voltage of the fourth NMOS switch tube (308).

10. A fast start-up circuit suitable for a bandgap reference circuit according to claim 9, characterized in that: The level shifter (212) comprises: a seventh NMOS switch tube (309) and a fifth PMOS switch tube (310), wherein the drain of the seventh NMOS switch tube (309) is connected to a power supply voltage VDD, the source of the seventh NMOS switch tube (309) and the source of the fifth PMOS switch tube (310) are both connected to the gate of the fourth NMOS switch tube (308) and one end of the first single-pole single-throw switch (213), and the gate of the seventh NMOS switch tube (309), the other end of the first single-pole single-throw switch (213), and the gate of the fifth PMOS switch tube (310) are all connected to the output end BG of the bandgap reference circuit. OUT The drain of the fifth PMOS switch tube (310) is connected to the ground.

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