Static memory and read-write method thereof

Abstract

The embodiment of the invention provides a static memory and a read-write method thereof. The static memory includes: a memory cell; a word line; the word selection signal driving circuit comprises a first switch sub-circuit, a gradual change sub-circuit and a second switch sub-circuit, and the first switch sub-circuit is configured to write a first selection signal of an operation signal line into a first node under the control of an effective signal of a first control signal line; the gradual change sub-circuit is configured to enable the first level line and the second level line to be conducted based on the signal of the first node under the condition that the first control signal line provides an invalid signal, and discharge a first selection signal of the first node, so that the first node generates a gradual change second selection signal; and the second switch sub-circuit is configured to provide a slowly changing second selection signal to the word line under the control of an effective signal of a second control signal line. According to the invention, the noise margin of the read operation can be improved, and the read stability is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of static random access memory, and in particular to a static memory and a reading and writing method thereof. Background Art

[0002] With the continuous advancement of SRAM (static random access memory, or SRAM, or static memory) technology, its application in computer systems and related electronic devices has become increasingly widespread, gradually establishing its position as the main storage medium. SRAM plays a key role in the field of microelectronics and has become an indispensable component in integrated circuit design.

[0003] In a storage array based on a traditional 6T SRAM, a storage element in a half-selected state (referred to as a half-selected unit) is always in a read operation state. As the array size increases, the read stability of the half-selected unit needs to be improved.

[0004] To improve the read stability, the read stability can be improved by controlling the word line voltage signal in two steps. However, this method requires providing two different driving voltages, which greatly increases the complexity of the circuit and occupies more area. Summary of the invention

[0005] The embodiments of the present disclosure provide a static memory and a reading and writing method thereof to solve or alleviate one or more technical problems in the prior art.

[0006] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a static memory, including:

[0007] A plurality of storage elements arranged in an array;

[0008] A word line connected to a plurality of memory cells in the same row;

[0009] The word selection signal driving circuit includes a first switch subcircuit, a slow-changing subcircuit, and a second switch subcircuit, wherein:

[0010] A first switch subcircuit is coupled to the first control signal line, the operation signal line and the first node respectively, and is configured to write a first selection signal of the operation signal line to the first node under the control of the valid signal of the first control signal line;

[0011] The slow-changing subcircuit is coupled to the first node, the first level line and the second level line respectively, and is configured to, when the first control signal line provides an invalid signal, make the first level line and the second level line conductive based on the signal of the first node, and discharge the first selection signal of the first node, so that the first node generates a slow-changing second selection signal;

[0012] The second switch sub-circuit is coupled to the second control signal line, the first node and the word line respectively, and is configured to provide a second slowly changing selection signal to the word line under the control of an effective signal of the second control signal line.

[0013] In some embodiments, after the signal provided by the first control signal line changes from a valid signal to an invalid signal, the signal provided by the second control signal line is a valid signal.

[0014] In some embodiments, in a read operation, when the signal provided by the first control signal line is a valid signal, the signal provided by the second control signal line is an invalid signal.

[0015] In some embodiments, in a read operation, the signal provided by the first control signal line changes from a valid signal to an invalid signal while the signal provided by the second control signal line changes from an invalid signal to a valid signal.

[0016] In some embodiments, when the signal provided by the first control signal line is a valid signal and the signal provided by the second control signal line is a valid signal, the first selection signal of the operation signal line is written into the first node through the first switch subcircuit and provided to the word line through the second switch subcircuit.

[0017] In some embodiments, during a write operation, the second control signal line provides a continuous valid signal.

[0018] In some embodiments, the valid signal of the first control signal line is a high level signal, and the valid signal of the second control signal line is a high level signal.

[0019] In some embodiments, one of the first level line and the second level line is connected to a high level signal, and the other is connected to a low level signal.

[0020] In some embodiments, at least one of the following is satisfied:

[0021] The first switch subcircuit includes a seventh transistor, a gate of the seventh transistor is coupled to the first control signal line, and a first electrode and a second electrode of the seventh transistor are respectively coupled to the operation signal line and the first node;

[0022] The slow-changing sub-circuit includes an eighth transistor, a gate of the eighth transistor is coupled to the first node, and a first electrode and a second electrode of the eighth transistor are coupled to the first level line and the second level line respectively;

[0023] The second switch subcircuit includes a ninth transistor, a gate of the ninth transistor is coupled to the second control signal line, and a first electrode and a second electrode of the ninth transistor are coupled to the first node and the word line, respectively.

[0024] In some embodiments,

[0025] The seventh transistor is an oxide transistor;

[0026] The eighth transistor is an oxide transistor;

[0027] The ninth transistor is an oxide transistor.

[0028] In some embodiments, the memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein:

[0029] The gate of the first transistor is coupled to the second node, and the first electrode and the second electrode of the first transistor are coupled to the first power line and the third node respectively;

[0030] The gate of the second transistor is coupled to the third node, and the first electrode and the second electrode of the second transistor are coupled to the first power line and the second node respectively;

[0031] The gate of the third transistor is coupled to the second node, and the first electrode and the second electrode of the third transistor are coupled to the third node and the second power line respectively;

[0032] The gate of the fourth transistor is coupled to the third node, and the first electrode and the second electrode of the fourth transistor are coupled to the second node and the second power line respectively;

[0033] A gate of the fifth transistor is coupled to the word line, and a first electrode and a second electrode of the fifth transistor are coupled to the third node and the first transmission line respectively;

[0034] A gate of the sixth transistor is coupled to the word line, and a first electrode and a second electrode of the sixth transistor are coupled to the second node and the second transmission line respectively;

[0035] The first transistor, the second transistor, the third transistor and the fourth transistor are all surround gate transistors, and the fifth transistor and the sixth transistor are all oxide transistors.

[0036] In some embodiments, including:

[0037] substrate;

[0038] A first structure layer, located on one side of the substrate, the first structure layer comprising a first transistor, a second transistor, a third transistor and a fourth transistor;

[0039] The second structure layer is located on a side of the first structure layer away from the substrate, and the second structure layer includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor.

[0040] In some embodiments, a plurality of word lines and a plurality of word selection signal driving circuits are included, and the plurality of word selection signal driving circuits are coupled to the plurality of word lines in a one-to-one correspondence.

[0041] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for reading and writing a static memory, which is applied to the static memory in any embodiment of the present disclosure, and the method includes:

[0042] In a write operation, a valid signal is provided to the first control signal line and a valid signal is provided to the second control signal line, so that the first selection signal of the operation signal line is written into the first node through the first switch sub-circuit and provided to the word line through the second switch sub-circuit; while the signal provided to the first control signal line is changed from a valid signal to an invalid signal, the valid signal is continuously provided to the second control signal line, the slow-changing sub-circuit discharges the first selection signal of the first node through the first level line and the second level line, so that the first node generates a slow-changing second selection signal, and the slow-changing second selection signal is provided to the word line through the second switch sub-circuit;

[0043] In a read operation, a valid signal is provided to the first control signal line and an invalid signal is provided to the second control signal line, so that the first selection signal of the operation signal line is written into the first node through the first switch sub-circuit; after the signal provided to the first control signal line is changed from a valid signal to an invalid signal, a valid signal is provided to the second control signal line, and the slow-changing sub-circuit discharges the first selection signal of the first node through the first level line and the second level line, so that the first node generates a slow-changing second selection signal, and provides the slow-changing second selection signal to the word line through the second switch sub-circuit.

[0044] In the static memory of the disclosed embodiment, in a read operation, after the first selection signal of the operation signal line is written into the first node, the first control signal line can provide an invalid signal, and the second control signal line can provide a valid signal, so that the first level line and the second level line are turned on, and the first selection signal of the first node is discharged, so that the first node generates a slowly changing second selection signal, and the slowly changing second selection signal is provided to the word line through the second switch sub-circuit, so that the voltage value of the second selection signal is slowly decreasing. When the second selection signal is provided to the word line, the signal on the word line is a slowly changing signal, that is, a slowly decreasing signal, which makes the signal value on the word line lower than the normal signal value in the read operation, which can improve the noise tolerance of the read operation in the SRAM and enhance the read stability.

[0045] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0047] Figure 1 It is a partial circuit diagram of a static memory in one embodiment of the present disclosure;

[0048] Figure 2 is a timing diagram of a write operation of a static memory in an embodiment of the present disclosure;

[0049] Figure 3 is a timing diagram of a read operation of a static memory in an embodiment of the present disclosure;

[0050] Figure 4 It is a partial circuit diagram of a static memory in another embodiment of the present disclosure;

[0051] Figure 5 A schematic diagram of the structure of a static memory in an embodiment of the present disclosure;

[0052] Figure 6 It is a schematic diagram of the structure of a surround gate transistor in one embodiment of the present disclosure;

[0053] Figure 7A-Figure 25A as well as Figure 7B-Figure 25B They are cross-sectional views along the XX axis and YY axis directions of the center of the full-ring gate transistor during the manufacturing process;

[0054] Fig.26 It is a schematic diagram after forming the first connecting part, the second connecting part and the third connecting part;

[0055] Figure 27A-27G It is a cross-sectional schematic diagram of forming the second structural layer.

[0056] Description of reference numerals:

[0057] 401 - semiconductor substrate; 402 - first semiconductor layer; 403 - second semiconductor layer; 404 - first sidewall; 405 - sacrificial layer; 406 - fin; 406 - 1 - lower fin; 406 - 2 - first semiconductor fin; 406 - 3 - second semiconductor fin; 407 - silicon germanium layer;

[0058] 408-nanosheet; 409-shallow trench isolation; 410-dummy gate stack; 411-gate oxide layer; 412-silicon layer; 413-mask layer; 414-gate stack sidewall; 415-embedded cavity structure; 416-inner sidewall insulating dielectric layer; 417-inner sidewall; 420-drain-source layer; 421-1-source region; 421-2-drain region; 422-first interlayer dielectric layer;

[0059] 423 - first opening; 424 - second opening; 425 - diffusion barrier layer; 426 - work function layer; 427 - conductive filling layer; 428 - gate insulating dielectric layer; 429 - metal gate material layer; 430 - second interlayer dielectric layer; 431 - third opening; 432 - fourth opening; 433 - metal gate stack;

[0060] 52 - isolation dielectric layer; 531 - gate electrode; 54 - gate dielectric layer; 551 - oxide semiconductor layer; 561 - source electrode; 562 - drain electrode; 57 - passivation layer. DETAILED DESCRIPTION

[0061] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0062] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source (source electrode) is called the first electrode, the drain (drain electrode) is called the second electrode, or the drain can be called the first electrode and the source is called the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate (also called the gate electrode), the signal input end is the source, and the signal output end is the drain. The switching transistor used in the embodiment of the present invention can be a P-type transistor (PMOS) or an N-type transistor (NMOS). The P-type switching transistor is turned on when the gate is low and turned off when the gate is high; the N-type transistor is turned on when the gate is high and turned off when the gate is low. In addition, multiple signals in each embodiment of the present invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential states of the signal, and do not represent that the first potential or the second potential has a specific value in the entire text. In the embodiment of the present invention, the first potential is taken as an effective potential for illustration.

[0063] The coupling may include: direct physical contact between the two ends or indirect connection between the two ends (eg, connection between the two ends via a signal line). The embodiment of the present invention does not limit the coupling method between the two ends.

[0064] In order to improve the read stability of SRAM, an embodiment of the present disclosure provides a static memory.

[0065] Figure 1 1 is a partial circuit diagram of a static memory in an embodiment of the present disclosure, wherein the static memory includes a plurality of memory cells arranged in an array, a word line WL, and a word selection signal driving circuit. The plurality of memory cells may be arranged in a matrix array, and the memory cell may be one memory cell in the static memory.

[0066] The word line WL is connected to a plurality of memory cells in the same row and can provide a word selection signal to the memory cells.

[0067] like Figure 1 As shown, the word selection signal driving circuit includes a first switch sub-circuit 11 , a ramp sub-circuit 12 and a second switch sub-circuit 13 .

[0068] The first switch subcircuit 11 is coupled to the first control signal line WWL, the operation signal line WBL and the first node N, respectively. The first switch subcircuit 11 is configured to write the first selection signal of the operation signal line WBL to the first node N under the control of the valid signal of the first control signal line WWL. For example, when the first control signal line WWL provides a valid signal, the first switch subcircuit 11, under the control of the valid signal of the first control signal line WWL, makes the operation signal line WBL conductive with the first node N, and can write the first selection signal of the operation signal line WBL to the first node N; when the first control signal line WWL provides an invalid signal, the first switch subcircuit 11 is turned off, and the operation signal line WBL is disconnected from the first node N. The first selection signal can be a voltage signal with a constant voltage value.

[0069] The slow-changing sub-circuit 12 is coupled to the first node N, the first level line RWL and the second level line RBL respectively. The slow-changing sub-circuit 12 is configured to, when the first control signal line WWL provides an invalid signal, turn on the first level line RWL and the second level line RBL based on the signal of the first node N, and discharge the first selection signal of the first node N, so that the first node N generates a slow-changing second selection signal.

[0070] When the first control signal line WWL provides an invalid signal, the first level line RWL and the second level line RBL are turned on, so that the first selection signal of the first node N is discharged, so that the signal of the first node N is generated from the first selection signal to a second selection signal with a slow change. Since the second selection signal is formed by the discharge of the first selection signal, the second selection signal is a signal whose signal value decreases slowly. For example, the second selection signal is a signal whose voltage value decreases slowly.

[0071] The second switch subcircuit 13 is coupled to the second control signal line CON, the first node N and the word line WL, respectively. The second switch subcircuit 13 is configured to provide a second selection signal of a slow change to the word line WL under the control of the valid signal of the second control signal line CON. For example, when the second control signal line CON provides an invalid signal, the second switch subcircuit 13 is turned off; when the second control signal line CON provides a valid signal, the second switch subcircuit 13 makes the first node N conductive with the word line WL, so that the second selection signal of the first node N can be provided to the word line WL.

[0072] In the static memory of the disclosed embodiment, in the read operation, after the first selection signal of the operation signal line WBL is written into the first node N, the first control signal line WWL can provide an invalid signal, and the second control signal line CON can provide a valid signal, so that the first level line RWL and the second level line RBL are turned on, and the first selection signal of the first node N is discharged, so that the first node N generates a slowly changing second selection signal, and the slowly changing second selection signal is provided to the word line WL through the second switch sub-circuit 13, so that the voltage value of the second selection signal is slowly decreasing. When the second selection signal is provided to the word line WL, the signal on the word line WL is a slowly changing signal, that is, a slowly decreasing signal, which makes the signal value on the word line WL lower than the normal signal value in the read operation, which can improve the noise tolerance of the read operation in the SRAM and enhance the read stability.

[0073] It should be noted that in the present disclosure, the first control signal line WWL can provide a valid signal or an invalid signal, and the second control signal line CON can provide a valid signal and an invalid signal. It can be understood that the valid signal provided by the first control signal line WWL and the valid signal provided by the second control signal line CON can be the same or different, and the invalid signal provided by the first control signal line WWL and the invalid signal provided by the second control signal line CON can be the same or different, and no specific limitation is made here. The specific signal values ​​of the valid signal and the invalid signal provided by the first control signal line WWL can be set as needed, and the specific signal values ​​of the valid signal and the invalid signal provided by the second control signal line CON can be set as needed.

[0074] Figure 2is a timing diagram of a write operation of a static memory in an embodiment of the present disclosure, Figure 3 FIG. 1 is a timing diagram of a read operation of a static memory in an embodiment of the present disclosure. Figure 2 and Figure 3 As shown, after the signal provided by the first control signal line WWL changes from a valid signal to an invalid signal, the signal provided by the second control signal line CON is a valid signal.

[0075] After the signal provided by the first control signal line WWL changes from a valid signal to an invalid signal can be understood as the moment when the signal provided by the first control signal line WWL changes from a valid signal to an invalid signal, or after the moment.

[0076] When the first control signal line WWL provides a valid signal, the first switch sub-circuit 11 writes the first selection signal of the operation signal line WBL to the first node N under the control of the valid signal of the first control signal line WWL. At the moment when the signal provided by the first control signal line WWL changes from a valid signal to an invalid signal, the first node N maintains the voltage of the first selection signal. For the slow-changing sub-circuit 12, based on the signal of the first node N, the first level line RWL and the second level line RBL are turned on, and the first selection signal of the first node N is discharged, so that the first node N generates a slow-changing second selection signal. Therefore, by setting the signal provided by the second control signal line CON as a valid signal after the signal provided by the first control signal line WWL changes from a valid signal to an invalid signal, the slow-changing second selection signal can be provided to the word line WL through the second switch sub-circuit 13.

[0077] like Figure 3 As shown, in a read operation, when the signal provided by the first control signal line CON is a valid signal, the signal provided by the second control signal line CON is an invalid signal.

[0078] When the first control signal provides a valid signal, the first selection signal of the operation signal line WBL is written into the first node N. If the second control signal line CON provides an invalid signal at this time, then the first selection signal with a constant voltage value will be provided to the word line WL, resulting in a constant voltage value of the word line WL in the read operation, which reduces the read stability. By setting the signal provided by the first control signal as a valid signal, the signal provided by the second control signal line CON is an invalid signal, so that when the signal of the first node N is a constant first selection signal, the second switch unit is turned off, and the constant first selection signal is not provided to the word line WL, so that the constant voltage part on the word line WL can be eliminated, so that the signal on the word line WL is a slowly changing second selection signal, so that the signal on the word line WL is lower than the normal signal value in the read operation, thereby improving the noise margin in the read operation and improving the read stability.

[0079] For example, in a read operation, the signal provided by the second control signal line CON can be changed from an invalid signal to a valid signal within a preset time after the signal provided by the first control signal line WWL is changed from a valid signal to an invalid signal. The specific time length of the preset time length can be set as needed, for example, Figure 3 In the embodiment, the time when the signal provided by the first control signal line WWL changes from a valid signal to an invalid signal is t4, at which time the first node N starts to discharge, and at t5, the discharge of the first node N ends. Therefore, the length of the preset time length needs to be less than the time difference between t5 and t4 to ensure that the word line WL can receive the slow-changing signal and implement the read operation.

[0080] In one embodiment, in a read operation, the signal provided by the first control signal line WWL changes from a valid signal to an invalid signal, while the signal provided by the second control signal line CON changes from an invalid signal to a valid signal. This ensures that the word line WL can receive a complete slow-changing signal, ensures the length of time for the slow-changing signal on the word line WL, avoids the inability to read data due to too short a slow-changing signal time on the word line WL, and ensures that data can be effectively read from the storage element.

[0081] like Figure 2 As shown, when the first control signal line WWL provides a valid signal and the second control signal line CON provides a valid signal, the first selection signal of the operation signal line WBL is written into the first node N through the first switch sub-circuit 11, and is provided to the word line WL through the second switch sub-circuit 13. With such a setting, when the first control signal line WWL provides a valid signal and the second control signal line CON provides a valid signal, the first selection signal can be provided to the word line WL, and the first selection signal is a voltage signal with a constant voltage value. When the signal on the word line WL is the first selection signal with a constant voltage, data can be written to the selected storage element to ensure the effective writing of data.

[0082] exist Figure 2 In the embodiment, after the signal provided by the first control signal line WWL is converted from a valid signal to an invalid signal, the second control signal line CON continues to provide a valid signal. At this time, the signal provided to the word line WL is a slowly varying second selection signal.

[0083] It can be understood that when a column of memory cells in a row of memory cells is selected for a write operation, the other columns of memory cells in the row of memory cells are in a half-selected state. The memory cells in the half-selected state can be called half-selected cells. These half-selected cells are in a read operation state, and the voltage of the slowly changing second selection signal is lower than the voltage of the first selection signal. Thus, the read stability of the half-selected cells in the SRAM can be improved.

[0084] Therefore, the SRAM of the embodiment of the present disclosure can not only ensure the effective writing of data, but also improve the reading stability of the half-selected cells in the write operation.

[0085] In one embodiment, Figure 2 As shown, in the write operation, the second control signal line CON provides a continuous valid signal. That is, in the write operation, no matter whether the first control signal line WWL provides a valid signal or an invalid signal, the second control signal line CON provides a continuous valid signal. In this way, the signal provided by the second control signal line CON can be avoided from changing during the write operation, thereby improving the write stability.

[0086] Exemplarily, the valid signal of the first control signal line WWL is a high level signal. The valid signal of the second control signal line CON is a high level signal.

[0087] In other embodiments, the level values ​​of the valid signal and the invalid signal of the first control signal line WWL can be set as needed, and the level values ​​of the valid signal and the invalid signal of the second control signal line CON can be set as needed.

[0088] Exemplarily, one of the first level line RWL and the second level line RBL is connected to a high level signal, and the other is connected to a low level signal. Thus, in the slow-changing subcircuit 12, based on the signal of the first node N, the first level line RWL and the second level line RBL can form a loop after being turned on, so as to discharge the first selection signal on the first node N and obtain a slow-changing second selection signal.

[0089] Figure 4 FIG. 1 is a partial circuit diagram of a static memory in another embodiment of the present disclosure. Figure 4 As shown, the first switch subcircuit 11 may include a seventh transistor T7. The gate of the seventh transistor T7 is coupled to the first control signal line WWL, and the first electrode and the second electrode of the seventh transistor T7 are coupled to the operation signal line WBL and the first node N, respectively. When the first control signal line WWL provides an invalid signal, the first switch subcircuit 11 is turned off; when the first control signal line WWL provides a valid signal, the first switch subcircuit 11 is turned on, and the first selection signal of the operation signal line WBL is written into the first node N. In one embodiment, the seventh transistor T7 is an oxide transistor, that is, the material of the channel of the seventh transistor T7 is oxide.

[0090] For example, Figure 4As shown, the slow-changing subcircuit 12 includes an eighth transistor T8. The gate of the eighth transistor T8 is coupled to the first node N, and the first electrode and the second electrode of the eighth transistor T8 are coupled to the first level line RWL and the second level line RBL respectively. In one embodiment, the eighth transistor T8 is an oxide transistor, that is, the material of the channel of the eighth transistor T8 is oxide.

[0091] Exemplarily, the second switch subcircuit 13 includes a ninth transistor T9. The gate of the ninth transistor T9 is coupled to the second control signal line CON, and the first electrode and the second electrode of the ninth transistor T9 are coupled to the first node N and the word line WL, respectively. In one embodiment, the ninth transistor T9 is an oxide transistor, that is, the material of the channel of the ninth transistor T9 is oxide.

[0092] In one embodiment, the first switch subcircuit 11 may include a seventh transistor T7, the slow-changing subcircuit 12 includes an eighth transistor T8, and the second switch subcircuit 13 includes a ninth transistor T9, and the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all oxide transistors. Oxide transistors have the characteristics of extremely low leakage, low-temperature large-area preparation, and low cost, which can improve the integration density of SRAM and reduce static power consumption.

[0093] Exemplarily, the oxide may include amorphous and polycrystalline semiconductor materials such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO), zinc oxide (ZnO), and titanium oxide (TiO).

[0094] Therefore, the SRAM of the disclosed embodiment, by using IGZO transistors to form a word selection signal driving circuit, does not seriously lose the area of ​​the SRAM, and improves the read noise margin, improves the read stability, and improves the stability of the half-selected unit during the write operation.

[0095] In one embodiment, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are all NMOS. It is understandable that the transistors in the first switch subcircuit 11, the ramp subcircuit 12 and the second subcircuit are not limited to NMOS, and PMOS can be used as needed as long as their functions can be achieved.

[0096] It should be noted that Figure 4 FIG. 1 shows an exemplary structure of the first switch subcircuit 11, the ramp subcircuit 12, and the second switch subcircuit 13. A person skilled in the art can understand that Figure 4 The schematic diagram of each sub-circuit structure can be a simple structure of each sub-circuit. Those skilled in the art can perform the above operations based on the conventional technology in the field. Figure 4For example, the first switch subcircuit 11 may adopt a structure of more than two transistors connected in series, so that the first switch subcircuit 11 can also achieve the same function as the first switch subcircuit 11 when the structure is changed. Figure 4 Therefore, the first switch sub-circuit 11, the slow-changing sub-circuit 12 and the second switch sub-circuit 13 are not limited to Figure 4 The structure shown will suffice as long as it can achieve its function.

[0097] like Figure 1 and Figure 4 As shown, the memory cell may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6.

[0098] A gate of the first transistor T1 is coupled to the second node QB, and a first electrode and a second electrode of the first transistor T1 are coupled to the first power line and the third node Q, respectively.

[0099] A gate of the second transistor T2 is coupled to the third node Q, and a first electrode and a second electrode of the second transistor T2 are coupled to the first power line and the second node QB, respectively.

[0100] A gate of the third transistor T3 is coupled to the second node QB, and a first electrode and a second electrode of the third transistor T3 are coupled to the third node Q and the second power line, respectively.

[0101] A gate of the fourth transistor T4 is coupled to the third node Q, and a first electrode and a second electrode of the fourth transistor T4 are coupled to the second node QB and the second power line, respectively.

[0102] A gate of the fifth transistor T5 is coupled to the word line WL, and a first electrode and a second electrode of the fifth transistor T5 are coupled to the third node Q and the first transmission line BL, respectively.

[0103] A gate of the sixth transistor T6 is coupled to the word line WL, and a first electrode and a second electrode of the sixth transistor T6 are coupled to the second node QB and the second transmission line BLB, respectively.

[0104] The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all gate-all-around transistors (GAA), and illustratively, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all gate-all-around field effect transistors (GAA FET). The fifth transistor T5 and the sixth transistor T6 are both oxide transistors.

[0105] In this embodiment, in the 6T storage element, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are set to use gate-all-around transistors (GAA). GAA transistors can provide a larger driving current, and compared with fin field effect transistors (FinFETs), the parasitic resistance and parasitic capacitance of GAA transistors are significantly optimized, which can further improve the performance of SRAM.

[0106] Exemplarily, the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , and the sixth transistor T6 may all be NMOS, and the first transistor T1 and the second transistor T2 may both be PMOS.

[0107] The SRAM disclosed in the present invention may include a plurality of word lines WL and a plurality of word selection signal driving circuits, wherein the plurality of word selection signal driving circuits are coupled to the plurality of word lines WL in a one-to-one correspondence. That is, the second switch sub-circuit 13 in each word selection signal driving circuit is coupled to the corresponding word line WL to provide a second selection signal that changes slowly to the word line WL.

[0108] Figure 5 Schematic diagram of the structure of a static memory in an embodiment of the present disclosure. The SRAM of the present disclosure includes a substrate 401, a first structure layer 400 and a second structure layer 500. The first structure layer 400 is located on one side of the substrate, and the first structure layer 400 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4. The second structure layer 500 is located on the side of the first structure layer 400 away from the substrate 401, and the second structure layer 500 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9. Although the thickness of the SRAM is increased by setting the SRAM as two structure layers, the occupied area of ​​the SRAM can be reduced, which is conducive to improving the integration density of the SRAM.

[0109] The embodiment of the present disclosure also provides a static memory read and write method, which is applied to the SRAM of the embodiment of the present disclosure. The SRAM read and write method includes a write operation and a read operation.

[0110] In a write operation, a valid signal is provided to the first control signal line WWL and a valid signal is provided to the second control signal line CON, so that the first selection signal of the operation signal line WBL is written into the first node N through the first switch sub-circuit 11 and provided to the word line WL through the second switch sub-circuit 13; while the signal provided to the first control signal line WWL is changed from a valid signal to an invalid signal, the valid signal continues to be provided to the second control signal line CON, and the slow-changing sub-circuit 12 discharges the first selection signal of the first node N through the first level line RWL and the second level line RBL, so that the first node N generates a slow-changing second selection signal, and provides the slow-changing second selection signal to the word line WL through the second switch sub-circuit 13.

[0111] In the read operation, a valid signal is provided to the first control signal line WWL and an invalid signal is provided to the second control signal line CON, so that the first selection signal of the operation signal line WBL is written into the first node N through the first switch sub-circuit 11; after the signal provided to the first control signal line WWL is changed from a valid signal to an invalid signal, a valid signal is provided to the second control signal line CON, and the slow-changing sub-circuit 12 discharges the first selection signal of the first node N through the first level line RWL and the second level line RBL, so that the first node N generates a slow-changing second selection signal, and provides the slow-changing second selection signal to the word line WL through the second switch sub-circuit 13.

[0112] Combine the following Figure 2-Figure 4 The processes of the write operation and the read operation of the SRAM in the present disclosure are described in detail.

[0113] refer to Figure 2 and Figure 4 The write operation includes a first stage M1 and a second stage M2. In the write operation, in the M1 stage (i.e., t0-t1), a valid signal is provided to the first control signal line WWL and a valid signal is provided to the second control signal line CON, the seventh transistor T7 is turned on under the control of the valid signal of the first control signal line WWL, and the first selection signal of the operation signal line WBL is written into the first node N; the ninth transistor T9 is turned on under the control of the valid signal of the second control signal line CON, and the first selection signal of the first node N is provided to the word line WL, and data is written into the selected storage element.

[0114] In the M2 phase (i.e., t1-t1), an invalid signal is provided to the first control signal line WWL, a valid signal is provided to the second control signal line CON, the seventh transistor T7 is turned off, and the eighth transistor T8 discharges the first selection signal of the first node N through the first level line RWL and the second level line RBL, so that the first node N generates a slowly changing second selection signal; the ninth transistor T9 is turned on under the control of the valid signal of the second control signal line CON, and the slowly changing second selection signal of the first node N is provided to the word line WL.

[0115] It can be seen that in the write operation, the word selection signal driving circuit provides a constant level signal to the word line WL in the M1 stage, and provides a slowly decreasing level signal to the word line WL in the M2 stage. That is to say, the signal on the word line WL slowly decreases after the data is written, which can provide stability for the half-selected units in the SRAM.

[0116] refer to Figure 3 and Figure 4 , the read operation includes a third stage M3 and a fourth stage M4. In the read operation, in the M3 stage (i.e., t3-t4), a valid signal is provided to the first control signal line WWL, and an invalid signal is provided to the second control signal line CON, the seventh transistor T7 is turned on under the control of the valid signal of the first control signal line WWL, and the first selection signal of the operation signal line WBL is written into the first node N; the ninth transistor T9 is turned off. In the M4 stage (i.e., t4-t5), an invalid signal is provided to the first control signal line WWL, and a valid signal is provided to the second control signal line CON, the seventh transistor T7 is turned off, and the eighth transistor T8 discharges the first selection signal of the first node N through the first level line RWL and the second level line RBL, so that the first node N generates a slowly changing second selection signal, and the ninth transistor T9 is turned on under the control of the valid signal of the second control signal line CON, so that the slowly changing second selection signal is provided to the word line WL.

[0117] It can be seen that in the read operation, the word selection signal driving circuit provides a slowly decreasing level signal to the word line WL in the M2 phase, so that the word line WL signal is lower than the level value of the first selection signal, thereby improving the read operation noise margin and enhancing the read stability.

[0118] Figure 6 Schematic diagram of the structure of a surround gate transistor in an embodiment of the present disclosure. The following uses a surround gate transistor in the first structure layer and an oxide transistor in the second structure layer as examples to illustrate the preparation process of an SRAM in an embodiment of the present disclosure. In the following, the substrate adopts a semiconductor substrate. Among them, Figure 7A-Figure 25A as well as Figure 7B-Figure 25B They are cross-sectional views along the XX axis and YY axis directions of the center of the full-ring gate transistor during the manufacturing process, respectively, and the XX axis and the YY axis are perpendicular to each other.

[0119] In step S201, refer to Fig. 9A and Fig. 9B , a fin 406 is formed above the semiconductor substrate 401, wherein the fin 406 includes a lower fin 406-1 and an upper stacked structure located above the lower fin 406-1 to form a channel region, and the upper stacked structure includes a plurality of alternating stacks of a first semiconductor layer (i.e., the first semiconductor layer after etching) and a second semiconductor layer (i.e., the second semiconductor layer after etching).

[0120] Forming a fin 406 on the semiconductor substrate 401 may include: Fig. 7A and Figure 7B , a first semiconductor layer 402 and a second semiconductor layer 403 are periodically epitaxially grown on a semiconductor substrate 401 using a superlattice epitaxial growth process to form a plurality of epitaxial stacks; Fig. 8A and Figure 8B , forming a sacrificial layer on the plurality of epitaxial stacks by a self-aligned spacer transfer process and etching the sacrificial layer to form a first spacer 404; and referring to Fig. 9A and Fig. 9B , using the first sidewall 404 as a hard mask, the multiple epitaxial stacks and a portion of the semiconductor substrate 401 are etched to form a recessed portion and a fin 406 protruding above the recessed portion, wherein the portion of the semiconductor substrate is etched into a lower fin 406-1, and the first semiconductor layer 402 and the second semiconductor layer 403 in the multiple epitaxial stacks are respectively etched into a first semiconductor fin 406-2 and a second semiconductor fin 406-3, so that the lower fin 406-1 is aligned with the upper stack structure in a vertical direction, the material of the first semiconductor layer 402 includes silicon germanium (SiGe), and the material of the second semiconductor layer 403 includes silicon (Si).

[0121] For example, the semiconductor substrate 401 may be a bulk silicon substrate, and the semiconductor substrate 401 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0122] For example, impurities may be injected into the bulk silicon substrate, and a highly doped well region may be formed after annealing to achieve the desired well depth. The doping type of the semiconductor substrate 401 is different for different device types, wherein for a P-type semiconductor device, the highly doped well region is an N-well, and the injected impurities are n-type impurity ions, such as phosphorus (P) ions, wherein for an N-type semiconductor device, the highly doped well region is a p-well, and the injected impurities are p-type impurity ions, such as boron (B) ions.

[0123] In the embodiment of the present application, the first semiconductor layer 402 and the second semiconductor layer 403 may be formed by an epitaxial growth process. Specifically, for different device types, the materials of the first semiconductor layer 402 and the second semiconductor layer 403 may be the same, for example, the material of the first semiconductor layer 402 may be silicon germanium, and the material of the second semiconductor layer 403 may be silicon or germanium. For different device types, the materials of the first semiconductor layer 402 and the second semiconductor layer 403 may be different, for example, for a P-type semiconductor device, the material of the first semiconductor layer 402 may be silicon, and the material of the second semiconductor layer 403 may be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 402 may be silicon germanium, and the material of the second semiconductor layer 403 may be silicon.

[0124] In practical applications, silicon oxide may be formed on the semiconductor substrate 401 . The stacked structure may be formed after the silicon oxide on the semiconductor substrate 401 is removed and the semiconductor substrate 401 is cleaned.

[0125] In an embodiment of the present application, a self-aligned sidewall transfer process is used to form a first sidewall 404. The material of the first sidewall 404 is silicon nitride. The specific formation process is: a sacrificial layer is covered on the stacked structure. The material of the sacrificial layer can be polysilicon or amorphous silicon. Part of the sacrificial layer is patterned and etched away by photolithography, and silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 405, so that only the silicon nitride material on the stacked structure is retained to form the first sidewall 404. The first sidewall 404 acts as a hard mask in the subsequent photolithography for forming the fin.

[0126] In the embodiment of the present application, multiple epitaxial stacks can be etched by an etching process to form multiple periodically distributed fins (also referred to as fins), see Fig. 9A and Fig. 9B The first sidewall 404 is used as a hard mask for etching to form a fin 406 with a stacked structure. The upper part of the fin is a channel region formed by the stacked structure, and the lower part of the fin (referred to as the lower fin 406-1) is a semiconductor substrate 401, forming a Fig. 9B The fin shown in FIG. The fin includes not only a stacked structure but also a single crystal silicon structure that penetrates into the semiconductor substrate 401. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin will be used to form a nanosheet of a semiconductor device. Although Fig. 9B While one fin is shown, it should be understood that any suitable number and configuration of fins may be used in practical applications.

[0127] In step S202, refer to Figures 10A to 9BA shallow trench isolation (STI) 409 is formed on both sides of the lower fin 406 - 1 , and a dummy gate stack 410 is formed above the shallow trench isolation 409 to cross the upper stack structure and form a gate stack spacer 414 sandwiching the dummy gate stack 410 .

[0128] Forming a dummy gate stack 410 across the upper stack structure and a gate stack spacer 414 sandwiching the dummy gate stack 410 above the shallow trench isolation 409 may include: Fig. 10A and Fig. 10B , a shallow trench isolation member 409 is formed at the recessed portion (i.e., the recessed portion formed by etching the plurality of epitaxial stacks and a portion of the semiconductor substrate), wherein the top surface of the shallow trench isolation member 409 is flush with the top surface of the lower fin 406-1; Fig.11A and Fig. 11B , a gate oxide layer 411, a silicon layer 412 and a mask layer 413 are conformally deposited above the shallow trench isolation member 409 and the upper stacked structure, wherein the silicon layer 412 is an amorphous silicon layer or a polycrystalline silicon layer; the mask layer 413 is etched to form a gate mask 413, wherein the gate mask 413 is located above the central region and the sidewall of the upper stacked structure; the silicon layer 412 and the gate oxide layer 411 are etched respectively by using the gate mask 413 to form a dummy gate stack 410 spanning the upper stacked structure; refer to Fig. 12A and Fig. 12B , forming a spacer isolation dielectric layer on the opposite sidewalls of the dummy gate stack 410 ; and etching the spacer isolation dielectric layer to form a gate stack spacer 414 .

[0129] In an embodiment of the present application, a shallow trench isolation 409 can be formed between different fins. Specifically, a dielectric insulating material can be deposited first, followed by a planarization process, such as a CMP process, and then a selective etching back process of the dielectric insulating material can be performed to expose the three-dimensional fins, thereby forming a shallow trench isolation 409 adjacent to the fin. The surface of the side of the shallow trench isolation 409 away from the semiconductor substrate 401 can be flush with the surface of the side of the stacked structure in the fin close to the semiconductor substrate 401, or it can be higher or lower than the surface. The shallow trench isolation 409 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 409 is to separate the channels on adjacent fins.

[0130] In an embodiment of the present application, a dummy gate stack (also called a replacement gate stack, dummy gate) 410 is formed on the exposed fin and in a direction perpendicular to the fin line, that is, in the YY direction. The dummy gate stack 410 is a multi-layer structure, including a gate oxide layer 411, a silicon layer 412 and a mask layer 413. The dummy gate stack 410 can be formed by processes such as thermal oxidation, chemical vapor deposition, and sputtering. The dummy gate stack 410 spans the stacked structure on the upper part of the fin, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 412 can be polycrystalline silicon or amorphous silicon. The mask layer 413 is a hard mask layer, and the material of the hard mask layer 413 can be oxide, carbide, organic matter, etc.

[0131] In the embodiment of the present application, gate stack spacers 414 may be provided on both sides of the dummy gate stack along the fin line direction, i.e., the XX direction, and the gate stack spacers 414 on both sides have the same thickness. The gate stack spacers 414 may be made of a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0132] In step S203, refer to Fig.14A , 12A and Fig.16A , the exposed first end and the second end in the first semiconductor layer are replaced with an insulating dielectric (eg, silicon nitride) material to form an inner sidewall 417 , wherein the width of the inner sidewall 417 is the same as the width of the gate stack sidewall 414 .

[0133] Replacing the exposed first end and the second end of the first semiconductor layer with an insulating dielectric material to form an inner sidewall 417 may include: Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B , the upper stack structure is etched using the dummy gate stack 410 and the gate stack spacer 414 as masks to form the first semiconductor layer into a SiGe layer 407 exposing the first end and the second end (i.e., the first semiconductor fin 406-2 described above is further etched) and the second semiconductor layer is formed into a nanosheet 408 (i.e., the second semiconductor fin 406-3 described above is further etched), i.e., a nanosheet 408 exposing the end of the nanosheet is formed; refer to Fig.14A and Fig. 14B , the first end and the second end of the SiGe layer 407 are selectively etched back to form a plurality of embedded cavity structures 415 at the first end and the second end in situ, so that the opposite side walls of the upper stacked structure after the back etching have a plurality of teeth (e.g., rectangular teeth or square teeth) of the nanosheet, wherein the depth of the plurality of embedded cavity structures 415 is the same as the thickness of the gate stack spacer 414; Fig.15A and Fig. 15B, an inner sidewall insulating dielectric layer (also referred to as a dielectric layer) 416 is conformally deposited on the top surface and a portion of the sidewalls of the dummy gate stack 410, on the gate stack sidewall 414, in the embedded cavity structure, and on a plurality of teeth; and the inner sidewall insulating dielectric layer 416 is etched to remove the inner sidewall insulating dielectric layer on the top surface and a portion of the sidewalls of the dummy gate stack 410, and to remove the inner sidewall insulating dielectric layer on the gate stack sidewall and a plurality of teeth, while retaining the first end and the second end of the inner sidewall insulating dielectric layer in the plurality of embedded cavity structures to form an inner sidewall 417.

[0134] In the embodiment of the present application, after etching the SiGe layer 407, a dielectric material is deposited on the stacked structure located in the channel region, i.e., the periphery of the fin, and the dielectric material is etched to form an inner sidewall 417, and the inner sidewall 417 is flush with the nanosheet 408 in a direction perpendicular to the plane where the semiconductor substrate 401 is located. In other words, the embedded cavity structure 415 formed by etching back the SiGe layer 407 is filled with the inner sidewall 417, and the material of the inner sidewall 417 can be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, low-k material and air, wherein the material of the inner sidewall 417 is air, which means that an air cavity can be formed at the location of the inner sidewall 417, and the function of the inner sidewall 417 is achieved by utilizing the air cavity.

[0135] In step 205, refer to Fig.22A and Fig. 22B , a source region 421 - 1 and a drain region 421 - 2 are formed on the outer surface of the inner sidewall 417 , and then the dummy gate stack and the first semiconductor layer in the upper stack structure are replaced with a metal gate material layer.

[0136] refer to Fig.17A and Fig.18A , forming a drain region and a source region on the outer surface of the outer sidewall 419, which may include: Fig.17A and Fig. 17B , epitaxially growing a drain source layer 420 on the outer surface of the outer sidewall 419 and above the shallow trench isolation member 409 without changing the epitaxial growth crystal direction of the drain source layer, wherein the material of the drain source layer includes SiGe, Si or SiC; and reference Fig.18A and Fig.18B The drain-source layer is doped with a drain-source dopant to form a source region 421 - 1 and a drain region 421 - 2 .

[0137] Replacing the SiGe layer in the dummy gate stack and the plurality of epitaxial stacks with a metal gate material layer may include: referring to Fig.19A and Fig.19B , depositing a first interlayer dielectric layer 422 above the dummy gate stack, the source region, and the drain region; Fig.19A and Fig.19B, the first interlayer dielectric layer is planarized by chemical mechanical polishing process; reference Fig. 20A and Fig. 20B , removing the dummy gate stack by a dummy gate removal process to form a first opening 423, and then removing the SiGe layer by a nanosheet release process while retaining the first end and the second end of the insulating dielectric material to form a plurality of second openings 424 between adjacent nanosheets in the released nanosheets; and referring to Fig.21A and Fig. 21B A metal gate stack 433 and a metal gate material layer 429 are respectively formed in the first opening 423 and the plurality of second openings 424, wherein the metal gate stack 433 and the metal gate material layer 429 include a gate insulating dielectric layer 428, a diffusion barrier layer 425 located above the gate insulating dielectric layer 428, a work function layer 426 located above the diffusion barrier layer 425, and a conductive filling layer 427 located above the work function layer 426.

[0138] After replacing the dummy gate stack with the metal gate material layer, a contact hole of the full-all-around gate transistor is formed. Specifically, forming the contact hole of the full-all-around gate transistor includes referring to Fig.23A and Fig. 23B , chemically mechanically polishing the metal gate stack to expose the top surface of the metal gate stack; referring to Fig.24A and Fig. 24B , a second interlayer dielectric layer 430 is formed above the metal gate stack; the second interlayer dielectric layer 430 is etched to form a third opening 431, a fourth opening 432 and a fifth opening (not shown) in the second interlayer dielectric layer 430 to expose the source region, the drain region and the top surface of the metal gate stack; and tungsten contact holes are formed in the third opening 431, the fourth opening 432 and the fifth opening as source contact holes, drain contact holes and gate contact holes.

[0139] In the examples of this application, reference is made to Fig.19A and Fig.19B , a first interlayer dielectric layer 422 may be deposited on the surface of the dummy gate stack 410, the source region 421-1 and the drain region 421-2 to prevent the interconnection short circuit between the dummy gate stack 410 and the source or drain 421 in the subsequent steps, and the first interlayer dielectric layer 422 may be subjected to a chemical mechanical polishing process to make it flat. Then, as Fig. 20A and Fig. 20B As shown, the dummy gate stack 410 formed of the polysilicon or amorphous silicon is etched or corroded by a selective etching or corrosion process, that is, the dummy gate stack 410 is removed.

[0140] In the embodiment of the present application, the first semiconductor layer silicon germanium layer 407 in the channel region can be removed, that is, a nanosheet channel release process is performed, so as to form a plurality of gaps to be filled between the nanosheets, that is, a plurality of second openings 424, as shown in FIG. Fig.21Aand Fig. 21B shown.

[0141] Specifically, the silicon germanium layer 407 in the stacked structure in the channel region can be selectively etched to release the nanosheet channel. In other words, the stacked structure exposed by the fin is processed to remove each layer of the silicon germanium layer 407, which is a sacrificial layer, and release the nanosheet 408 formed by the second semiconductor layer.

[0142] In the embodiment of the present application, after the nanosheet channel is released, there are multiple gaps to be filled between the multiple nanosheets 408, and a metal gate material layer (referred to as a gate) 429 can be filled in the multiple gaps to be filled. The metal gate material layer 429 surrounds the nanosheet 408 to form a ring gate structure. The stack composed of multiple nanosheets 408 forms a channel structure, that is, a nanosheet channel of a semiconductor device is formed. Fig.23A and Fig. 23B shown.

[0143] In the embodiment of the present application, the metal gate material layer 429 may further include a multi-layer structure (not shown) such as a gate insulating dielectric layer, a diffusion barrier layer, a work function layer, and a conductive filling layer.

[0144] In actual applications, in addition to forming a metal gate material layer 429 in the gap to be filled, the gate (metal gate stack) 433 covers the first interlayer dielectric layer (also called isolation layer) 422 and the space after the dummy gate stack 410 is removed. The metal gate stack 433 covering the first interlayer dielectric layer 422 can be chemically mechanically polished and planarized.

[0145] In the embodiment of the present application, after forming the metal gate material layer 429, a dielectric deposition may be performed on the top of the semiconductor device away from the semiconductor substrate 401 to form a second interlayer dielectric layer (also referred to as a top dielectric layer) 430, as shown in FIG. Fig.24A and Fig. 24B shown.

[0146] In the embodiment of the present application, contact holes are etched in the second interlayer dielectric layer 430 to the top surface of the source region, the drain region or the gate, and metal materials are deposited in the contact holes to form source contact holes, drain contact holes and gate contact holes. Fig.25A and Fig.25B shown.

[0147] refer to Fig.26A metal layer is deposited on the upper side of the second interlayer dielectric layer 430, and the metal layer is patterned to form a first connection portion 451, a second connection portion 452, and a third connection portion 453. The first connection portion 451, the second connection portion 452, and the third connection portion 453 are respectively connected to the source region, the drain region, or the gate of the full-all-around gate transistor. The materials of the first connection portion 451, the second connection portion 452, and the third connection portion 453 can be conductive metals.

[0148] refer to Fig.27A An isolation dielectric layer 52 is deposited on the upper side of the second interlayer dielectric layer 430 formed with the first connection portion 451, the second connection portion 452 and the third connection portion 453. The isolation dielectric layer 52 may be made of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The isolation dielectric layer 52 is patterned to form a via hole exposing the third connection portion.

[0149] refer to Fig.27B A gate metal layer is deposited on the upper side of the isolation dielectric layer 52 , and the gate metal layer is patterned to form a gate 531 . The gate 531 is connected to the third connection portion 453 (not shown) through a via hole in the isolation dielectric layer 52 .

[0150] refer to Fig.27C A gate dielectric layer 54 is formed on the upper side of the gate. The gate dielectric layer 54 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0151] refer to Fig.27D An oxide semiconductor film is deposited on the upper side of the gate dielectric layer 54 by a sputtering process, and the oxide semiconductor film is patterned by a wet etching process to form an oxide semiconductor layer 551 of the oxide transistor. The oxide semiconductor layer 551 can be conductorized by a conductorization process to form a first conductorization region, a second conductorization region and a channel, respectively, and the channel is located between the first conductorization region and the second conductorization region.

[0152] refer to Fig.27E A source-drain metal layer is deposited on the upper side of the oxide semiconductor layer 551, and the source-drain metal layer is patterned to form a source electrode 561 and a drain electrode 562. The source electrode 561 and the drain electrode 562 are connected to the first conductive region and the second conductive region, respectively.

[0153] refer to Fig.27F A passivation layer 57 is deposited on the upper side of the source 561 and the drain 562. The material of the passivation layer can be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0154] refer to Figure 27G, the passivation layer is etched to form vias exposing the source 561 and the drain 562; then a metal layer is deposited on the upper side of the passivation layer, and the metal layer is patterned to form a fourth connection portion 581 and a fifth connection portion 582, and the fourth connection portion 581 and the fifth connection portion 582 are used to realize the connection in the SRAM.

[0155] Figure 27A-27G Only one oxide transistor in the second structure layer is described. It can be understood that a plurality of oxide transistors in the second structure layer can be formed simultaneously.

[0156] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0157] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0158] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0159] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0160] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0161] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A static memory, characterized in that: include: A plurality of storage elements arranged in an array; A word line connected to a plurality of the memory cells located in the same row; The word selection signal driving circuit includes a first switch subcircuit, a slow-changing subcircuit, and a second switch subcircuit, wherein: The first switch subcircuit is coupled to the first control signal line, the operation signal line and the first node respectively, and is configured to write the first selection signal of the operation signal line to the first node under the control of the valid signal of the first control signal line; The slow-changing subcircuit is coupled to the first node, the first level line and the second level line respectively, and is configured to, when the first control signal line provides an invalid signal, make the first level line and the second level line conductive based on the signal of the first node, and discharge the first selection signal of the first node, so that the first node generates a slow-changing second selection signal; The second switch subcircuit is coupled to the second control signal line, the first node and the word line respectively, and is configured to provide the second selection signal with a gradual change to the word line under the control of the effective signal of the second control signal line.

2. The static memory according to claim 1, characterized in that: After the signal provided by the first control signal line changes from a valid signal to an invalid signal, the signal provided by the second control signal line is a valid signal.

3. The static memory according to claim 2, characterized in that: In a read operation, when the signal provided by the first control signal line is a valid signal, the signal provided by the second control signal line is an invalid signal.

4. The static memory according to claim 3, characterized in that: In a read operation, the signal provided by the first control signal line changes from a valid signal to an invalid signal, while the signal provided by the second control signal line changes from an invalid signal to a valid signal.

5. The static memory according to claim 1 or 2, characterized in that: When the signal provided by the first control signal line is a valid signal and the signal provided by the second control signal line is a valid signal, the first selection signal of the operation signal line is written into the first node through the first switch sub-circuit and provided to the word line through the second switch sub-circuit.

6. The static memory according to claim 5, characterized in that: In a write operation, the second control signal line provides a continuous valid signal.

7. The static memory according to claim 1, characterized in that: The effective signal of the first control signal line is a high level signal, and the effective signal of the second control signal line is a high level signal.

8. The static memory according to claim 1, characterized in that: One of the first level line and the second level line is connected to a high level signal, and the other is connected to a low level signal.

9. The static memory according to claim 1, characterized in that: Satisfy at least one of the following: The first switch subcircuit includes a seventh transistor, a gate of the seventh transistor is coupled to the first control signal line, and a first electrode and a second electrode of the seventh transistor are respectively coupled to the operation signal line and the first node; The slow-changing subcircuit comprises an eighth transistor, a gate of the eighth transistor is coupled to the first node, and a first electrode and a second electrode of the eighth transistor are respectively coupled to the first level line and the second level line; The second switch subcircuit includes a ninth transistor, a gate of the ninth transistor is coupled to the second control signal line, and a first electrode and a second electrode of the ninth transistor are coupled to the first node and the word line, respectively.

10. The static memory according to claim 9, characterized in that: The seventh transistor is an oxide transistor; The eighth transistor is an oxide transistor; The ninth transistor is an oxide transistor.

11. The static memory according to claim 10, characterized in that: The memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein: The gate of the first transistor is coupled to the second node, and the first electrode and the second electrode of the first transistor are coupled to the first power line and the third node respectively; The gate of the second transistor is coupled to the third node, and the first electrode and the second electrode of the second transistor are coupled to the first power line and the second node respectively; The gate of the third transistor is coupled to the second node, and the first electrode and the second electrode of the third transistor are coupled to the third node and the second power line respectively; The gate of the fourth transistor is coupled to the third node, and the first electrode and the second electrode of the fourth transistor are coupled to the second node and the second power line respectively; The gate of the fifth transistor is coupled to the word line, and the first electrode and the second electrode of the fifth transistor are coupled to the third node and the first transmission line respectively; The gate of the sixth transistor is coupled to the word line, and the first electrode and the second electrode of the sixth transistor are coupled to the second node and the second transmission line respectively; The first transistor, the second transistor, the third transistor, and the fourth transistor are all surround gate transistors, and the fifth transistor and the sixth transistor are all oxide transistors.

12. The static memory according to claim 11, characterized in that: include: substrate; A first structure layer, located at one side of the substrate, the first structure layer comprising the first transistor, the second transistor, the third transistor and the fourth transistor; The second structure layer is located on a side of the first structure layer away from the substrate, and the second structure layer includes the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor.

13. The static memory according to claim 1, characterized in that: It includes a plurality of word lines and a plurality of word selection signal driving circuits, wherein the plurality of word selection signal driving circuits are coupled to the plurality of word lines in a one-to-one correspondence.

14. A method for reading and writing a static memory, characterized in that: Applied to the static memory of any one of claims 1 to 13, the method comprising: In a write operation, a valid signal is provided to the first control signal line and a valid signal is provided to the second control signal line, so that a first selection signal of the operation signal line is written into the first node through the first switch sub-circuit and provided to the word line through the second switch sub-circuit; while the signal provided to the first control signal line is changed from a valid signal to an invalid signal, a valid signal is continuously provided to the second control signal line, and the slow-changing sub-circuit discharges the first selection signal of the first node through the first level line and the second level line, so that the first node generates a slow-changing second selection signal, and the second switch sub-circuit provides the slow-changing second selection signal to the word line; In a read operation, a valid signal is provided to the first control signal line and an invalid signal is provided to the second control signal line, so that the first selection signal of the operation signal line is written into the first node through the first switch sub-circuit; after the signal provided to the first control signal line is changed from a valid signal to an invalid signal, a valid signal is provided to the second control signal line, and the slowly changing sub-circuit discharges the first selection signal of the first node through the first level line and the second level line, so that the first node generates a slowly changing second selection signal, and provides the slowly changing second selection signal to the word line through the second switch sub-circuit.

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