GaN HEMT resistant to single particle irradiation

Abstract

According to the GaN HEMT resistant to single-particle irradiation, the step-shaped structure is arranged on the side, close to the drain electrode, of the p-GaN layer, electric field gathering, close to the drain electrode side, below the grid electrode is effectively relieved, electric field peaks are restrained, and therefore the off-state blocking capacity of a device under single-particle irradiation is improved; etching holes are formed in the step-shaped structure of the p-GaN layer, metal is deposited to form an extraction electrode, excess holes induced by irradiation near the grid electrode are effectively extracted and discharged, and electron injection caused by accumulation of the holes below the grid electrode is avoided. The arrangement of the stepped structure and the extraction electrode can improve the single particle irradiation resistance of the device from the aspects of weakening an electric field and extracting excess carriers.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, relates to a GaN power device, and in particular to a GaN HEMT resistant to single particle irradiation. Background Art

[0002] GaN HEMT has the advantages of low on-resistance and high operating frequency due to the presence of high-concentration and high-mobility two-dimensional electron gas at the heterojunction interface, which is conducive to realizing low-loss and miniaturized power supply systems. In particular, it has broad application prospects in radiation scenarios such as aerospace, satellite communications, etc.

[0003] In the irradiation scenario, the incidence of high-energy particles will cause radiation-induced carriers to be generated inside the device. For GaN HEMTs with conventional structures, there is a serious electric field concentration at the gate edge close to the drain side. The strong electric field in this area will further lead to the collision ionization of radiation-induced carriers, generating more unbalanced carriers, which will lead to increased leakage and even device burning.

[0004] Therefore, for the application and development of GaN HEMT in radiation scenarios, corresponding improvements need to be made to the device structure to effectively suppress the electric field spikes near the gate, extract non-equilibrium holes, and enhance the GaN HEMT's ability to resist single-particle radiation. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a GaN HEMT resistant to single particle irradiation. The present invention sets a stepped structure near the drain side of the p-GaN layer to effectively alleviate the electric field concentration near the drain side under the gate and suppress the electric field spike, thereby improving the off-state blocking ability of the device under single particle irradiation; an etched hole is set on the stepped structure of the p-GaN layer, and metal is deposited to form an extraction electrode, which effectively extracts and discharges the excess holes induced by irradiation near the gate, and avoids electron injection caused by the accumulation of holes under the gate. The setting of the stepped structure and the extraction electrode can improve the device's resistance to single particle irradiation by weakening the electric field and extracting excess carriers, respectively.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The present invention provides a GaN HEMT resistant to single particle irradiation, wherein the GaN The HEMT comprises a substrate, a buffer layer, a channel layer, a barrier layer and a first passivation layer from bottom to top, wherein a first source and a drain are arranged on both sides of the channel layer, a p-GaN layer is arranged between the first source and the drain near the first source, at least one layer of stepped structure from high to low is arranged near the drain, the stepped structure region is a non-gate region of the p-GaN layer, the non-stepped structure region of the p-GaN layer near the first source is a gate region of the p-GaN layer, and a gate is arranged on the gate region of the p-GaN layer; etching holes arranged at intervals along the y direction are arranged on the stepped structure of the p-GaN layer, extraction electrodes are arranged in the etching holes, and the extraction electrodes are in contact with the sidewalls and the bottom along the etching holes; a second source is arranged near the first source, and the first source is connected to the extraction electrode and the second source through a metal interconnection layer; except for the top surfaces of the extraction electrode, the first source, the second source and the drain, the rest of the surface is filled with the second passivation layer.

[0008] As a preferred embodiment of the present invention, the number of steps in the non-gate region of the p-GaN layer is one or more, the size of each step is not required to be equal, the spacing from the bottom step to the drain is greater than 0, and the height of the highest step is less than the height of the gate region of the p-GaN layer.

[0009] In the present invention, the height of a step is defined as the distance from the top of the step to the upper surface of the barrier layer.

[0010] As a preferred solution of the present invention, the depth of the extraction electrode and the depth of the second source are independent.

[0011] As a preferred embodiment of the present invention, the etched hole is etched to the upper surface or the inside of the buffer layer; or the etched hole is etched to the upper surface or the inside of the channel layer. The shape of the etched cross section of the etched hole forming the extraction electrode in the xy plane is circular, elliptical, polygonal or other irregular edge shapes, and the shapes and sizes of the etched cross sections of adjacent etched holes in the xy plane are the same or different; the ratio of the projected length of the etched hole in the y direction to the length of the p-GaN layer in the y direction is 5%-90%.

[0012] As a preferred solution of the present invention, the second source electrode extends into the buffer layer through the barrier layer and the channel layer; or the second source electrode extends into the channel layer through the barrier layer; or the second source electrode passes through the barrier layer and the channel layer to contact the upper surface of the buffer layer; or the second source electrode passes through the barrier layer to contact the upper surface of the channel layer.

[0013] As a preferred solution of the present invention, the gate is one or a combination of Schottky-type p-GaN gate, ohmic p-GaN gate, recessed gate structure, MIS gate, or a complex gate structure having the above gate structure characteristics.

[0014] As a preferred solution of the present invention, the p-GaN layer doping concentration is 1×10 17 cm -3 Up to 1×10 21 cm -3 , wherein the height of the gate region of the p-GaN layer is 50nm to 150nm, and the size along the x-direction is 500nm to 5000nm; the height of each step in the non-gate region of the p-GaN layer is 5nm to 120nm, and the size of each step along the x-direction is 500nm to 5000nm.

[0015] As a preferred solution of the present invention, the non-gate region of the p-GaN layer is a slope structure, and the angle between the slope and the upper surface of the barrier layer is ≥2°.

[0016] In the present invention, 2°≤the angle between the inclined surface and the upper surface of the barrier layer<90°. When the angle between the inclined surface and the upper surface of the barrier layer is 90°, the inclined surface becomes a step-like structure.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1) In the present invention, the non-gate region of the p-GaN layer and the gate region of the p-GaN layer are finely parameterized (such as the number of steps, the size of each step, etc.). In the blocking state, the stepped structure of the non-gate region of the p-GaN layer can be fully depleted, thereby effectively alleviating the electric field concentration under the gate near the drain side, effectively reducing the peak electric field intensity, and fully reducing the transient current caused by irradiation, thereby improving the device's ability to resist single particle irradiation.

[0019] 2) The extraction electrode in the present invention can fully collect and discharge the excess holes induced by radiation, weaken the accumulation of holes in the area below the gate, and further enhance the device's ability to resist single-particle radiation through fine parameter settings (such as the position of the extraction electrode relative to the step, the size of the electrode, the ratio of the projection length of the extraction electrode in the y direction to the length of the p-GaN layer in the y direction, etc.).

[0020] 3) The stepped structure of the non-gate region of the p-GaN layer of the present invention not only alleviates the electric field concentration and improves the radiation resistance of the device, but also helps to alleviate the dynamic resistance problem related to the electric field concentration and improve the dynamic conduction performance of the device.

[0021] 4) The manufacturing process of the device structure in the present invention is fully compatible with the traditional process and does not add any additional complex process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] FIG. 1( a ) is a schematic diagram of Embodiment 1 of the present invention.

[0024] FIG. 1( b ) is a cross-sectional view taken along line AA′ in FIG. 1( a ).

[0025] FIG. 1( c ) is a cross-sectional view taken along line BB′ in FIG. 1( a ).

[0026] Figure 2 It is a schematic diagram of step 1 of the present invention.

[0027] Figure 3 It is a schematic diagram of step 2 of the present invention.

[0028] Figure 4 It is a schematic diagram of step 3 of the present invention.

[0029] Figure 5 It is a schematic diagram of step 4 of the present invention.

[0030] Figure 6 It is a schematic diagram of step 5 of the present invention.

[0031] Figure 7 It is a schematic diagram of step 6 of the present invention.

[0032] Figure 8 It is a schematic diagram of step 7 of the present invention.

[0033] Fig. 9 It is a schematic diagram of step 8 of the present invention.

[0034] Fig.10 It is a schematic diagram of step 9 of the present invention.

[0035] Fig.11 It is a schematic diagram of step 10 of the present invention.

[0036] Fig.12 It is a schematic diagram of step 11 of the present invention.

[0037] Fig.13 It is a schematic diagram of step 12 of the present invention.

[0038] Fig.14 It is a schematic diagram of step 13 of the present invention.

[0039] Fig.15It is a schematic diagram of step 14 of the present invention.

[0040] Fig.16 It is a schematic diagram of step 15 of the present invention.

[0041] Fig.17 It is a schematic diagram of step 16 of the present invention.

[0042] FIG. 18( a ) is a schematic diagram of Embodiment 2 of the present invention.

[0043] FIG. 18( b ) is a cross-sectional view taken along line AA′ in FIG. 18( a ).

[0044] FIG. 18( c ) is a cross-sectional view taken along line BB′ in FIG. 18( a ).

[0045] FIG. 19( a ) is a schematic diagram of Embodiment 3 of the present invention.

[0046] FIG. 19( b ) is a cross-sectional view taken along line AA′ in FIG. 19( a ).

[0047] FIG. 19( c ) is a cross-sectional view taken along line BB′ in FIG. 19( a ).

[0048] FIG. 20( a ) is a schematic diagram of embodiment 4 of the present invention.

[0049] FIG. 20( b ) is a cross-sectional view taken along line AA′ in FIG. 20( a ).

[0050] FIG. 20( c ) is a cross-sectional view taken along line BB′ in FIG. 20( a ).

[0051] Figure 21(a) is a schematic diagram of Example 5 of the present invention.

[0052] FIG. 21( b ) is a cross-sectional view taken along line AA′ in FIG. 21( a ).

[0053] FIG. 21( c ) is a cross-sectional view taken along line BB′ in FIG. 21( a ).

[0054] Fig. 22 This is the electric field distribution diagram on the surface of the channel layer of devices with the same stepped structure thickness and different lengths and devices without a stepped structure under a voltage of 400V.

[0055] In the figure, 1. substrate; 2. buffer layer; 3. channel layer; 4. barrier layer; 5. first passivation layer; 6. first source; 7. drain; 8-1. p-GaN layer gate region, 8-2. p-GaN layer non-gate region; 9. gate; 10. extraction electrode; 11. second source; 12. metal interconnect layer; 13. second passivation layer; 14. hole storage layer. DETAILED DESCRIPTION

[0056] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0057] The preparation process of the present invention is an existing process, comprising the following steps:

[0058] 1) Select a substrate layer. The material of the substrate layer includes but is not limited to one of silicon, silicon carbide, sapphire, gallium nitride, gallium oxide and diamond, or several of them, or other complex materials with the above material components, or a complex material substrate such as a QST substrate. The size of the substrate layer includes but is not limited to two inches, four inches, and six inches.

[0059] 2) The growth method of the buffer layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the buffer layer includes but is not limited to growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials under the conditions of temperature of 0-1500°C and pressure of 0-300Torr, or several of them, or other complex materials with the above material components as the device buffer layer. The buffer layer structure is composed of at least one layer of material, and also includes but is not limited to one of the various complex structure designs such as AlGaN stress release layer with gradient Al component, superlattice structure, low-temperature grown AlN structure, or a combination of several of them, or other complex structures with the above structural characteristics.

[0060] 3) The growth method of the channel layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the channel layer includes but is not limited to growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components as the device channel layer under the conditions of temperature of 0-1500°C and pressure of 0-300Torr. The channel layer is composed of at least one layer of semiconductor material, and also includes but is not limited to various complex structural designs.

[0061] 4) The growth method of the barrier layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the barrier layer includes but is not limited to growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components as the device barrier layer under the conditions of temperature of 0-1500°C and pressure of 0-300Torr. The barrier layer is composed of at least one layer of semiconductor material, and also includes but is not limited to various complex structural designs.

[0062] 5) The growth method of the p-GaN layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the p-GaN layer includes but is not limited to growing the p-GaN layer at a temperature of 0 to 1500°C and a pressure of 0 to 300 Torr. The p-GaN layer is composed of at least one layer of semiconductor material, and also includes but is not limited to various complex structural designs.

[0063] 6) The etching method of the p-GaN layer includes but is not limited to one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the p-GaN layer includes but is not limited to etching the p-GaN layer under the conditions of RF power of 0 to 600W and pressure of 0 to 100mTorr.

[0064] 7) The growth method of the first source and drain includes but is not limited to one of the coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The growth process of the first source and drain includes but is not limited to growing one of the materials including but not limited to Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of them, or other complex materials with the above material components as the first source and drain of the device under the conditions of temperature of 0-1200°C and pressure of 0-300Torr, and the annealing method includes but is not limited to annealing at 95-1500°C.

[0065] 8) The deposition method of the first passivation layer and the second passivation layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The deposition process of the first passivation layer and the second passivation layer includes but is not limited to deposition under the conditions of temperature of 0 to 1500°C and pressure of 0 to 300 Torr, including but not limited to (Al x Ga 1-x )2O3, Al2O3, AlN, SiN x , SiO2, HfO2, ZrO2, SOG, PI, SiON, HfZrO and other materials, or several of them, or a composite material composed of other multiple materials with the above material components as the first passivation layer and the second passivation layer of the device. The first passivation layer and the second passivation layer structure are composed of at least one layer, and include but are not limited to various complex structure designs.

[0066] 9) The etching method of the first passivation layer and the second passivation layer includes but is not limited to one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the first passivation layer and the second passivation layer includes but is not limited to etching the first passivation layer and the second passivation layer under the conditions of RF power of 0 to 600 W and pressure of 0 to 100 mTorr.

[0067] 10) The gate growth method includes but is not limited to one of the coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The gate growth process includes but is not limited to growing one of the materials including but not limited to Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of them, or other complex materials with the above-mentioned material components as the device gate under the conditions of temperature of 0-1200°C and pressure of 0-300Torr, and the annealing method includes but is not limited to annealing at 95-1500°C.

[0068] 11) The etching methods of the buffer layer, channel layer and barrier layer include but are not limited to one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the buffer layer, channel layer and barrier layer includes but is not limited to etching under the conditions of RF power of 0 to 600W and pressure of 0 to 100mTorr.

[0069] 12) The growth method of the extraction electrode, the second source electrode and the metal interconnection layer includes but is not limited to one of the coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The growth process of the extraction electrode, the second source electrode and the metal interconnection layer includes but is not limited to growing one of the materials including but not limited to Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of them, or other complex materials with the above-mentioned material components as the device extraction electrode, the second source electrode and the metal interconnection layer under the conditions of temperature of 0-1200°C and pressure of 0-300Torr, and the annealing method includes but is not limited to annealing at 95-1500°C.

[0070] Example 1

[0071] See also Figure 1(a)-Figure 1(c) The present invention provides a GaN HEMT resistant to single particle irradiation. The GaN HEMT resistant to single particle irradiation includes a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4 and a first passivation layer 5 from bottom to top. A first source 6 and a drain 7 are respectively provided on both sides of the channel layer 3. A p-GaN layer is provided between the first source 6 and the drain 7 near the first source 6, and the p-GaN layer is composed of a p-GaN layer gate region 8-1 near the first source 6 and a p-GaN layer non-gate region 8-2 near the drain 7. A gate 9 is provided on the p-GaN layer gate region 8-1, and the p-GaN layer non-gate region 8-2 includes a stepped structure. Etched holes are provided in the p-GaN layer non-gate region 8-2 along the y direction, and the bottom of the etched holes is located inside the buffer layer 2. The etched holes are provided with extraction electrodes 10. A second source 11 is provided near the first source 6, and the first source 6, the extraction electrode 10 and the second source 11 are connected through a metal interconnection layer 12. Except for the top surfaces of the extraction electrode 10, the first source 6, the second source 11 and the drain 7, the rest of the surface is filled with a second passivation layer 13.

[0072] In this embodiment, the size of the p-GaN layer gate region in the x direction is 3 μm, the size in the y direction is 60 μm, and the height is 100 nm. The size of the p-GaN layer non-gate region in the x direction is 3 μm, the size in the y direction is 60 μm, and the height is 20 nm.

[0073] In this embodiment, the number of extraction electrodes arranged at intervals on the non-gate region of the p-GaN layer is 4. The shapes of the etched holes of the extraction electrodes on the first and second passivation layers are rectangular, the dimensions in the x-direction are 2 μm, the dimensions in the y-direction are 6 μm, and the spacing between adjacent etched holes is 10 μm. The shapes and dimensions of the openings of adjacent extraction electrodes on the first and second passivation layers are consistent. The shapes of the etched holes forming the extraction electrodes on the buffer layer, channel layer, and barrier layer are all rectangular, the dimensions in the x-direction are all 1.2 μm, and the dimensions in the y-direction are all 5 μm.

[0074] The distance between the gate and the first source is 1μm, and the distance between the gate and the drain is 15μm; the size of the first source and the drain in the x-direction is 3μm; the spacing from the second source to the first source is 1μm, and the size of the second source in the x-direction is 3μm, and the bottom of the second source is located inside the buffer layer, 50nm away from the upper surface of the buffer layer.

[0075] The distance between the interconnection metal connecting the extraction electrode, the second source and the first source and the drain electrode is 10 μm near the drain electrode.

[0076] The substrate material of the device of the present invention includes but is not limited to one of silicon, silicon carbide, sapphire, gallium nitride, gallium oxide and diamond, or several of them, or other complex materials with the above material components, or complex material substrates such as QST substrates. In this embodiment, silicon is selected as the substrate.

[0077] The buffer layer of the device of the present invention includes but is not limited to one of the materials of group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components. The buffer layer structure of the device of the present invention is composed of at least one layer of material, and also includes but is not limited to one of various complex structure designs such as AlGaN stress release layer with gradual Al component change, superlattice structure, low temperature grown AlN structure, or a combination of several of them, or other complex structures with the above structural characteristics. In this embodiment, an AlN layer with a thickness of 50nm and a GaN layer with a thickness of 3000nm are selected from bottom to top as the buffer layer.

[0078] The channel layer of the device of the present invention includes but is not limited to one of the materials such as group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components. The channel layer is composed of at least one layer of semiconductor material, and includes but is not limited to various complex structural designs. In this embodiment, GaN with a thickness of 300nm is selected as the channel layer.

[0079] The barrier layer of the device of the present invention includes but is not limited to one of the materials of group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components. The barrier layer is composed of at least one layer of semiconductor material, and includes but is not limited to various complex structural designs. In this embodiment, AlGaN with an Al component of 0.20 and a thickness of 15nm is selected as the barrier layer.

[0080] The Mg doping concentration of the p-GaN layer of the device of the present invention can be 1×10 17 ~1×10 21 cm -3 The thickness can be 0 to 500 nm. In this embodiment, the doping concentration is 1×10 19 cm -3 , a p-GaN layer with a thickness of 100nm.

[0081] The gate material of the device of the present invention includes but is not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon and other materials, or several of them, or other complex materials with the above material components. The gate structure of the device of the present invention includes but is not limited to one or several combinations of Schottky-type p-GaN gate, ohmic p-GaN gate, recessed gate, MIS gate, or other complex gate structures with the above gate features. In this embodiment, 20nm Ni and 80nm Au are selected as the gate metal of the device to form a Schottky contact with the p-GaN layer.

[0082] The first source and drain materials of the device of the present invention include but are not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon and other materials, or several of them, or other complex materials with the above material components. The structure of the drain of the device of the present invention includes but is not limited to one of Schottky drain and ohmic drain or a combination of two, or other complex drain structures with Schottky drain and ohmic drain characteristics. The structure of the first source of the device of the present invention includes but is not limited to one of Schottky source and ohmic source or a combination of two, or other complex source structures with Schottky source and ohmic source characteristics. In this embodiment, 20nm Ti, 150nm Al, 50nm Ni, and 80nm Au are selected as the first source and drain metals of the device to form ohmic contacts with the channel layer.

[0083] The second source material of the device of the present invention includes but is not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon and the like, or several of them, or other complex materials having the above material components. The structure of the source of the device of the present invention includes but is not limited to one of Schottky source and ohmic source or a combination of two, or other complex source structures having Schottky source and ohmic source characteristics. In this embodiment, 20nm Ni and 200nm Au are selected as the second source material of the device to form Schottky contact with the semiconductor layer at the side wall and bottom of the etched hole.

[0084] The extraction electrode material of the device of the present invention includes but is not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of them, or other complex materials with the above material components. In this embodiment, 20nm Ni and 200nm Au are selected as the extraction electrode material of the device to form Schottky contact with the semiconductor layer on the side wall and bottom of the etched hole.

[0085] The metal interconnection layer material of the device of the present invention includes but is not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of them, or other complex materials having the above material components. In this embodiment, 20nm Ni and 200nm Au are selected as the metal interconnection layer materials of the device.

[0086] See also Figure 2-Figure 17 This embodiment provides a process for preparing a GaN HEMT resistant to single particle irradiation, and the preparation method is as follows Figure 1(a)-Figure 1(c) The specific steps of the single-particle irradiation-resistant GaN HEMT shown are as follows:

[0087] 1) Select a substrate. In this embodiment, a two-inch Si (111) substrate is used as the substrate. First, it is placed in a mixed solution of three parts sulfuric acid, one part hydrogen peroxide and one part water for pickling, and then placed in a 5% hydrofluoric acid solution to remove surface oxides. Finally, acetone, isopropanol and anhydrous ethanol are used to clean the substrate surface in sequence, and finally the substrate is placed in water, taken out and blown dry. Figure 2 .

[0088] 2) Growth of buffer layer. In this embodiment, trimethylaluminum (TMAl) and NH3 are introduced into the MOCVD reaction chamber to grow a 50nm thick AlN layer on the substrate at a temperature of 1120°C and a pressure of 70Torr. The introduction of TMAl is stopped, and the introduction of NH3 is continued to raise the temperature to 1200°C for high temperature treatment. After the AlN layer is grown, trimethylgallium (TMGa) and NH3 are introduced into the MOCVD reaction chamber to grow a 3000nm thick GaN layer at a temperature of 900°C and a pressure of 70Torr. Figure 3 .

[0089] 3) Growing the channel layer. In this embodiment, after growing the buffer layer, TMGa and NH3 are introduced into the MOCVD reaction chamber, and GaN with a thickness of 300 nm is grown as the channel layer at a temperature of 900°C and a pressure of 70 Torr. Figure 4 .

[0090] 4) Growth of barrier layer. In this embodiment, after the channel layer is grown, TMAl is gradually introduced into the MOCVD reaction chamber and TMGa is reduced. AlGaN with an Al component of 0.20 and a thickness of 15 nm is grown as a barrier layer at a temperature of 960° C. and a pressure of 70 Torr. Figure 5 .

[0091] 5) Growth of p-GaN layer. In this embodiment, the p-GaN layer is epitaxially grown after the barrier layer is grown. TMGa, dipentyl magnesium (Cp2Mg), NH3 and H2 are introduced into the MOCVD reaction chamber. The growth temperature is 940°C and the pressure is 70 Torr. The doping concentration is 1×10 19 cm -3 , a p-GaN layer with a thickness of 100 nm, and annealed at a temperature of 700°C, such as Figure 6 .

[0092] 6) First etching of the p-GaN layer. In this embodiment, after the p-GaN layer is grown, ICP etching is performed to remove the 80 nm thick p-GaN in the region other than the gate region of the p-GaN layer. The ICP power is set to 100 W, the pressure is set to 5 mTorr, and Cl2, O2 and Ar are introduced. Figure 7 .

[0093] 7) Second etching of the p-GaN layer. In this embodiment, a second ICP etching is performed after the first etching of the p-GaN layer to remove the 20 nm thick p-GaN layer except the non-gate region of the p-GaN layer and the gate region of the p-GaN layer. The ICP power is set to 100 W, the pressure is set to 5 mTorr, and Cl2, O2 and Ar are introduced. Figure 8 .

[0094] 8) Etch and deposit the drain and the first source, use ICP etching to remove the barrier layer in the area below the first source and drain, set the ICP power to 100W, the pressure to 5mTorr, and pass Cl2, O2 and Ar. Use E-beam evaporation deposition to deposit 20nm Ti, 150nm Al, 50nm Ni, and 80nm Au in sequence, and selectively remove the metal except the first source and drain area by stripping, and anneal at 830℃, as shown in Figure 8. Fig. 9 .

[0095] 9) Grow the first passivation layer by using PECVD at a temperature of 300°C and a pressure of 850 mTorr, introducing N2O and 5% SiH4 / N2 to deposit 80 nm of SiO2 as the first passivation layer. Fig.10 .

[0096] 10) Etching the first passivation layer, using RIE etching to remove the first passivation layer of the gate region, the extraction electrode region, the first source region, the drain region, and the second source region, setting the RIE power to 200W, the pressure to 3-10mTorr, and passing CHF3 and Ar, such as Fig.11 .

[0097] 11) Deposit the gate, use E-beam evaporation deposition to deposit 20nm Ni and 80nm Au in sequence, selectively remove the metal outside the gate area by stripping, and anneal at 300℃, as shown in Fig.12 .

[0098] 12) growing a second passivation layer, using PECVD at a temperature of 300°C and a pressure of 850 mTorr to pass N2O and 5% SiH4 / N2 to deposit 500 nm of SiO2 as the second passivation layer, as shown in FIG. Fig.13 .

[0099] 13) Etching the second passivation layer, using RIE etching to remove the second passivation layer of the extraction electrode region, the first source region, the drain region, and the second source region, setting the RIE power to 200W, the pressure to 3-10mTorr, and passing CHF3 and Ar, such as Fig.14 .

[0100] 14) Etching the barrier layer, channel layer and part of the buffer layer in the second source region, using ICP etching to remove the barrier layer, channel layer and part of the buffer layer in the second source region, setting the ICP power to 100W, the pressure to 5mTorr, and passing Cl2, O2 and Ar. In this embodiment, etching is performed to 50nm below the upper surface of the buffer layer, as shown in FIG. Fig.15 .

[0101] 15) Etching the barrier layer, channel layer and part of the buffer layer in the extraction electrode region, using ICP etching to remove the barrier layer, channel layer and part of the buffer layer in the extraction electrode region, setting the ICP power to 100W, the pressure to 5mTorr, and passing Cl2, O2 and Ar. In this embodiment, etching is performed to 50nm below the upper surface of the buffer layer, as shown in FIG. Fig.16 .

[0102] 16) Deposit the extraction electrode, the second source electrode and the metal interconnection layer, use E-beam evaporation deposition to deposit 20nm of Ni and 200nm of Au in sequence, and selectively remove the metal in the area other than the extraction electrode, the second source electrode, the metal interconnection layer, the first source electrode and the drain electrode by stripping, such as Fig.17 .

[0103] Example 2

[0104] like Figure 18(a)-Figure 18(c) In this embodiment, a hole storage layer 14 is introduced between the buffer layer 2 and the channel layer 3 during the epitaxial layer growth process. The hole storage layer 14 can be made of AlGaN with an Al component of 0.20 and a thickness of 10 nm. The rest of the structure and preparation process are the same as those of Example 1.

[0105] Example 3

[0106] like Figure 19(a)-Figure 19(c) In this embodiment, the number of steps in the non-gate region 8-2 of the p-GaN layer is 2, the bottom of the extraction electrode 10 is located inside the buffer layer 2, and the rest of the structure and preparation process are the same as those in Embodiment 1.

[0107] Example 4

[0108] like Figure 20(a)-Figure 20(c) In this embodiment, the bottom of the second source electrode 11 is located inside the channel layer 3, and the bottom of the extraction electrode 10 is located inside the buffer layer 2. The remaining structures and preparation processes are the same as those in the first embodiment.

[0109] Example 5

[0110] like Figure 21(a)-Figure 21(c) In this embodiment, the non-gate region 8-2 of the p-GaN layer is a bevel. In the present invention, 2°≤the angle between the bevel and the upper surface of the barrier layer is less than 90°. When the angle between the bevel and the upper surface of the barrier layer is 90°, the bevel becomes a stepped structure. In this embodiment, the angle between the bevel and the upper surface of the barrier layer is 4°. The rest of the structure and preparation process are the same as those in Example 1. The bevel-shaped stepped area can more effectively alleviate the electric field concentration phenomenon under the gate near the drain side.

[0111] Fig. 22The results show that the distance between the gate and the drain is 10 μm, no staircase structure is set, and a single step structure is set with the length of the step in the x direction of 1 μm, 2 μm, and 3 μm, and the height is 20 nm. The blocking state (V DS =400V), the electric field intensity distribution at different positions on the upper surface of the channel layer shows that the setting of the stepped structure can effectively alleviate the electric field concentration, reduce the peak value of the electric field intensity, and improve the device's radiation resistance.

[0112] The above embodiments are only part of the possible structures of the present invention. In practical applications, parameters such as material selection, thickness and doping concentration design of each layer, specific HEMT structure design (such as whether there are other semiconductor layers between the buffer layer, channel layer and barrier layer, whether there are other semiconductor layers between the substrate and the buffer layer, other gate types, SOI structure devices, gradient semiconductor layer composition, drain and similar designs), the number of steps in the non-gate region of the specific stepped p-GaN layer, the shape and size of each step, the position of the extraction electrode relative to the step, the size of the extraction electrode relative to the p-GaN layer in the y direction, etc. The aspect ratio, the specific depth of the etching hole for forming the extraction electrode, the specific shape and size of the etching hole for forming the extraction electrode, the specific shape and size of the gate electrode, the specific spacing between the extraction electrode and the gate electrode, the specific depth of the second source, the specific shape and size of the second source, the specific shape and size of other key structures, the type of gold semiconductor contact, the position, depth and shape of the gold semiconductor contact can be appropriately changed according to different application conditions. In addition, the buffer layer, the channel layer, and the barrier layer refer to the layer that should have at least one layer of structure, rather than only one layer of structure. Without departing from the principles of the present invention, these changes should also be regarded as the scope of protection of the present invention.

[0113] The above is only a preferred embodiment of the present invention, and is not any formal or substantial limitation of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the method of the present invention, and these improvements and supplements should also be regarded as the protection scope of the present invention. Any technician familiar with this profession, without departing from the spirit and scope of the present invention, can make some changes, modifications and evolutions of the technical content disclosed above, which are equivalent embodiments of the present invention; at the same time, any changes, modifications and evolutions of any equivalent changes made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A GaN HEMT resistant to single particle irradiation, characterized in that: The single-particle irradiation-resistant GaN The HEMT comprises a substrate, a buffer layer, a channel layer, a barrier layer and a first passivation layer from bottom to top, wherein a first source and a drain are arranged on both sides of the channel layer, a p-GaN layer is arranged between the first source and the drain near the first source, and at least one layer of stepped structure from high to low is arranged near the drain side of the p-GaN layer, the stepped structure region is a non-gate region of the p-GaN layer, and the non-stepped structure region of the p-GaN layer near the first source side is a gate region of the p-GaN layer, and a gate is arranged on the gate region of the p-GaN layer; etching holes arranged at intervals along the y direction are arranged on the non-gate region of the p-GaN layer, and extraction electrodes are arranged in the etching holes, and the extraction electrodes are in contact with the sidewalls and the bottom along the etching holes; a second source is arranged near the first source, and the first source is connected to the extraction electrode and the second source through a metal interconnection layer; and except for the top surfaces of the extraction electrode, the first source, the second source and the drain, the rest of the surface area is filled with the second passivation layer.

2. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The number of steps in the non-gate region of the p-GaN layer is one or more, the size of each step is not required to be equal, the spacing from the bottom step to the drain is greater than 0, and the height of the highest step is less than the height of the gate region of the p-GaN layer.

3. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The depth of the extraction electrode is independent of the depth of the second source.

4. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The bottom of the etching hole is located on the upper surface or inside of the buffer layer; or the bottom of the etching hole is located on the upper surface or inside of the channel layer; the shape of the etching cross section of the etching hole in the xy plane is circular, elliptical, polygonal or other irregular edge shapes, and the shapes and sizes of the etching cross sections of adjacent etching holes in the xy plane are the same or different; the ratio of the projection length of the etching hole in the y direction to the length of the p-GaN layer in the y direction is 5%-90%.

5. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The depths of adjacent etched holes are the same or different.

6. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The extraction electrode forms a Schottky contact or an Ohmic contact with the semiconductor layer at the sidewall and the bottom.

7. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The second source electrode extends into the buffer layer through the barrier layer and the channel layer; or the second source electrode extends into the channel layer through the barrier layer; or the second source electrode contacts the upper surface of the buffer layer through the barrier layer and the channel layer; or the second source electrode contacts the upper surface of the channel layer through the barrier layer.

8. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The gate is one or a combination of Schottky-type p-GaN gate, Ohmic-type p-GaN gate, recessed gate structure, MIS gate, or a complex gate structure having the above gate structure characteristics.

9. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The doping concentration of the p-GaN layer is 1×10 17 cm -3 Up to 1×10 21 cm -3 , wherein the height of the gate region of the p-GaN layer is 50nm to 150nm, and the size along the x-direction is 0.5μm to 5μm; the height of each step in the non-gate region of the p-GaN layer is 5nm to 120nm, and the size of each step along the x-direction is 0.5μm to 5μm.

10. A GaN HEMT resistant to single particle irradiation according to any one of claims 1 to 9, characterized in that the non-gate region of the p-GaN layer is a slope structure, and the angle between the slope and the upper surface of the barrier layer is ≥2°.

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