Display substrate and display device

Abstract

A display substrate includes an array substrate and a color film substrate. The array substrate includes a first substrate, a first conductive layer, a first insulating layer, a first via, a semiconductor layer and a connecting electrode. The first conductive layer includes first signal lines and a first pattern distributed at intervals. The first insulating layer is disposed on a side of the first conductive layer away from the first substrate. The first via penetrates at least the first insulating layer and exposes at least part of the first signal lines. The semiconductor layer includes a semiconductor pattern. The semiconductor pattern includes a first portion, a second portion and a channel structure between the first portion and the second portion. A normal projection of the first portion on the first substrate partially overlaps a normal projection of the first signal lines on the first substrate, and a normal projection of the channel structure on the first substrate is within a range of a normal projection of the first pattern on the first substrate. The connecting electrode is disposed on a side of the semiconductor layer away from the first substrate, at least part of the connecting electrode is located in the first via, and the connecting electrode is connected to the first portion and the first signal lines, respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] With the continuous development of display technology, display devices have been widely applied, and people's requirements for display devices are also getting higher and higher. Among them, high pixel density (Pixels Per Inch; PPI for short) is an important development direction of display devices. Common display devices can include liquid crystal display devices (Liquid Crystal Display; LCD for short) and organic light-emitting diode display devices (Organic Light-Emitting Diode; OLED for short). Due to the simpler pixel circuit structure of liquid crystal display devices (which can contain fewer thin film transistors and capacitors), liquid crystal display devices have more advantages in ultra-high pixel density (such as greater than or equal to 1000 PPI). With the increase of pixel density, the aperture ratio of the display device gradually decreases, resulting in a decrease in the transmittance (transmittance / light transmittance) of the display device. How to improve the aperture ratio and light transmittance of the display device is an important technical problem faced by liquid crystal display devices. SUMMARY

[0003] In one aspect, a display substrate is provided. The display substrate includes an array substrate and a color film substrate. The array substrate includes a first substrate, a first conductive layer, a first insulating layer, a first via, a semiconductor layer, and a connection electrode. The first conductive layer is disposed on one side of the first substrate and includes a first signal line and a first pattern distributed at intervals. The first insulating layer is disposed on a side of the first conductive layer away from the first substrate. The first via at least penetrates the first insulating layer and at least exposes part of the first signal line. The semiconductor layer is disposed on a side of the first insulating layer away from the first substrate and includes a semiconductor pattern. The semiconductor pattern includes a first portion, a second portion, and a channel structure between the first portion and the second portion. The first portion has a projection on the first substrate that partially overlaps a projection of the first signal line on the first substrate, and the channel structure has a projection on the first substrate that is within a projection of the first pattern on the first substrate. The connection electrode is disposed on a side of the semiconductor layer away from the first substrate, at least part of the connection electrode is located in the first via, and the connection electrode is connected to the first portion and the first signal line, respectively.

[0004] In some embodiments, the array substrate further comprises a first electrode disposed on a side of the film layer on which the connection electrode is disposed away from the first substrate, and a projection of the first electrode on the first substrate covers a projection of the first signal line on the first substrate.

[0005] In some embodiments, the first electrode comprises a first extension section, and an extension direction of the first extension section is the same as an extension direction of the first signal line. A projection of the first extension section on the first substrate covers a projection of the first signal line on the first substrate, and a first interval between mutually proximal boundaries of the first extension section and the first signal line in the projections of the first extension section and the first signal line on the first substrate is 2 μm to 5 μm.

[0006] In some embodiments, the semiconductor layer further comprises a second electrode connected to the second portion and disposed integrally with the second portion.

[0007] In some embodiments, a projection of the second electrode on the first substrate has a second interval from a projection of the first pattern on the first substrate and a third interval from a projection of the first signal line on the first substrate.

[0008] In some embodiments, the first insulating layer comprises a first groove portion recessed toward the first substrate, and the first groove portion is at least partially located between the first signal line and the first pattern. The second interval is greater than or equal to 2 μm; and / or, the third interval is greater than or equal to 5 μm.

[0009] In some embodiments, the array substrate further comprises a planar layer between the first conductive layer and the first insulating layer, and a surface of the planar layer away from the first substrate is a planar surface. Projections of the first conductive layer, the second interval, and the third interval on the first substrate are located within a projection of the planar layer on the first substrate. The second interval is greater than or equal to 1 μm; and / or, the third interval is greater than or equal to 3 μm.

[0010] In some embodiments, the first insulating layer comprises a first groove portion recessed toward the first substrate, and at least a portion of the first groove portion is located between the first signal line and the first pattern. The first groove portion comprises two oppositely disposed first side walls. The first portion comprises two first sub-portions covering the two first side walls, and a second sub-portion covering other regions of the first insulating layer, and a thickness of the first sub-portion is less than a thickness of the second sub-portion.

[0011] In some embodiments, the array substrate further comprises a second insulating layer disposed between the semiconductor layer and a film layer where the connection electrode is located. A first sub-portion of the two first sub-portions that is closer to the first signal line is a target sub-portion, the first via penetrates through the second insulating layer and exposes the target sub-portion, the connection electrode covers the target sub-portion, and a dimension of the channel structure in a direction perpendicular to the first substrate is greater than or equal to

[0012] In some embodiments, the array substrate further comprises a second insulating layer disposed between the semiconductor layer and a film layer where the connection electrode is located. A first sub-portion of the two first sub-portions that is closer to the first signal line is a target sub-portion, the first via penetrates through the second insulating layer and exposes the target sub-portion, the connection electrode covers the target sub-portion, and a dimension of the channel structure in a direction perpendicular to the first substrate is greater than or equal to

[0013] In some embodiments, the array substrate further comprises a second insulating layer disposed between the semiconductor layer and a film layer where the connection electrode is located. A first sub-portion of the two first sub-portions that is closer to the first signal line is a target sub-portion, the first via penetrates through the second insulating layer and exposes the target sub-portion, the connection electrode covers the target sub-portion, and a dimension of the channel structure in a direction perpendicular to the first substrate is greater than or equal to

[0014] In some embodiments, in a direction perpendicular to the first substrate, a dimension of the first conductive layer is 0.4 μm to 0.8 μm; and / or, in a cross section perpendicular to the first substrate and perpendicular to an extension direction of an edge of the first conductive layer, a first included angle between a sidewall of the first conductive layer and the first substrate is less than or equal to 50°.

[0015] In some embodiments, the array substrate further comprises a planar layer between the first conductive layer and the first insulating layer, a surface of the planar layer away from the first substrate is a planar surface. The planar layer covers at least the first signal line, the first pattern, and a space between the first signal line and the first pattern. The semiconductor layer further comprises a second electrode connected to and integrally disposed with the second portion, a projection of the second electrode on the first substrate at least partially does not overlap with a projection of the planar layer on the first substrate.

[0016] In some embodiments, in a cross section perpendicular to the first substrate and perpendicular to an extending direction of the sidewall of the planar layer, the sidewall of the planar layer and the first substrate have a second included angle, the second included angle being less than or equal to 50°. And / or, a spacing between a surface of the planar layer away from the first substrate and the first substrate is 0.4 μm to 0.8 μm.

[0017] In some embodiments, the first conductive layer includes a plurality of the first signal lines, the plurality of the first signal lines are arranged at intervals along a first direction and each extends along a second direction. The array substrate further includes a plurality of signal line groups, the plurality of signal line groups are arranged at intervals along the second direction and each extends along the first direction. The plurality of the first signal lines and the plurality of signal line groups cross to form a grid structure, an area where a projection of the signal line group and the first signal line on the first substrate overlaps protrudes to a side away from the first substrate to form a columnar structure. The color film substrate includes a spacer, the spacer is strip-shaped and extends along the first direction, a projection of the spacer on the array substrate does not overlap with the columnar structure in the winding area.

[0018] In some embodiments, the spacer abuts against part of the columnar structure away from the color film substrate.

[0019] In some embodiments, the spacer is equal in distance from the color film substrate away from a side of the color film substrate.

[0020] In some embodiments, the signal line group in the winding area protrudes to the first direction.

[0021] In some embodiments, a size of the spacer along the first direction is greater than a pitch of two adjacent first signal lines.

[0022] In some embodiments, the signal line group and the connecting electrode include the same material and are arranged in the same layer.

[0023] In some embodiments, the signal line group includes a second signal line, a projection of the second signal line on the color film substrate overlaps with the spacer. A size of the second signal line in the second direction is C1, a size of an end of the spacer close to the array substrate in the second direction is C4, C4 is greater than C1.

[0024] In some embodiments, the signal line group includes a second signal line and a third signal line, the orthogonal projection of the spacer on the array substrate covers an area between the second signal line and the third signal line; the orthogonal projection of the spacer on the array substrate partially overlaps the second signal line; the orthogonal projection of the spacer on the array substrate partially overlaps the third signal line.

[0025] In some embodiments, the size of the second signal line in the second direction is C1, the size of the third signal line in the second direction is C2, the interval between the second signal line and the third signal line is C3, and the size of the spacer near the end of the array substrate in the second direction is C4. C1, C2, C3 and C4 satisfy: C2>C1, C4=C3+C1; or, C1, C2, C3 and C4 satisfy: C1>C2, C4=C3+C2.

[0026] In some embodiments, at least one of the second signal line and / or at least one of the third signal line crosses the first signal line at a position provided with the winding area.

[0027] In some embodiments, the array substrate includes a first electrode, and the third signal line is connected to the first electrode on one side of the protrusion of the winding area in the first direction.

[0028] In some embodiments, the orthogonal projection of one of the spacers on the array substrate overlaps at least thirteen of the first signal lines and one of the signal line groups, and at least eleven of the crossing positions of the at least thirteen first signal lines and the one signal line group are provided with the winding area.

[0029] In some embodiments, a plurality of the first signal lines and a plurality of the signal line groups form a grid structure defining a plurality of pixel areas; at least one of the spacers is provided in every twenty-four pixel areas.

[0030] In some embodiments, the orthogonal projection of the spacer on the array substrate partially overlaps the signal line group or the first signal line. The spacer includes a main spacer area having a first thickness and a secondary spacer area having a second thickness, the first thickness being greater than the second thickness; the orthogonal projection of the main spacer area on the array substrate overlaps the first signal line, and the orthogonal projection of the main spacer area on the array substrate does not overlap the signal line group.

[0031] In some embodiments, the orthogonal projection of the main spacer area on the array substrate overlaps at least two of the first signal lines.

[0032] In some embodiments, the color filter substrate further includes a black matrix; a projection of the black matrix on the array substrate covers the spacers, the first signal lines, and the signal line groups.

[0033] In some embodiments, the black matrix includes a first portion, a projection of the first portion on the array substrate covers the semiconductor patterns, the first patterns, and regions where the signal line groups and the first signal lines overlap; the first portion and the spacers are close to each other in a projection of the array substrate on a surface of the array substrate, and a fourth interval between borders close to each other is 20 μm to 40 μm.

[0034] In some embodiments, the black matrix further includes a second portion, a projection of the second portion on the array substrate covers regions in the signal line groups that are staggered with the first patterns and the semiconductor patterns in the second direction, and portions of the black matrix that cover the same signal line group include the first portion and the second portion staggered in the first direction; the second portion and the signal line groups are close to each other in a projection of the array substrate on a surface of the array substrate, and a fifth interval between borders close to each other is 3 μm to 6 μm.

[0035] In some embodiments, the first insulating layer includes a first groove portion recessed toward a direction close to the first substrate, and at least a portion of the first groove portion is located between the first signal lines and the first patterns. The black matrix further includes a third portion, a projection of the third portion on the array substrate covers the first signal lines, and the third portion and the first signal lines are close to each other in a projection of the first substrate on a surface of the first substrate, and a sixth interval between borders close to each other is 0.5 μm to 2 μm.

[0036] In some embodiments, the display substrate has a transmittance greater than or equal to 6%.

[0037] In some embodiments, the array substrate further includes a planar layer between the first conductive layer and the first insulating layer, and a surface of the planar layer away from the first substrate is a planar surface. The planar layer includes a first planar portion covering the first signal lines. The black matrix includes a third portion, a projection of the third portion on the array substrate covers the first planar portion, and the third portion and the first planar portion are close to each other in a projection of the first substrate on a surface of the first substrate, and a seventh interval between borders close to each other is 0.5 μm to 2 μm.

[0038] In some embodiments, the display substrate has a transmittance greater than or equal to 9%.

[0039] On the other hand, a display device is provided. The display device includes a display substrate as described in any of the above embodiments. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0041] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0042] Figure 2 This is a structural diagram of a display substrate according to some embodiments;

[0043] Figure 3 This is a planar structural diagram of an array substrate according to some embodiments;

[0044] Figure 4 for Figure 3 A magnified view of a portion of region A1 in the middle;

[0045] Figure 5 For along Figure 4 Cross-sectional view along section line B1-B1;

[0046] Figure 6 This is a planar structural diagram of a pixel region according to some embodiments;

[0047] Figure 7 This is another planar structure diagram of an array substrate according to some embodiments;

[0048] Figure 8 for Figure 7 A magnified view of a portion of region A2 in the middle;

[0049] Figure 9 For along Figure 8 Cross-sectional view along section line B2-B2;

[0050] Figure 10 shows the route along Figure 3 Cross-sectional view along section line B3-B3;

[0051] Figures 11 and 12 are process diagrams for fabricating an array substrate according to some embodiments;

[0052] Figure 13 is a partial enlarged view of a thin-film transistor according to some embodiments;

[0053] Figure 14 is another partially enlarged view of a thin-film transistor according to some embodiments;

[0054] Figure 15 is a cross-sectional view along section line B4-B4 in Figure 14;

[0055] Figure 16 is another partially enlarged view of a thin-film transistor according to some embodiments;

[0056] Figure 17 is a cross-sectional view along section line B5-B5 in Figure 16;

[0057] Figure 18 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0058] Figure 19 is another cross-sectional view of the array substrate according to some embodiments;

[0059] Figure 20A is yet another partially enlarged view of a thin-film transistor according to some embodiments;

[0060] Figure 20B is another partially enlarged view of a thin-film transistor according to some embodiments;

[0061] Figure 21 shows the route along Figure 3 Cross-sectional view along section line B6-B6;

[0062] Figure 22 shows the route along Figure 7 Cross-sectional view along section line B7-B7;

[0063] Figure 23 is a partial top view of a display substrate according to some embodiments;

[0064] Figure 24 is a cross-sectional view along section line B8-B8 in Figure 23;

[0065] Figure 25 is a partial structural diagram of a display substrate under pressure according to some embodiments;

[0066] Figure 26 is a top view of another partial structure of a display substrate according to some embodiments;

[0067] Figure 27 is an equivalent circuit diagram of an array substrate according to some embodiments;

[0068] Figure 28 is a graph showing the thickness of the liquid crystal cell after being subjected to external force when the spacer is not displaced, according to some embodiments;

[0069] Figure 29 is a graph showing the thickness of the liquid crystal cell after the spacer has been displaced and subjected to external force according to some embodiments;

[0070] Figure 30 is a graph showing the deformation data of the septum after displacement and external force according to some embodiments;

[0071] Figure 31 is a partial top view of a display substrate according to some embodiments;

[0072] FIG. 32 is a cross-sectional view along section line B9-B9 in FIG. 31;

[0073] FIG. 33 is another equivalent circuit diagram of an array substrate according to some embodiments;

[0074] FIG. 34 is yet another partial structure top view of a display substrate according to some embodiments;

[0075] FIG. 35 is a cross-sectional view along section line B10-B10 in FIG. 34;

[0076] FIG. 36 is a cross-sectional view along section line C1-C1 in FIG. 26;

[0077] FIG. 37 is a cross-sectional view along section line C2-C2 in FIG. 26;

[0078] FIG. 38 is a cross-sectional view along section line C3-C3 in FIG. 26;

[0079] FIG. 39 is another cross-sectional view along section line C3-C3 in FIG. 26. DETAILED DESCRIPTION

[0080] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0081] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, and other forms thereof, are to be construed as open-ended, meaning “including, but not limited to”, in the entire description and claims. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” etc. are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0082] In the present disclosure, terms such as "lower", "below", "upper" and "above" and the like are used to explain the relative positional association of components shown in the drawings. The terms can be relative concepts and described based on the direction represented in the drawings, or can be described based on the order of formation of process steps, but are not limited thereto.

[0083] The term "relative" means that a first element can be directly or indirectly opposite to a second element. In the case where a third element is interposed between the first element and the second element, although still opposite to each other, the first element and the second element can be understood as indirectly opposite to each other.

[0084] Hereinafter, the terms "first", "second" are used only for descriptive purposes and cannot be understood to indicate or imply relative importance or implicitly indicate the number of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise stated.

[0085] In describing some embodiments, "coupled" and "connected", and the derivatives thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0086] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0087] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0088] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

[0089] In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0090] As used herein, "about," "approximately," or "around" includes the value recited and the average value within an acceptable range of deviation for the particular value being discussed, as determined by one of ordinary skill in the art considering what is being measured and the error inherent in the measuring system (i.e., the limitations of the measurement system).

[0091] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering what is being measured and the error inherent in the measuring system (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable deviation of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable deviation of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable deviation of, for example, less than or equal to 5% of either of the two being equal.

[0092] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0093] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the individual parts of the devices are shown in the figures nor is every instance of a given part of the devices shown. Thus, the drawings represent a simplified view of the implementations. As such, the embodiments are not intended to be limited to the illustrated examples. In addition, the drawings are not necessarily drawn to scale.

[0094] Referring to Figure 1 Embodiments of the present disclosure provide a display device. The display device 1000 is a product having an image display function. The display device 1000 can be exemplarily any device that displays images whether moving (e.g., video) or fixed (e.g., still image) and whether text or image.

[0095] Exemplarily, the display device 1000 can be any product or component with display function, such as a television, a notebook computer, a tablet computer, a personal digital assistant (PDA), a mobile phone, a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a mixed reality (MR) device, a vehicle display, a flight display, etc.

[0096] In some embodiments, the display device 1000 can be a liquid crystal display (LCD) in terms of the light-emitting type of the display device 1000. The display device 1000 can be a flat display device or a curved display device, etc. in terms of the driving type of the display device, the form of the display device 1000. The display device 1000 can be rectangular or circular, etc. in terms of the shape of the display device 1000. In the following, some embodiments of the present disclosure are schematically described by taking a liquid crystal display device with a rectangular shape and a flat surface as an example, but the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0097] In some embodiments, referring to Figure 2 , the display device 1000 includes a display substrate 1100 (which can also be referred to as a display panel) and a driving circuit board (not shown in the figure). The driving circuit board can include, for example, a timing controller (TCON), a power management chip (DC / DC), an adjustable resistance voltage dividing circuit (generating Vcom), and other driving circuits, and the driving circuit board can also include other circuit structures, which are not listed one by one here. The driving circuit board is electrically connected to the display substrate 1100, and is used to transmit control signals to the display substrate 1100, so as to drive the display substrate 1100 to realize image display. In addition, the display device 1000 can also include touch structures, under-screen cameras, under-screen fingerprint recognition sensors, etc., so that the display device 1000 can realize various functions such as touch, shooting, video recording, or fingerprint recognition, which are not listed one by one here.

[0098] Continuing to refer to Figure 2In a case where the display device 1000 is a liquid crystal display device, the display device 1000 can further include a backlight 1200 disposed on a backlight side of the display substrate 1100. The backlight 1200 can be, for example, a direct backlight or an edge backlight, and is configured to provide a light source for the display substrate 1100, which includes a plurality of sub-pixels each configured to adjust an amount of light passing through the display substrate 1100, and thus display the same or different gray scales to achieve an image display purpose.

[0099] With continued reference to Figure 2 In a case where the display substrate 1100 is a liquid crystal display substrate, the display substrate 1100 can include an array substrate 100 and a color filter substrate 200 disposed opposite to each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 can also be referred to as a counter substrate or an encapsulation substrate. Of course, the structure of the display substrate 1100 is not limited to this, and the display substrate 1100 can also include other structures as long as the same technical idea is adopted. For example, the display substrate 1100 can also include a first alignment film (not shown in the figure) disposed on a side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on a side of the color filter substrate 200 close to the liquid crystal layer 300, and the like.

[0100] The array substrate 100 can be of an Advanced Super Dimension Switch (ADS) type or a High-Advanced Dimension Switch (HADS) type with a high aperture ratio. The ADS technology is configured to form a multi-dimensional electric field by an electric field generated by a slit electrode edge in the same plane and an electric field generated between the slit electrode layer and the plate-shaped electrode layer, so that all the liquid crystal molecules between the slit electrodes and directly above the electrodes in the liquid crystal cell can rotate, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency, and having advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low color difference, no push Mura, and the like. In addition, the array substrate 100 can include a display area and a peripheral area disposed around the display area. The display area can include a plurality of pixel circuits, pixel electrodes, and first electrodes, and the peripheral area can include, for example, a Gate Driver On Array (GOA).

[0101] The color film substrate 200 can include a filter portion and a black matrix. The filter portion is configured to filter light rays entering the color film substrate 200, so that each sub-pixel emits light rays of one color (such as red, green, or blue). Different sub-pixels can emit light rays of the same or different colors, so that the display substrate 1100 can realize color display. The black matrix is configured to cover the transistors and signal lines on the array substrate, so as to improve the contrast of the display substrate.

[0102] In the liquid crystal display device, the transmittance of the display substrate 1100 is an important indicator. Improving the transmittance of the display substrate 1100 can not only improve the brightness of the display device, but also reduce the power consumption of the backlight source 1200 of the display device and the overall power consumption of the display device. The conventional ADS liquid crystal display substrate includes a plurality of signal lines on the array substrate and a black matrix on the color film substrate. The orthographic projection of the black matrix on the array substrate covers the plurality of signal lines, so as to reduce the light leakage problem of the signal lines and the peripheral region of the signal lines. However, due to the size of the black matrix in the color film substrate, the transmittance of the display substrate is low.

[0103] Figure 3 FIG. 6 is a partial structural view of a display area of the array substrate without a planarization layer. Figure 4 FIG. 7 is a partial structural view of a region where a thin film transistor of the array substrate is located. Figure 5 FIG. 8 is a cross-sectional view of the thin film transistor of the array substrate without a planarization layer.

[0104] Referring to Figure 3 , Figure 4 and Figure 5 , in order to improve the transmittance of the display substrate, some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a first substrate 110, a first conductive layer SD, a first insulating layer BUF, a semiconductor layer ACT, and a connection electrode 20 arranged in sequence in a direction away from the first substrate 110. In addition, the array substrate 100 further includes a first via V1 penetrating through the first insulating layer BUF.

[0105] Exemplarily, the first substrate 110 can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc. The first substrate 110 can also be a flexible substrate. For example, the flexible substrate can be, for example, a PET (Polyethylene terephthalate) substrate, a PI (Polyimide) substrate, or a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, etc. Exemplarily, the first substrate 110 can be a transparent substrate, so that the light emitted by the backlight source can pass through the first substrate 110, which is conducive to improving the transmittance of the array substrate 100.

[0106] The first conductive layer SD is disposed on one side of the first substrate 110 and includes the first signal lines DL and the first patterns LS distributed at intervals. In the embodiments of the present disclosure, the first signal lines DL and the first patterns LS are formed of the same material and disposed in the same layer, and exemplarily, the first patterns LS and the first signal lines DL are formed in the same patterning process using the same mask plate and / or the same material.

[0107] The first signal lines DL and the first patterns LS are both disposed on the side of the semiconductor layer ACT close to the first substrate 110. On the one hand, this is conducive to reducing the parasitic capacitance between the first signal lines DL and other structures (such as the first electrode 21 and the second electrode 22), thereby improving the pixel density and refresh rate of the array substrate 100, and reducing the power consumption of the first signal lines DL and the overall power consumption of the array substrate 100. On the other hand, this is conducive to increasing the distance between the first signal lines DL and the liquid crystal layer. It can also reduce the influence of the electric field generated by the first signal lines DL on the liquid crystal molecules of the liquid crystal layer, reduce the area of the light leakage area caused by the first signal lines DL, and is conducive to reducing the size of the black matrix used to shield the first signal lines DL, thereby improving the aperture ratio of the display substrate and improving the transmittance of the display substrate.

[0108] Exemplarily, a first signal line DL is disposed on the first substrate 110, and the first signal line DL can be a data signal line configured to transmit a data signal. Of course, in other examples, the first signal line DL can also be used to transmit other signals, as long as the same technical concept is adopted. The first pattern LS can be a light-shielding pattern, which can be configured to block the channel structure 13 of the semiconductor layer ACT to reduce the light incident on the channel structure 13 and reduce the risk of thin film transistor drift under backlight illumination. Exemplarily, the orthographic projection of the first pattern LS on the first substrate 110 coincides at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) with the orthographic projection of the channel structure 13 on the first substrate 110.

[0109] In some embodiments, the material of the first conductive layer SD may include a conductive material, which may include a metallic material, such as one or more of titanium, aluminum, copper, molybdenum, niobium, nickel and their alloys, or the first conductive layer SD may also be a metallic stacked structure. For example, the first conductive layer SD may include one or a combination of the following structures: titanium-aluminum-titanium (Ti / Al / Ti), molybdenum-aluminum (Mo / Al), molybdenum-aluminum-molybdenum (Mo / Al / Mo), molybdenum-niobium-titanium (MoNb / Ti), molybdenum-niobium-titanium-copper (MoNb / Ti / Cu), molybdenum-niobium-copper (MoNb / Cu), molybdenum-nickel-titanium-copper (MTD / Cu), molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD), molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD), molybdenum-neodymium-copper, MoNb-copper-MoNb, and AlNb-molybdenum-AlNd. Of course, the embodiments of this disclosure are not limited to these, and the first conductive layer SD may also consider any other suitable metal or metal stack structure. Furthermore, the thickness of the first conductive layer SD can be... (angstrom; )~ For example, the thickness of the first conductive layer SD can be or Examples of these embodiments will not be listed individually in this disclosure.

[0110] The first insulating layer BUF is disposed on the side of the first conductive layer SD away from the first substrate 110. The first insulating layer BUF may include an insulating material. The first insulating layer BUF may be used to cover at least a portion of the first signal line DL to prevent the first signal line DL from short-circuiting with a conductive structure (such as the second signal line 32) disposed on the upper side of the first signal line DL.

[0111] Exemplarily, the material of the first insulating layer BUF can include a silicon oxide compound (SiOx, x>0), in some embodiments, x can be 1 or 2. The material of the first insulating layer BUF can also include a silicon nitride compound (SiNy, y>0), in some embodiments, y can be 1-2, such as SiN and SiN1.33. The first insulating layer BUF can be a single layer or a stacked structure, in some embodiments, the first insulating layer BUF is a stacked structure including a silicon oxide compound and a silicon nitride compound. In addition, the thickness of the first insulating layer BUF can be 100-700 nm, exemplarily, the thickness of the first insulating layer BUF can be 100 nm, 300 nm, 550 nm, or 700 nm, etc., and the embodiments of the present disclosure will not list them one by one.

[0112] The first via V1 at least penetrates the first insulating layer BUF and at least exposes at least part of the first signal line DL, so as to connect the first signal line DL with the semiconductor layer ACT (the first part 11). The first part 11 is configured to be connected with the first signal line DL through the first via V1, so that the first signal line DL can transmit a data signal to the first part 11.

[0113] The semiconductor layer ACT is located on the side of the first insulating layer BUF away from the first substrate 110. The semiconductor layer ACT includes a plurality of semiconductor patterns 10, one semiconductor pattern 10 is configured to form one thin film transistor (TFT), that is, one thin film transistor can include one semiconductor pattern 10, Figure 4 and Figure 5 Exemplarily, one thin film transistor and one semiconductor pattern 10 are shown in FIGS. 1-3. The semiconductor pattern 10 can include a first part 11, a second part 12, and a channel structure 13 located between the first part 11 and the second part 12. The channel structure 13 is configured to form a channel structure of the TFT, one of the first part 11 and the second part 12 is configured to form a source electrode (or a source electrode connection area) of the TFT, and the other is configured to form a drain electrode (or a drain electrode connection area) of the TFT.

[0114] In some embodiments, the orthogonal projection of the first part 11 on the first substrate 110 partially overlaps with the orthogonal projection of the first signal line DL on the first substrate 110, so that the difficulty of the connecting electrode 20 climbing on the sidewall of the first via V1 can be reduced in the process of preparing the array substrate 100 (see below), the continuity of the connecting electrode 20 in the first via V1 is improved, and the connection stability between the first part 11 and the first signal line DL is ensured.

[0115] The orthographic projection of the channel structure 13 on the first substrate 110 is within the orthographic projection of the first pattern LS on the first substrate 110, based on which the first pattern LS can greatly shield the light from the backlight source to the channel structure 13, reducing the risk of threshold voltage drift of the channel structure 13 under light conditions.

[0116] Exemplarily, as shown in FIG. 1, the orthographic projection of the first pattern LS on the first substrate 110 completely covers the orthographic projection of the channel structure 13 on the first substrate 110, and at least part of the boundary of the orthographic projection of the first pattern LS on the first substrate 110 (e.g., the whole boundary of the first pattern LS) does not coincide with the boundary of the orthographic projection of the channel structure 13 on the first substrate 110, that is, the area of the first pattern LS is greater than the area of the channel structure 13, so that the first pattern LS can shield as many light rays as possible to the channel structure 13. Figure 4 Figure 4 Exemplarily, as shown in FIG. 1, the orthographic projection of the first pattern LS on the first substrate 110 completely covers the orthographic projection of the channel structure 13 on the first substrate 110, and at least part of the boundary of the orthographic projection of the first pattern LS on the first substrate 110 (e.g., the whole boundary of the first pattern LS) does not coincide with the boundary of the orthographic projection of the channel structure 13 on the first substrate 110, that is, the area of the first pattern LS is greater than the area of the channel structure 13, so that the first pattern LS can shield as many light rays as possible to the channel structure 13.

[0117] In some embodiments, the semiconductor layer ACT comprises a metal oxide material with a Hall mobility of 10-30 cm 2 / V.s. In some embodiments, the semiconductor layer ACT comprises a metal oxide material with a Hall mobility greater than or equal to 30 cm 2 / V.s.

[0118] Exemplarily, the semiconductor layer ACT can be manufactured by using various appropriate semiconductor materials and various appropriate manufacturing methods, or in other words, the material of the semiconductor layer ACT can comprise at least one of various appropriate semiconductor materials. In some embodiments, the semiconductor material comprises M1OaNb, wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents an oxygen element, and N represents a nitrogen element, that is, the semiconductor material is a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), In-free OS, rare earth doped oxide (Ln-OS, e.g., rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the semiconductor layer ACT can be in an amorphous, partially crystalline, single crystalline, or polycrystalline state, and can be a single layer or a multi-layer structure.

[0119] ​Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material of the semiconductor layer ACT includes indium gallium zinc oxide (IGZO).

[0120] In some embodiments, the first part 11, the second part 12, and the channel structure 13 are an integral structure, and the materials of the channel structure 13, the first part 11, and the second part 12 all include M1OaNb. The first part 11 and the second part 12 differ from the channel structure 13 in that the first part 11 and the second part 12 undergo a process to make them more conductive (conducting process). The conductivity of the channel structure 13 is different from the conductivity of the first part 11 and also different from the conductivity of the second part 12.

[0121] For example, the channel structure 13 may include a semiconductor material, and the second portion 12 and the first portion 11 may include doped semiconductor materials. In this way, the second portion 12 and the first portion 11 can form conductors, and the channel structure 13 can form a semiconductor.

[0122] In one example, when the materials of channel structure 13, first portion 11, and second portion 12 all include M1OaNb, the M1OaNb in first portion 11 and second portion 12 undergoes a light doping process (e.g., a light doping ion implantation process). In another example, when the materials of channel structure 13, first portion 11, and second portion 12 include M1OaNb, the M1OaNb in first portion 11 and second portion 12 undergoes an annealing process. In yet another example, when the materials of channel structure 13, first portion 11, or second portion 12 include M1OaNb, the M1OaNb in first portion 11 or second portion 12 undergoes an oxide-supplemented process. Exemplarily, materials of approximately 1 × 10⁻⁶ M1OaNb can be used. 15 atoms / cm 3 To approximately 1×10 20 atoms / cm 3 Within a certain range, the doping concentration can be, for example, approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 16 atoms / cm 3 Approximately 1×10 16 atoms / cm 3 To approximately 1×10 17 atoms / cm 3 Approximately 1×10 17 atoms / cm 3 To approximately 1×10 18 atoms / cm 3 Approximately 1×10 18 atoms / cm3 about 1 x 1011atoms / cm2 20 about 1 x 1011atoms / cm2 3 about 1 x 1011atoms / cm2 19 about 1 x 1011atoms / cm2 3 about 1 x 1011atoms / cm2 20 about 1 x 1011atoms / cm2 3 about 1 x 1011atoms / cm2The light doping process is illustratively performed using an N-type dopant to enhance conductivity. Examples of N-type dopants can include Group VA elements of the Periodic Table, including but not limited to nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). The light doping process can also be performed using a shielding gas element, such as argon (Ar), helium (He), oxygen (O), hydrogen (H), fluorine (F).

[0123] Figure 6 FIG. 10 is a structural diagram of the array substrate 100 after removing the first electrode 21 on the basis of FIG. 9. Figure 3

[0124] In some embodiments, referring to FIGS. 1, 2, and 3, the semiconductor layer ACT further includes a second electrode 22, which is connected to the second portion 12 and is integrally arranged with the second portion 12. The second electrode 22 is arranged in the same layer as the semiconductor pattern 10, which is advantageous for simplifying the manufacturing process of the array substrate 100 (the number of masks of the array substrate 100 can be reduced to 6 masks), reducing the thickness and manufacturing cost of the array substrate 100, and improving the light transmittance of the array substrate. Figure 5 Figure 6 Illustratively, the second electrode 22 can be a pixel electrode of the array substrate 100, and one second electrode 22 is electrically connected to one thin film transistor (the second portion 12 of the semiconductor pattern 10) and is configured to receive a data signal transmitted by the first signal line DL.

[0125] Illustratively, the second electrode 22 can be prepared from the same material as the first portion 11 and the second portion 12 in the same layer. In order to improve the conductivity of the second electrode 22, the second electrode 22 can adopt the same conductorization process as the first portion 11 and the second portion 12, so that the conductivity of the second electrode 22 is comparable to that of the first portion 11 and the second portion 12, and is greater than that of the channel structure 13. The conductorization process that can be selected by the second electrode 22 can refer to the conductorization process that can be adopted by the first portion 11 and the second portion 12, which will not be described herein again.

[0126] Illustratively, the second electrode 22 can be prepared from the same material as the first portion 11 and the second portion 12 in the same layer. In order to improve the conductivity of the second electrode 22, the second electrode 22 can adopt the same conductorization process as the first portion 11 and the second portion 12, so that the conductivity of the second electrode 22 is comparable to that of the first portion 11 and the second portion 12, and is greater than that of the channel structure 13. The conductorization process that can be selected by the second electrode 22 can refer to the conductorization process that can be adopted by the first portion 11 and the second portion 12, which will not be described herein again.

[0127] ​Furthermore, to improve the transmittance of the array substrate 100, the second electrode 22 can also be formed using a transparent conductive material. A transparent conductive material is a conductive material with a light transmittance greater than a first threshold value. This first threshold value can be, for example, 80%, 85%, 90%, 95%, or other suitable values, which will not be listed here. In other words, the material of the semiconductor layer ACT is a transparent semiconductor material, which includes one or more of the semiconductor materials described above, and will not be elaborated further here.

[0128] In some embodiments, see Figure 6 The dimension L1 of the second electrode 22 along the first direction X is less than or equal to 1000 μm, and / or the dimension L2 of the second electrode 22 along the second direction Y is less than or equal to 1000 μm. This is beneficial to improving the uniformity of the conductor treatment of the second electrode 22 during the conductor formation process. In other words, it can make the conductivity of the second electrode 22 approximately the same at all points, and it is beneficial to improve the conductivity of the second electrode 22.

[0129] For example, the dimension L1 of the second electrode 22 along the first direction X can be 300μm, 600μm, 750μm, 900μm, or 1000μm, etc.; the dimension L2 of the second electrode 22 along the second direction Y can be 400μm, 600μm, 800μm, 950μm, or 1000μm, etc., and the embodiments of this disclosure will not be listed one by one. The dimension L1 of the second electrode 22 along the first direction X and the dimension L2 along the second direction Y can be equal, or they can be unequal. For example, if the dimension L2 of the second electrode 22 along the second direction Y is greater than the dimension L1 of the second electrode 22 along the first direction X, then the second electrode 22 can form a generally rectangular structure.

[0130] In some embodiments, the first insulating layer BUF is an inorganic insulating layer, typically formed using a thin-film deposition process, see reference. Figure 5 The first insulating layer BUF can be directly disposed on the first conductive layer SD, for example, the first insulating layer BUF is in direct contact with the first conductive layer SD. In this case, the first insulating layer BUF includes a recessed portion in the direction close to the first substrate 110. Figure 5 A first groove 41 (concave from top to bottom) is formed, with at least a portion of the first groove 41 located between the first signal line DL and the first pattern LS. In other words, the surface of the first insulating layer BUF has an undulating morphology adapted to the morphology of the surface of the first conductive layer SD away from the first substrate 110. This simplifies the fabrication process of the array substrate 100, reducing its fabrication difficulty and cost.

[0131] Figure 7A partial structure diagram of the display area of the array substrate including the planar layer; Figure 8 A partial enlarged view of the thin film transistor position of the array substrate including the planar layer; Figure 9 A cross-sectional structure diagram of the thin film transistor of the array substrate including the planar layer.

[0132] In other embodiments, referring to Figure 7 , Figure 8 and Figure 9 , the array substrate 100 further includes a planar layer SOG between the first conductive layer SD and the first insulating layer BUF, and the planar layer SOG is a planar surface away from the surface of the first substrate 110. Exemplarily, the orthographic projection of the planar layer SOG on the first substrate 110 at least covers the orthographic projection of the first conductive layer SD on the first substrate 110, i.e., the planar layer SOG at least covers the first signal line DL and the first pattern LS, which is conducive to improving the planarity of the position of the first insulating layer BUF covering the first conductive layer SD, and further improving the planarity of the position of the semiconductor layer ACT overlapping the first conductive layer SD, reducing the risk of uneven thickness or even local fracture of the semiconductor layer ACT due to the height difference of the surface where the semiconductor layer ACT is located, and improving the performance of the semiconductor layer ACT.

[0133] Exemplarily, the planar layer SOG can fill the gap between the first signal line DL and the first pattern LS, so that the first insulating layer BUF is partially between the first signal line DL and the first pattern LS and is planar away from the surface of the first substrate 110, which is conducive to reducing the phenomenon of uneven thickness of the first part 11 in the area between the first signal line DL and the first pattern LS, improving the uniformity of the thickness of the first part 11, and further improving the connection reliability between the first part 11 and the first signal line DL.

[0134] Exemplarily, the planar layer SOG can be an organic insulating layer, for example, the material of the planar layer SOG can be a Silicon On Glass (SOG) material.

[0135] Referring to Figure 5 and Figure 9 , the array substrate 100 further includes a second insulating layer GI. The second insulating layer GI is located on the side of the semiconductor layer ACT away from the first insulating layer BUF. Exemplarily, the second insulating layer GI is located between the semiconductor layer ACT and the connecting electrode 20.

[0136] The material of the second insulating layer GI can include an insulating material, which can be silicon oxide, for example. Of course, the second insulating layer GI is not limited thereto, and any other suitable material can also be used. The second insulating layer GI can be a single layer or a multi-layer structure. In addition, the thickness of the second insulating layer GI can be Exemplarily, the thickness of the second insulating layer GI can be 10-100nm. or and the like, the embodiments of the present disclosure will not list them one by one.

[0137] In some embodiments, referring to Figure 4 and Figure 5 or referring to Figure 8 and Figure 9 , the array substrate 100 further comprises a connecting electrode 20, which is located on the side of the semiconductor layer ACT away from the first substrate 110. At least part of the connecting electrode 20 is located in the first via V1, and the connecting electrode 20 is electrically connected with the first signal line DL and the first part 11 respectively, thereby electrically connecting the first signal line DL and the first part 11. That is, the first part 11 is configured to be electrically connected with the first signal line DL through the connecting electrode 20, and the first part 11 is indirectly electrically connected with the first signal line DL through the connecting electrode 20.

[0138] In some embodiments, referring to Figure 7 , the array substrate 100 further comprises a plurality of signal line groups 30, which are spaced apart along the second direction Y and each extend along the first direction X. The plurality of first signal lines DL and the plurality of signal line groups 30 cross each other to form a grid structure, and each grid structure defines a pixel region 101.

[0139] The pixel region 101 can be a red pixel region, a green pixel region or a blue pixel region. Each pixel region 101 is controlled by one of the first signal lines DL and one of the signal line groups 30. Exemplarily, the first signal line DL transmits a data signal to the second electrode 22 of the pixel region 101 under the control of the signal line group 30, and an electric field can be generated between the second electrode 22 and the first electrode 21 to drive the liquid crystal molecules of the liquid crystal layer to deflect, and the deflection angle of the liquid crystal molecules can control the polarization direction of the light passing through the pixel region 101, and cooperate with the polarizer to realize different gray scale display.

[0140] wherein, Figure 7The array substrate is only exemplarily shown with two signal line groups 30 and a part of the four first signal lines DL. In the embodiment of the present disclosure, the length direction (extending direction) of the signal line group 30 is the first direction X, and the length direction (extending direction) of the first signal line DL is the second direction Y. The first direction X and the second direction Y intersect with each other, and exemplarily, the first direction X and the second direction Y are perpendicular to each other. The signal line group 30 can extend along the first direction X at the position where the at least one orthographic projection of the signal line group 30 and the first signal line DL overlaps, and a main spacer region for forming a spacer is formed at the projection position. The signal line group 30 can be a broken line at the position where the at least one orthographic projection of the signal line group 30 and the first signal line DL overlaps, and the broken line can form a recess on the signal line group 30, the recess is recessed to a side away from the center of the signal line group 30 along the second direction Y, and is configured to form a sub-spacer region. The specific shape and structure of the signal line group 30 are described below.

[0141] In some embodiments, referring to Figure 4 and Figure 8 , the signal line group 30 at least includes a second signal line 32. Exemplarily, the second signal line 32 is configured to transmit a gate signal to a thin film transistor TFT. The second signal line 32 includes a main body extension 321 extending along the first direction X and a gate portion 322 protruding from the main body extension 321 along the second direction Y to form a gate of the thin film transistor. The main body extension 321 and the gate portion 322 include the same material and are located in the same layer, and exemplarily, the main body extension 321 and the gate portion 322 are in an integral structure, and at this time, the gate portion 322 can be regarded as a branch structure extending outward (perpendicular to the extending direction X of the second signal line 32) of the main body extension 321.

[0142] Referring to Figure 8 and Figure 9 , the size of the gate portion 322 can define the area of the channel structure 13. Exemplarily, the orthographic projection of the channel structure 13 on the first substrate 110 is located within the range of the orthographic projection of the gate portion 322 on the first substrate 110. It can also be said that the part of the semiconductor pattern 10 on the first substrate 110 that overlaps with the orthographic projection of the gate portion 322 on the first substrate 110 is the channel structure 13, the part of the semiconductor pattern 10 located on the side of the channel structure 13 close to the first via V1 is the first part 11, and the part of the semiconductor pattern 10 located on the side of the channel structure 13 away from the first via V1 is the second part 12.

[0143] One thin film transistor can include the gate portion 322, the first portion 11, the second portion 12, and the channel structure 13. One of the first portion 11 and the second portion 12 forms a source connection region of the thin film transistor (e.g., the first portion 11 forms the source connection region), the other forms a drain connection region of the thin film transistor (e.g., the second portion 12 forms the drain connection region), the channel structure 13 forms a channel of the thin film transistor, and the gate portion 322 forms a gate of the thin film transistor. The thin film transistor is turned on or turned off under the control of the gate portion 322, in other words, the channel structure 13 electrically connects between the first portion 11 and the second portion 12 under the control of the gate portion 322 (the thin film transistor is turned on), or the channel structure 13 electrically insulates between the first portion 11 and the second portion 12 under the control of the gate portion 322 (the thin film transistor is turned off).

[0144] In some embodiments, the first pattern LS can also be used to transmit an electrical signal, in which case the first pattern LS can be electrically connected with the second signal line 32, the first pattern LS constitutes a gate of a thin film transistor, and the thin film transistor forms a double-gate structure. Alternatively, in some other embodiments, the first pattern LS can also not be used to transmit an electrical signal, for example, the first pattern LS is electrically insulated from the second signal line 32, in which case the thin film transistor is a top-gate structure including the gate portion 322.

[0145] In some embodiments, referring to Figure 9 , the connecting electrode 20 and the signal line group 30 are formed of the same material and in the same layer, or in other words, the connecting electrode 20 and the second signal line 32 are formed of the same material and in the same layer. For example, the connecting electrode 20 and the signal line group 30 are formed in the same patterning process using the same mask plate and / or using the same material. Compared with preparing the connecting electrode 20 using an additional film layer and process, the connecting electrode 20 and the signal line group 30 being formed of the same material and in the same layer is advantageous in simplifying the manufacturing process of the array substrate 100 and reducing the manufacturing cost of the array substrate 100. Exemplarily, the film layer in which the connecting electrode 20 and the signal line group 30 are located is the gate conductive layer Gate in the embodiments of the present disclosure.

[0146] In some embodiments, referring to Figure 9 , the first portion 11, the channel structure 13, and the second portion 12 are arranged in a substantially straight line direction, that is, the first portion 11, the channel structure 13, and the second portion 12 substantially extend in a linear shape. In this way, it is advantageous to reduce the width (the size along the second direction Y) of the thin film transistor, and thus reduce the area of the black matrix on the color filter substrate, which is advantageous to improve the aperture ratio of the display substrate, and thus improve the transmittance of the display substrate.

[0147] It should be noted that the black matrix on the color filter substrate has a normal projection on the array substrate, which at least covers the thin film transistor. The black matrix can reduce the ambient light incident on the thin film transistor, thereby reducing the reflection of the ambient light by the thin film transistor and improving the display quality of the display substrate.

[0148] In some embodiments, referring to Figure 9 The first portion 11, the channel structure 13 and the second portion 12 extend along the first direction X, that is, the arrangement direction of the first portion 11, the channel structure 13 and the second portion 12 is substantially parallel to the extension direction of the second signal line 32, and the first portion 11, the channel structure 13 and the second portion 12 are arranged close to the second signal line 32. In this way, the space occupied by the thin film transistor and the second signal line 32 in the second direction Y can be greatly reduced, the area of the black matrix on the color filter substrate can be greatly reduced, and the aperture ratio of the display substrate can be improved, thereby improving the transmittance of the display substrate.

[0149] In some embodiments, the material connecting the electrode 20 and the signal line group 30 can include a metal material. For example, the electrode 20 and the signal line group 30 can be a metal stack structure. The metal stack structure can refer to the metal stack structure of the first signal line DL described above, which will not be described again here. The material connecting the electrode 20 and the signal line group 30 can be the same as the material of the first signal line DL, or the material connecting the electrode 20 and the signal line group 30 can be different from the material of the first signal line DL. In addition, the thickness of the electrode 20 and the signal line group 30 can be 200 nm to 1200 nm. For example, the thickness of the electrode 20 and the signal line group 30 can be 200 nm, 500 nm, 950 nm or 1200 nm, and the like. The embodiments of the present disclosure will not list them one by one.

[0150] In some embodiments, referring to Figure 3 and FIG. 10, the array substrate further includes a first electrode 21 disposed on the side of the film layer where the electrode 20 is away from the first substrate 110, and the normal projection of the first electrode 21 on the first substrate 110 covers the normal projection of the first signal line DL on the first substrate 110. Based on this, the first electrode 21 can shield the influence of the electric field generated by the first signal line DL on the liquid crystal layer, reduce the area of the light leakage area of the liquid crystal layer caused by the voltage fluctuation of the first signal line DL, and thereby facilitate reducing the area of the black matrix on the color filter substrate.

[0151] For example, the first electrode 21 can be a common electrode of the array substrate 100. In this way, when the array substrate 100 is working, the first electrode 21 is connected to a constant voltage signal terminal, and the voltage on the first electrode 21 will not be affected by the voltage fluctuation of the first signal line DL, thereby reducing the risk of voltage fluctuation on the first electrode 21.

[0152] In some embodiments, as shown in Figure 3 and Figure 4 The first electrode 21 also covers at least part of the pixel region 101, for example, the first electrode 21 includes a plurality of slit openings 23, so that the first electrode 21 forms a plurality of slit electrodes 24, facilitating the array substrate 100 to form an ADS type array substrate.

[0153] The material of the first electrode 21 may, for example, include a transparent conductive material, including but not limited to at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and IGZO. In addition, the thickness of the first electrode 21 may be 40 nm to 135 nm, for example, the thickness of the first electrode 21 may be 40 nm, 80 nm, 100 nm, or 135 nm, etc., and the embodiments of the present disclosure will not be enumerated one by one.

[0154] In some embodiments, referring to Figure 3 and FIG. 10, the first electrode 21 includes a first extension 24, the extension direction of the first extension 24 is the same as the extension direction of the first signal line DL, the orthographic projection of the first extension 24 on the first substrate 110 covers the orthographic projection of the first signal line DL on the first substrate 110, and the boundary of the orthographic projection of the first extension 24 on the first substrate 110 has a first interval D1 with the boundary of the orthographic projection of the first signal line DL on the first substrate 110, the first interval D1 is 2 μm to 5 μm, so that the coverage effect of the first extension 24 on the first signal line DL can be greatly improved, the shielding effect of the first extension 24 on the electric field of the first signal line DL can be improved, and the influence of the electric field generated by the first signal line DL on the liquid crystal layer can be greatly reduced. It is beneficial to reduce the width of the part of the black matrix on the color film substrate that covers the first signal line DL, and further improve the aperture ratio of the display substrate. For example, the value of the first interval D1 may be 2 μm, 3 μm, 4 μm, 4.5 μm, or 5 μm, etc., and the embodiments of the present disclosure will not be enumerated one by one.

[0155] In some embodiments, referring to Figure 4 and Figure 8 The orthographic projection of the second electrode 22 on the first substrate 110 has a second interval D2 with the orthographic projection of the first pattern LS on the first substrate 110, the second interval D2 is beneficial to reduce the parasitic capacitance between the second electrode 22 and the first pattern LS, and is beneficial to reduce the risk of signal interference between the gate portion 322 and the second electrode 22.

[0156] Continuing to refer to Figure 4 and Figure 8The second electrode 22 has a third interval D3 between the orthographic projection of the second electrode 22 on the first substrate 110 and the orthographic projection of the first signal line DL on the first substrate 110. The third interval D3 is beneficial to increase the interval between the second electrode 22 and the first signal line DL, reduce the risk of short circuit between the second electrode 22 and the first signal line DL, and reduce the size of the parasitic capacitance generated between the second electrode 22 and the first signal line DL, so that the signal crosstalk between the second electrode 22 and the first signal line DL, such as the amplitude of the voltage fluctuation on the second electrode 22 caused by the voltage fluctuation of the first signal line DL, can be reduced.

[0157] In some embodiments, referring to Figure 4 and Figure 5 In the case where the first insulating layer BUF is directly arranged on the first conductive layer SD, that is, the first insulating layer BUF includes the first groove portion 41 recessed in the direction close to the first substrate 110, and the first groove portion 41 is at least partially located between the first signal line DL and the first pattern LS, the relief of the first insulating layer BUF is adjacent to the edge position of the first pattern LS, and at this time, the second interval D2 is greater than or equal to 2 μm, that is, D2≥2 μm; in this way, not only can the risk of signal interference between the gate portion 322 and the second electrode 22 be greatly reduced, but also the risk of residue of the second electrode 22 at the edge position close to the first pattern LS can be reduced, which is beneficial to reduce the development difficulty in the preparation process of the semiconductor layer ACT, and is beneficial to improve the flatness of the second electrode 22 at the edge position close to the first pattern LS (hereinafter referred to as the first region), improve the electric field uniformity of the first region, and reduce the risk of light leakage of the liquid crystal layer in the first region.

[0158] Exemplarily, the range of the second interval D2 can be 2 μm-3 μm, or the range of the second interval D2 can be 3 μm-4 μm, or the range of the second interval D2 can be 4 μm-6 μm, etc. For example, the second interval D2 can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. The embodiments of the present disclosure do not enumerate them one by one.

[0159] It should be understood that, as Figure 5As shown, in the case where the first insulating layer BUF is directly disposed on the first conductive layer SD, the first insulating layer BUF has a relief profile away from the surface of the first substrate 110 at the edge positions of the first pattern LS and the first signal line DL. The preparation process of the semiconductor layer ACT includes: forming a continuous and integral initial semiconductor layer on the surface of the first insulating layer BUF, the initial semiconductor layer also has a relief profile at the edges of the first pattern LS and the first signal line DL, and the distance between the part of the initial semiconductor layer above the first pattern LS and the first substrate 110 is greater than the distance between the part in the pixel area and the first substrate 110. Then the photoresist is coated on the initial semiconductor layer, and the thickness of the photoresist on the part above the first pattern LS is less than the thickness of the photoresist on the part within the pixel area 101. Then the photoresist layer is patterned by an exposure and development process, and in this process, the above-mentioned second interval D2 can avoid forming a thicker photoresist which is difficult to remove by development at the edge positions of the first pattern LS, thereby avoiding the problem of residual first electrode 21 at the edge positions of the first pattern LS.

[0160] Referring to Figure 4 and Figure 5 In the case where the first insulating layer BUF is directly disposed on the first conductive layer SD, that is, the first insulating layer BUF includes a first groove portion 41 recessed in the direction close to the first substrate 110, and the first groove portion 41 is at least partially located between the first signal line DL and the first pattern LS, the relief profile of the first insulating layer BUF is also located at the edge positions of the first signal line DL, and at this time the third interval D3 is greater than or equal to 4 μm, that is, D3≥4 μm; in this way, not only can the risk of short circuit between the second electrode 22 and the first signal line DL be greatly reduced, and the size of the parasitic capacitance generated between the second electrode 22 and the first signal line DL be reduced, but also the risk of residual of the second electrode 22 at the edge positions close to the first signal line DL can be reduced, which is conducive to reducing the development difficulty in the preparation process of the semiconductor layer ACT, and is conducive to improving the flatness of the second electrode 22 at the edge positions close to the first signal line DL (hereinafter referred to as the first area), improving the electric field uniformity of the first area, and reducing the risk of light leakage of the liquid crystal layer in the first area.

[0161] For example, the third interval D3 can be in the range of 4 μm to 5 μm, or the third interval D3 can be in the range of 5 μm to 7 μm, or the third interval D3 can be in the range of 7 μm to 10 μm, etc. For example, the third interval D3 can be 4 μm, 5 μm, 6.5 μm, 7 μm or 8 μm, etc. The embodiments of the present disclosure do not list them one by one.

[0162] In some embodiments, referring to Figure 8 and Figure 9In the case where the array substrate 100 further comprises a planar layer SOG between the first conductive layer SD and the first insulating layer BUF, the planar layer SOG is a planar surface away from the surface of the first substrate 110, and the orthographic projections of the first conductive layer SD, the second interval D2 and the third interval D3 on the first substrate 110 are within the orthographic projection of the planar layer SOG on the first substrate 110, that is, the planar layer SOG covers the first conductive layer SD, the second interval D2 and the third interval D3. At this time, the first insulating layer BUF is on the planar layer SOG within the second interval D2 and the third interval D3. The portion of the first insulating layer BUF within the second interval D2 and the third interval D2 is free of undulating topography away from the surface of the first substrate 110, and the semiconductor layer ACT does not have the problem of thick photoresist development difficulty within the second interval D2 and the third interval D3. Based on this, the second interval D2 is greater than or equal to 1 μm, that is, D2≥1 μm. In the case where the second interval D2 is small, the second electrode 22 is also free of the risk of residue at the edge position close to the first pattern LS, the parasitic capacitance generated between the second electrode 22 and the first pattern LS is reduced, and the area ratio of the second electrode 22 is greatly increased, which is beneficial to improving the pixel density of the array substrate.

[0163] Exemplarily, the range of the second interval D2 can be 1 μm-2 μm, or the range of the second interval D2 can be 2 μm-4 μm, or the range of the second interval D2 can be 4 μm-6 μm, etc. For example, the second interval D2 can be 1 μm, 2 μm, 3 μm, 3.5 μm or 5 μm, etc. Embodiments of the present disclosure will not list them one by one.

[0164] In some embodiments, in the case where the array substrate 100 further comprises a planar layer SOG between the first conductive layer SD and the first insulating layer BUF, continuing to refer to Figure 8 and Figure 9 , the third interval D3 is greater than or equal to 3 μm, that is, D3≥3 μm. In this way, the risk of short circuit between the second electrode 22 and the first signal line DL is reduced, the size of the parasitic capacitance generated between the second electrode 22 and the first signal line DL is reduced, and the area ratio of the second electrode 22 is increased, which is beneficial to improving the pixel density of the array substrate.

[0165] Exemplarily, the range of the third interval D3 can be 3 μm-4 μm, or the range of the third interval D3 can be 4 μm-6 μm, or the range of the third interval D3 can be 6 μm-10 μm, etc. For example, the third interval D3 can be 3 μm, 5 μm, 6 μm, 7.5 μm or 9 μm, etc. Embodiments of the present disclosure will not list them one by one.

[0166] In some embodiments, such as Figure 5 As shown, when the first insulating layer BUF is directly disposed on the first conductive layer SD, the surface of the first insulating layer BUF changes with the undulation of its surface. The first insulating layer BUF includes a first groove 41 recessed inward toward the first substrate 110. At least a portion of the first groove 41 is located between the first signal line DL and the first pattern LS, or in other words, at least a portion of the orthographic projection of the first groove 41 on the first substrate 110 is located between the orthographic projections of the first signal line DL and the first pattern LS on the first substrate 110.

[0167] The first groove 41 includes two opposing first sidewalls 42. In a cross-section perpendicular to the first substrate 110 and parallel to the first signal line DL and the first pattern LS alignment direction (first direction X) (e.g.) Figure 5 (as shown in the cross section), the first sidewall 42 has an acute angle with the first substrate 110, or in other words, the first sidewall 42 is an inclined sidewall.

[0168] Continue reading Figure 5 The first portion 11 of the semiconductor pattern 10 includes two first sub-portions 14 covering two first sidewalls 42, and a second sub-portion 15 covering other areas of the first insulating layer BUF. The thickness of the first sub-portion 14 is less than the thickness of the second sub-portion 15. The semiconductor layer ACT is typically formed using a thin-film deposition process. Because the first sidewalls 42 are inclined sidewalls, the thickness of the semiconductor layer ACT material deposited on the first sidewalls 42 is relatively small. The thicknesses of the first sub-portions 14 and 15 refer to their dimensions along a direction perpendicular to their respective surfaces. For example, the thickness of the first sub-portion 14 refers to its dimension along a direction perpendicular to the first sidewalls 42; the thickness of the second sub-portion 15 refers to its dimension in the Z-direction.

[0169] In some embodiments, in a cross-section perpendicular to the extension direction of the first substrate 110 and perpendicular to the edge of the first conductive layer SD (e.g. Figure 5 In the cross-section shown, the sidewall 16 of the first conductive layer SD has a first included angle α with the first substrate 110, which is less than or equal to 50°. This helps to reduce the tilt of the first sidewall 42, thereby facilitating the deposition of the semiconductor layer ACT on the first sidewall 42. It reduces the risk of breakage of the semiconductor layer ACT on the first sidewall 42 (discontinuous deposition or insufficient film thickness), or in other words, it helps to increase the thickness of the first sub-part 14 on the first sidewall 42, and also helps to reduce the thickness of the portion of the semiconductor layer ACT located on the plane (such as the thickness of the channel structure 13 and the second electrode 22), thereby reducing the fabrication cost of the semiconductor layer ACT and improving the transmittance of the second electrode 22.

[0170] Exemplarily, the first included angle a can range from 40° to 50°, or the first included angle a can range from 30° to 40°. For example, the first included angle a can be 30°, 35°, 40°, 45°, 47° or 50°, and the like, and the embodiments of the present disclosure will not list them one by one.

[0171] In some embodiments, the ratio K of the thickness of the first sub-portion 14 to the thickness of the second sub-portion 15 is greater than or equal to 40%, that is, the thickness retention rate of the semiconductor layer ACT climbing at the first side wall 42 is greater than or equal to 40%. Exemplarily, the ratio K can range from 40% to 50%, or the ratio K can range from 50% to 60%, or the ratio K can range from 60% to 80%. For example, the ratio K of the thickness of the first sub-portion 14 to the thickness of the second sub-portion 15 can be 40%, 45%, 50%, 60% or 70%, and the like, and the embodiments of the present disclosure will not list them one by one. Among them, the ratio K of the thickness of the first sub-portion 14 to the thickness of the second sub-portion 15 is negatively related to the size of the first included angle a, that is, the greater the value of the first included angle a, the smaller the ratio K of the thickness of the first sub-portion 14 to the thickness of the second sub-portion 15.

[0172] In some embodiments, the thickness of the first sub-portion 14 is greater than or equal to In this way, the risk of the first sub-portion 14 being broken can be reduced, and the resistance of the first sub-portion 14 can meet the use requirements. Exemplarily, the thickness of the first sub-portion 14 is Alternatively, the thickness of the first sub-portion 14 is Alternatively, the thickness of the first sub-portion 14 is For example, the thickness of the first sub-portion 14 can be Alternatively and the like, and the embodiments of the present disclosure will not list them one by one.

[0173] In some embodiments, referring to Figure 8 and Figure 9 In the case that the array substrate 100 further includes a planar layer SOG between the first conductive layer SD and the first insulating layer BUF, and the semiconductor layer ACT includes the second electrode 22 layer, the planar layer SOG can only cover the area of the first conductive layer SD, so that the influence of the planar layer SOG on the transmittance of the pixel area 101 can be greatly reduced, which is beneficial to improve the light transmittance of the array substrate.

[0174] Referring to Figure 9 , the first insulating layer BUF will form a relief topography at the edge of the planar layer SOG, for example, the first insulating layer BUF will form a second side wall 43 at the edge position of the planar layer SOG, in the cross section perpendicular to the first substrate 110 and perpendicular to the extension direction of the side wall of the planar layer SOG (such asFigure 9 As shown in the cross section), the second side wall 43 has an acute included angle with the first substrate 110, that is, the second side wall 43 is an inclined side wall.

[0175] In some embodiments, in a cross section perpendicular to the first substrate 110 and perpendicular to the extending direction of the side wall of the planar layer SOG (as shown in the cross section), the side wall of the planar layer SOG has a second included angle β with the first substrate 110, and the second included angle β is less than or equal to 50°. This is advantageous to reduce the inclination of the second side wall 43, to facilitate the deposition of the semiconductor layer ACT on the second side wall 43, to reduce the risk of breaking (discontinuous deposition or film thickness not meeting the requirements) of the semiconductor layer ACT on the second side wall 43, and to reduce the thickness of the semiconductor layer ACT on the planar portion (such as the thickness of the channel structure 13 and the second electrode 22), to reduce the preparation cost of the semiconductor layer ACT, and to improve the transmittance of the second electrode 22. Figure 9 Exemplarily, the second included angle β can range from 40° to 50°, or the second included angle β can range from 30° to 40°. For example, the value of the second included angle β can be 30°, 35°, 40°, 45°, 47° or 50°, and the like. Embodiments of the present disclosure do not list them one by one.

[0176] In some embodiments, taking the array substrate 100 not including the planar layer SOG as an example, referring to FIG. 11 and FIG. 12, the preparation process of the array substrate 100 includes: sequentially preparing and forming the first conductive layer SD, the first insulating layer BUF, the semiconductor layer ACT and the second insulating layer GI on the first substrate 110; then forming the first via V1, part of the first via V1 penetrating through the second insulating layer GI and the first insulating layer BUF, and exposing part of the first signal line DL, part of the first via V1 penetrating through the second insulating layer GI, and exposing part of the first portion 11 (as shown in FIG. 11). Then, an initial gate line layer is prepared and formed in a continuous whole layer, and the initial gate line layer covers the first via V1. Then, the initial gate line layer is patterned to form the connection electrode 20 and the signal line group 30 (as shown in FIG. 12). Wherein, the connection pattern 20 can be located entirely in the first via V1 (as shown in FIG. 12), or partially in the first via V1 and partially covering the surface of the second insulating layer GI (as shown in FIG. 15).

[0177]

[0178] ​In some embodiments, as shown in FIGS. 12 and 13, the first sub-portion 14 of the two first sub-portions 14 close to the first signal line DL is a target sub-portion 14A, the first via V1 penetrates through the second insulating layer GI and exposes the target sub-portion 14A, and the connection electrode 20 covers the target sub-portion 14A. At this time, in the process of forming the first via V1, part of the first sub-portion 14 can be etched and removed, thereby causing the thickness of the first sub-portion 14 to decrease. The size of the channel structure 13 in the direction perpendicular to the first substrate 110 (the third direction Z) is greater than or equal to In this way, the target sub-portion 14A can be guaranteed not to be broken even if it is removed in the process of forming the first via V1, which is conducive to improving the continuity and conductivity of the target sub-portion 14A. Moreover, the first via V1 occupies a smaller area, which is conducive to improving the pixel density of the array substrate 100.

[0179] For example, the size of the channel structure 13 in the third direction Z can be Alternatively, the size of the channel structure 13 in the third direction Z can be Alternatively, the size of the channel structure 13 in the third direction Z can be In this way, the thickness of the channel structure 13 can be reduced as much as possible on the premise of guaranteeing the continuity of the first sub-portion 14, the consumption of the semiconductor layer ACT is reduced, and the thickness of the second electrode 22 is reduced, which is conducive to improving the transmittance of the second electrode 22. For example, the size of the channel structure 13 in the third direction Z can be Alternatively and so on. The embodiments of the present disclosure do not list them one by one.

[0180] It should be noted that in the semiconductor layer ACT, the thickness of the channel structure 13 is the thickness of the deposited semiconductor material in the preparation process of the semiconductor layer ACT. In the process of patterning the second insulating layer GI, the first portion 11, the second portion 12, and the second electrode 22 can be partially removed. Therefore, in some embodiments, the thicknesses of the first portion 11, the second portion 12, and the second electrode 22 are all less than or equal to the thickness of the channel structure 13.

[0181] In other embodiments, as shown in FIGS. 14 and 15, the first sub-portion 14 of the two first sub-portions 14 close to the first signal line DL is a target sub-portion 14A, the first via V1 penetrates through the second insulating layer GI, and the first via V1 has a spacing with the target sub-portion 14A. At this time, in the process of forming the first via V1, the target sub-portion 14A will not be etched, which is conducive to maintaining the thickness of the target sub-portion 14A. The size of the channel structure 13 in the direction perpendicular to the first substrate 110 (the third direction Z) is greater than or equal to In this way, the thickness of the semiconductor layer ACT can be reduced, the material consumption of the semiconductor layer ACT can be reduced, and the thickness of the second electrode 22 can be reduced, thereby improving the transmittance of the second electrode 22.

[0182] It should be noted that after the connection electrode 20 is formed, the preparation method of the array substrate further includes patterning the second insulating layer GI. In the process of patterning the second insulating layer GI, the second insulating layer above the first sub portion 14 can also be etched and removed. In this process, part of the first sub portion 14 can be etched and removed synchronously. The etching degree of the first sub portion 14 in this process is small, and the thickness reduction of the first sub portion 14 is small (for example, less than 10 nm). The size of the channel structure 13 in the direction perpendicular to the first substrate 110 (the third direction Z) is greater than or equal to

[0183] For example, the size of the channel structure 13 in the third direction Z can be Alternatively, the size of the channel structure 13 in the third direction Z can be Alternatively, the size of the channel structure 13 in the third direction Z can be In this way, the thickness of the channel structure 13 can be reduced as much as possible under the premise of ensuring the continuity of the first sub portion 14, the material consumption of the semiconductor layer ACT can be reduced, and the thickness of the second electrode 22 can be reduced, thereby improving the transmittance of the second electrode 22. For example, the size of the channel structure 13 in the third direction Z can be Alternatively and the like. The embodiments of the present disclosure do not list them one by one.

[0184] In some embodiments, referring to FIGS. 16 and 17, the first sub portion 14 close to the first signal line DL among the two first sub portions 14 is a target sub portion 14A, the first via V1 penetrates the second insulating layer GI and exposes the target sub portion 14A, and the connection electrode 20 has a spacing with the target sub portion 14A. At this time, in the process of forming the first via V1, and in the subsequent process of patterning the second insulating layer GI, part of the target sub portion 14A can be etched and removed. The size of the channel structure 13 in the direction perpendicular to the first substrate is greater than or equal to In this way, the risk of the target sub portion 14A being etched and penetrated to break can be greatly reduced.

[0185] For example, the size of the channel structure 13 in the third direction Z can be Alternatively, the size of the channel structure 13 in the third direction Z can be Alternatively, the size of the channel structure 13 in the third direction Z can be For example, the size of the channel structure 13 in the third direction Z can be Or and the like, the embodiments of the present disclosure will not be listed one by one.

[0186] In some embodiments, after the formation of the connection electrode 20, the second insulating layer GI can be subjected to a patterning process, such as Figure 5 、 Figure 9 , as shown in FIGS. 12, 15 and 17, at this time, the second insulating layer GI does not extend substantially over the entire array substrate 100, and the position where the second insulating layer GI is located substantially coincides with the position where the signal line group 30 is located.

[0187] In other embodiments, after the formation of the connection electrode 20, the second insulating layer GI can not be subjected to a patterning process, as shown in FIG. 18, at this time, the second insulating layer GI substantially extends over the entire array substrate 100.

[0188] In some embodiments, as shown in Figure 9 , in the case where the second insulating layer GI does not substantially extend over the entire array substrate 100, the connection electrode 20 can be completely located within the range of the first via V1, at this time, the side of the connection electrode 20 close to the first substrate 110 does not include the second insulating layer GI.

[0189] In some embodiments, as shown in FIGS. 12 and 15, in the case where the second insulating layer GI does not substantially extend over the entire array substrate 100, the connection electrode 20 can be partially located within the range of the first via V1 and partially located outside the range of the first via V1, at this time, the connection electrode 20 and the first insulating layer BUF (as shown in FIG. 12), and / or the connection electrode 20 and the first portion 11 include at least part of the second insulating layer GI (as shown in FIG. 15).

[0190] In some embodiments, as shown in FIG. 15, the connection electrode 20 can expose at least part of the first portion 11, such as the part located on the side of the connection electrode 20 close to the channel structure 13. At this time, the surface of the first portion 11 away from the first substrate 110 includes a second groove portion 17 recessed toward the side close to the first substrate 110. The second groove portion 17 can be formed in the process of forming the connection electrode 20 and patterning the second insulating layer GI.

[0191] In some embodiments, when the second insulating layer GI extends substantially over the entire array substrate 100, referring to FIG. 19, the connection electrode 20 can be entirely within the range of the first via V1, in which case the side of the connection electrode 20 close to the first substrate 110 does not include the second insulating layer GI. Alternatively, referring to FIG. 18, the connection electrode 20 can be partially within the range of the first via V1 and partially outside the first via V1, in which case at least part of the connection electrode 20 is located away from the surface of the first substrate 110.

[0192] It can be understood that the relative positional relationship between the connection electrode 20, the first via V1, the first portion 11, and the first signal line DL is not limited to the above-described embodiments, as long as the same technical idea is adopted.

[0193] Exemplarily, referring to FIG. 20A, the orthographic projection of the first portion 11 and the first signal line DL on the first substrate 110 partially overlaps, the orthographic projection of the first via V1 on the substrate 110 is within the range of the orthographic projection of the first signal line DL on the first substrate 110, the connection electrode 21 entirely covers the first via V1, and the edge of the connection electrode 21 extends beyond the edge of the first via V1. Exemplarily, referring to FIG. 20B, the orthographic projection of the first portion 11 and the first signal line DL on the first substrate 110 partially overlaps, the orthographic projection of the first via V1 on the substrate 110 partially overlaps the first signal line DL and partially overlaps the first pattern LS, the connection electrode 20 covers the edges of the first via V1 on both sides in the first direction X, and is within the range of the first via V1 at both ends in the second direction Y. Of course, embodiments of the present disclosure are not limited thereto, and any other feasible implementation can be considered, and embodiments of the present disclosure will not be exemplified one by one here.

[0194] In some embodiments, referring to FIGS. 21 and 22, the orthographic projection of the signal line group 30 and the first signal line DL on the first substrate 110 overlaps in a region (hereinafter referred to as a main spacer region) 201, and protrudes away from the first substrate 110 to form a columnar structure 50. That is, the surface of the array substrate 100 away from the first substrate 110 protrudes in the direction away from the first substrate 110 (the direction from bottom to top in FIGS. 21 and 22) within the main spacer region 201 to form the columnar structure 50. The columnar structure 50 is configured to support the spacers on the color film substrate.

[0195] In some embodiments, referring to FIG. 21, in the case where the first insulating layer BUF is directly disposed on the first conductive layer SD, the size of the first conductive layer SD in the direction perpendicular to the first substrate 110 (the third direction Z) is 0.4 μm to 0.8 μm. In this way, the height difference (step) between the first signal line DL and the first substrate 110 is increased, and the columnar structure 50 is formed on the main spacer region 201 of the array substrate 100 and on the surface away from the first substrate 110. For example, the size of the first conductive layer SD is 0.4 μm, 0.5 μm, 0.65 μm, 0.7 μm, or 0.8 μm, and the like, and the embodiments of the present disclosure are not limited to this.

[0196] In some embodiments, referring to FIG. 22, in the case where the array substrate 100 further includes a planar layer SOG, the planar layer SOG is located between the first conductive layer SD and the first insulating layer BUF, and the planar layer SOG covers at least the first signal line DL, the first pattern LS, and the interval (the second interval D2) between the first signal line DL and the first pattern LS, the orthographic projection of the second electrode 22 on the first substrate 110 does not at least partially coincide with the orthographic projection of the planar layer SOG on the first substrate 110. On the one hand, the area of the planar layer SOG in the pixel region 101 is reduced, and the transmittance of the pixel region 101 is improved. On the other hand, the height difference between the edge of the planar layer SOG and the first substrate 110 is formed, and the columnar structure 50 is formed on the main spacer region 201 of the array substrate 100 and on the surface away from the first substrate 110. For example, the size of the first conductive layer SD is 0.4 μm, 0.55 μm, 0.6 μm, 0.7 μm, or 0.8 μm, and the like, and the embodiments of the present disclosure are not limited to this.

[0197] As shown in FIG. 22, in the case where the array substrate 100 further includes the planar layer SOG, the thickness of the first conductive layer SD is not limited, which is conducive to reducing the thickness of the first conductive layer SD and reducing the width of the first signal line DL, thereby improving the aperture ratio of the array substrate 100 and improving the transmittance of the array substrate 100.

[0198] In some embodiments, the array substrate 100 further includes an alignment film (not shown in the figure) disposed on the side of the first electrode 21 away from the first substrate 110. The alignment film is used to define an initial bias angle for the liquid crystal molecules of the liquid crystal layer, so that the liquid crystal molecules of the liquid crystal layer can be arranged at a certain angle in the absence of an electric field.

[0199] In the following embodiments, some embodiments of the present disclosure are exemplarily described by taking the case where the first insulating layer BUF is directly disposed on the first conductive layer SD (the array substrate 100 does not include the planar layer SOG) as an example, but the embodiments of the present disclosure are not limited to this.

[0200] In some embodiments, referring to FIGS. 23-26, the array substrate 100 includes a plurality of first signal lines DL spaced apart along the first direction X, and a plurality of signal line groups 30 spaced apart along the second direction Y. The plurality of first signal lines DL each extend along the second direction Y, and the plurality of signal line groups 30 each extend along the first direction X. The plurality of first signal lines DL and the plurality of signal line groups 30 cross each other to form a grid structure.

[0201] The color filter substrate 200 includes a plurality of spacers 230. The plurality of spacers 230 are in the form of strips. Exemplarily, the plurality of strip-shaped spacers 230 are disposed on the side of the color filter substrate 200 close to the array substrate 100, and extend along the first direction X. The orthogonal projection of the spacers 230 on the array substrate 100 partially overlaps the signal line groups 30 and the first signal lines DL.

[0202] The present application utilizes the thickness and length of the signal line groups 30 and the first signal lines DL to cooperate with the long strip-shaped spacers 230 to form a structure for supporting the liquid crystal layer (liquid crystal cell thickness). When the spacers 230 are displaced, the spacers 230 can be supported by the first signal lines DL and the signal line groups 30 to prevent the spacers 230 from scratching the portion of the alignment film in the pixel region 101.

[0203] Referring to FIG. 24, the color filter substrate 200 further includes a second substrate 210 and a filter layer 220. The second substrate 210 can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc. The second substrate 210 can also be a flexible substrate. For example, the flexible substrate can be, for example, a PET (Polyethylene terephthalate) substrate, a PI (Polyimide) substrate, or a PEN (Polyethylene naphthalate two formic acid glycol ester) substrate, etc. It can be understood that the type of the second substrate 210 includes various types, which can be selected and arranged according to actual needs, and the embodiments of the present disclosure do not limit this.

[0204] The second substrate 210 is provided with the filter layer 220 on the side close to the array substrate 100. The filter layer 220 includes a black matrix 60 and filter portions (not shown in the figure). The filter portions are arranged in correspondence with the pixel regions 101. The orthogonal projection of the filter portions on the array substrate 100 covers the pixel regions 101. The filter portions include red filter portions, green filter portions, and blue filter portions. Different pixel regions 101 correspond to different filter portions.

[0205] The orthogonal projection of the black matrix 60 on the array substrate 100 covers the area of the non-pixel region 101. Exemplarily, the orthogonal projection of the black matrix 60 on the array substrate 100 covers the first signal line DL, the signal line group 30, the first pattern LS, etc., and the black matrix 60 also covers the spacer 230 structure on the color film substrate 200. The black matrix 60 is also configured to separate different pixel regions 101 to reduce the risk of crosstalk between different pixel regions, affecting the final display effect. The black matrix 60 can also prevent the spacer 230 from slipping to cause panel display abnormalities and shield scratches. The color film substrate 200 is provided with an alignment film (not shown in the figure) on the side close to the array substrate 100.

[0206] The liquid crystal layer 300 between the array substrate 100 and the color film substrate 200 is supported by the spacers 230. The spacers 230 are supported on the array substrate 100 at one end (lower end surface) close to the array substrate and on the color film substrate 200 at one end (upper end surface) close to the color film substrate 200, thereby maintaining the liquid crystal layer 300 with a certain thickness. Exemplarily, the spacers 230 can be prepared on the color film substrate 200.

[0207] In some embodiments, referring to FIGS. 23-27, the signal line group 30 includes a second signal line 32 and a third signal line 33. The structure and function of the second signal line 32 are described above and will not be repeated here. The third signal line 33 is configured to be connected with the first electrode, and the third signal line 33 is also configured to provide a stable voltage to one end of the liquid crystal capacitor Clc and the storage capacitor Cst, so as to maintain a stable voltage difference between the liquid crystal capacitor Clc and the storage capacitor Cst, and further maintain a directional deflection angle of the liquid crystal molecules.

[0208] Exemplarily, one signal line group 30 includes one second signal line 32 and one third signal line 33. The second signal line 32 controls the on-off between the first signal line DL of one row of pixel regions 101 and the second electrode of the row of pixel regions 101 through one row of thin film transistors, and the third signal line 33 provides a stable voltage to one end of the liquid crystal capacitor Clc and the storage capacitor Cst of the adjacent row of pixel regions 101.

[0209] In some embodiments, referring to FIG. 23, the orthogonal projection of the spacer 230 on the array substrate 100 covers the area between the second signal line 32 and the third signal line 33 in the signal line group 30. The orthogonal projection of the spacer 230 on the array substrate 100 partially overlaps the second signal line 32, and the orthogonal projection of the spacer 230 on the array substrate 100 partially overlaps the third signal line 33. That is, the orthogonal projection of the spacer 230 on the array substrate 100 simultaneously covers part of the second signal line 32, part of the third signal line 33, and the area between the second signal line 32 and the third signal line 33 in the length range of the spacer 230.

[0210] In some embodiments, referring to FIG. 23, the size of the second signal line 32 in the second direction Y is C1, the size of the third signal line 33 in the second direction Y is C2, the interval between the second signal line 32 and the third signal line 33 is C3, and the size of the spacer 230 near the end of the array substrate 100 in the second direction Y is C4. Where the size C2 of the third signal line 33 in the second direction Y is greater than the size C1 of the second signal line 32 in the second direction Y (C2>C1), C4=C3+C1. Or, where the size C1 of the second signal line 32 in the second direction Y is greater than the size C2 of the third signal line 33 in the second direction Y (C1>C2), C4=C3+C2. That is, the size C4 of the spacer 230 near the end of the array substrate 100 in the second direction Y is equal to the sum of the interval C3 between the second signal line 32 and the third signal line 33 and the size of the one of the second signal line 32 and the third signal line 33 that is smaller in the second direction Y. In this way, even if there is a certain alignment deviation between the spacer 230 and the array substrate 100, the total contact area between the spacer 230 and the second signal line 32 and the third signal line 33 remains unchanged when the spacer at least partially covers the region between the second signal line 32 and the third signal line 33, so that the spacer 230 can provide stable support for the liquid crystal layer 300, and the liquid crystal layer 300 can maintain a stable thickness, thereby ensuring the display effect of the display substrate.

[0211] In some embodiments, the distance from the side of the spacer 230 away from the color filter substrate 200 to the color filter substrate 200 (the second substrate 210) is equal. The length of the spacer 230 is greater than the pitch of the two adjacent first signal lines DL. The overlapping region of the first signal line DL and the signal line group 30 forms a plurality of columnar structures 50 protruding toward the color filter substrate 200, and the side of the spacer 230 away from the color filter substrate 200 abuts against part of the columnar structures 50. In this way, the spacer 230 cooperates with the first signal line DL and the signal line group 30 to form different spacer regions.

[0212] The part of the side of the spacer 230 away from the color filter substrate 200 that abuts against part of the columnar structures 50 forms a main spacer region 201. The part of the spacer 230 whose orthographic projection on the array substrate 100 coincides with the first signal line DL or the signal line group 30 but does not coincide with the columnar structures 50 forms a first auxiliary spacer region 202. The part of the spacer 230 whose orthographic projection on the array substrate 100 coincides with the region between the second signal line 32 and the third signal line 33 in the signal line group 30 forms a second auxiliary spacer region 203.

[0213] The columnar structure 50 abuts the spacer 230 on the side close to the color filter substrate 200. The distance between the region on the first signal line DL or the signal line group 30 where the columnar structure 50 is absent and the spacer 230 on the side close to the color filter substrate 200 is f. The distance between the region between the second signal line 32 and the third signal line 33 in the signal line group 30 and the spacer 230 is g. g > f > 0. In this way, the spacer 230 cooperates with the first signal line DL and the signal line group 30 to form the main spacer region 201, the first sub-spacer region 202 and the second sub-spacer region 203 with steps.

[0214] When the display substrate is in the normal state, the main spacer region 201 of the spacer 230 provides support for the liquid crystal cell thickness. When the display substrate 1100 is pressed, the color filter substrate 200 is pressed towards the array substrate 100, the spacer 230 is deformed by the pressing, and the first sub-spacer region 202 participates in the support for the liquid crystal cell thickness, i.e., the spacer 230 contacts the upper surface (the surface close to the color filter substrate) of the array substrate 100 at the position of the second signal line 32 and the third signal line 33. When the display substrate is pressed with great force, the degree of pressing of the color filter substrate 200 towards the array substrate 100 increases, and the degree of deformation of the spacer 230 increases. At this time, the second sub-spacer region 203 also participates in the support for the liquid crystal cell thickness, i.e., the spacer 230 also contacts the upper surface of the array substrate at the region between the second signal line 32 and the third signal line 33.

[0215] In some embodiments, the signal line group 30 is provided with a plurality of winding regions 34 along the length direction (the first direction X) thereof. The winding region 34 is provided at the position where the at least one signal line group 30 crosses the first signal line DL. The winding region 34 is provided at the position where the at least one second signal line 32 and / or the at least one third signal line 33 crosses the first signal line DL. The orthographic projection of the spacer 230 on the array substrate 100 in the winding region 34 does not overlap the columnar structure 50.

[0216] Exemplarily, the signal line group 30 includes the second signal line 32 and the third signal line 33, the second signal line 32 and the third signal line 33 extend along the length direction of the signal line group 30, i.e. the first direction X, in the non-winding area 35, in the winding area 34, the second signal line 32 bends away from the third signal line 33 for a distance, then extends along the length direction of the signal line group 30, bends away from the third signal line 33 after passing the first signal line DL, and extends to the position where the second signal line 32 in the non-winding area 35 is in line, then continues to extend along the length direction of the signal line group 30, i.e. the second signal line 32 protrudes along the second direction Y in the winding area 34 to avoid the spacer 230. In the winding area 34, the third signal line 33 bends away from the second signal line 32 for a distance, then extends along the length direction of the signal line group 30, bends away from the second signal line 32 after passing the columnar structure 50, and extends to the position where the third signal line 33 in the non-winding area 35 is in line, then continues to extend along the length direction of the signal line group 30, i.e. the third signal line 33 protrudes along the second direction Y in the winding area 34 to avoid the spacer 230. In this way, the original main spacer area 201 in the winding area 34 becomes the first auxiliary spacer area 202.

[0217] Exemplarily, in the winding area 34, the second signal line 32 bends away from the third signal line 33 for a distance h, the maximum alignment deviation of the array substrate 100 and the color filter substrate 200 in the second direction Y is e, and h is greater than or equal to e. The structure that the second signal line 32 and the third signal line 33 hold the spacer 230 in the winding area 34 can effectively prevent the spacer 230 from moving in the second direction Y.

[0218] In some embodiments, one spacer 230 is provided in the display substrate 1100 for every twenty-four pixel areas 101 on average. For example, in twenty-four pixel areas 101 arranged in two rows and twelve columns, one spacer 230 at least spans thirteen first signal lines DL in the length direction of the spacer 230, i.e. the spacer 230 spans twelve pixel areas 101 in the length direction of the spacer 230. The orthogonal projection of the spacer 230 on the array substrate 100 has an overlapping area with the thirteen first signal lines DL, and an overlapping area with a group of signal line groups 30. At least eleven of the positions where the thirteen first signal lines DL and the group of signal line groups 30 intersect are provided with winding areas 34. In this way, the contact density ratio of the main spacer area 201 and the first auxiliary spacer area 202 is close to 1:100. The main spacer area 201 and the first auxiliary spacer area 202 with the proportional contact density can not only support the liquid crystal cell thickness, but also meet the requirement of no dark spots under external pressure.

[0219] Of course, the arrangement of the spacers 230 and the arrangement of the winding regions 34 can be determined according to actual needs. For example, one spacer 230 can be arranged in each of 23, 24, 25, 26, or 27 pixel regions 101. One spacer 230 can span 12, 13, 14, 15, or 16 first signal lines DL in the length direction of the spacer 230, i.e., the spacer 230 can span 11, 12, 13, 14, or 15 pixel regions 101 in the length direction of the spacer 230. The number of winding regions 34 can also be 11, 12, 13, 14, or 15. As long as the contact density of the main spacer region 201 is close to 200 μm 2 / mm 2 , and the contact density of the first sub-spacer region 202 is close to 20000 μm 2 / mm 2 , the display substrate can be used.

[0220] The spacer 230 spans a plurality of first signal lines DL in the length direction of the spacer 230. As shown in FIG. 25, when the spacer 230 is displaced in the second direction Y by a large displacement, for example, the spacer 230 is displaced in the second direction Y to be out of alignment with the signal line group 30, the first signal line DL can still support the spacer 230. That is, when the spacer 230 is displaced in the second direction Y by a large displacement, the spacer 230 loses the first sub-spacer region 202 formed by the main spacer region 201 and the signal line group 30, but does not lose the first sub-spacer region 202 formed by the spacer 230 and the first signal line DL. Therefore, the large displacement of the spacer 230 in the second direction Y does not scratch the alignment film on the array substrate 100.

[0221] For example, the arrangement of the spacers 230 can be determined according to needs. For example, in a 24-pixel-region 101 array having three rows and eight columns, one main spacer region 201 and six to twelve first sub-spacer regions 202 can be arranged. Or, in a 24-pixel-region 101 array having four rows and six columns, one main spacer region 201 and six to twelve first sub-spacer regions 202 can be arranged. As long as the spacers 230 are arranged uniformly on the entire surface and the ratio of the contact density of the main spacer region 201 to the contact density of the first sub-spacer region 202 is close to 1:100, the display substrate can be used.

[0222] FIGS. 28 and 29 show the cell gap of display substrates having different contact densities of the main spacer region 201 and the first sub-spacer region 202 after the substrates are subjected to an external force when the spacers 230 are not displaced and when the spacers 230 are displaced.

[0223] The abscissa in FIGS. 28 and 29 is the contact density (μm 2 / mm 2 ) of the first sub-spacer region 202, and the ordinate is the cell gap (μm). The six lines from top to bottom in FIG. 28 represent the contact density of the main spacer region 201 being 100 μm 2 / mm 2 , 150 μm 2 / mm 2 , 200 μm 2 / mm 2 , 250 μm 2 / mm 2 , 300 μm 2 / mm 2 , 350 μm 2 / mm 2 . The six lines from top to bottom in Fig. 29 represent the contact density of the main spacer area 201 being 100 μm 2 / mm 2 , 150 μm 2 / mm 2 , 200 μm 2 / mm 2 , 250 μm 2 / mm 2 , 300 μm 2 / mm 2 , 350 μm 2 / mm 2 , respectively. It is obvious that the cell gap of the display substrate after being subjected to an external force increases gradually with the increase of the contact density of the first sub spacer area 202. When the contact density of the main spacer area 201 is 200 μm 2 / mm 2 , and the contact density of the first sub spacer area 202 is 20,000 μm 2 / mm 2 , the spacer 230 can provide better support for the cell gap.

[0224] Fig. 30 shows the display substrate with different contact densities of the main spacer area 201 and the first sub spacer area 202, and the deformation amount of the spacer 230 after being subjected to an external force when the spacer 230 is displaced. The abscissa in Fig. 30 is the contact density of the first sub spacer area 202 (μm 2 / mm 2 , and the ordinate is the cell deformation amount (μm). The six lines from top to bottom in Fig. 30 represent the contact density of the main spacer area 201 being 100 μm 2 / mm 2 , 150 μm 2 / mm 2 , 200 μm 2 / mm 2 , 250 μm 2 / mm 2 , 300 μm 2 / mm 2 , 350 μm 2 / mm 2The thickness of the first signal line DL is generally between 0.55 μm and 0.65 μm, and the thickness of the signal line group 30 is between 0.65 μm and 0.75 μm. It can be seen that when the contact density of the first sub-spacer area 202 is greater than 15000 μm 2 / mm 2 , and the contact density of the main spacer area 201 is greater than 150 μm 2 / mm 2 , the deformation amount of the spacer 230 is obviously less than the thickness of the first signal line DL. At this time, the displacement of the spacer 230 will not scratch the alignment film.

[0225] The third signal line 33 is provided with a second via V2 (as shown in Figure 4 ) near the intersection position of the first signal line DL, and the third signal line 33 is connected with the first electrode layer 21 through the second via V2. The second via V2 is arranged near the intersection position of the third signal line 33 with the first signal line DL, and when light leakage occurs due to the second via V2, the black matrix 60 can block the light leaked due to the second via V2, reducing the adverse effects of the second via V2 on the display effect of the display substrate 1100.

[0226] In some embodiments, referring to FIGS. 31, 32 and 33, the signal line group 30 includes a second signal line 32. The second signal line 32 controls the connection of the first signal line DL with the liquid crystal capacitor Clc and the storage capacitor Cst (the second electrode 22), that is, the second signal line 32 controls whether the first signal line DL charges the liquid crystal capacitor Clc and the storage capacitor Cst.

[0227] Exemplarily, one signal line group 30 includes one second signal line 32. The second signal line 32 controls the on-off between the first signal line DL of one row of pixel areas 101 and the second electrode 22 of the row of pixel areas, and the second signal line 32 of the adjacent row of pixel areas 101 provides a stable voltage for one end of the liquid crystal capacitor Clc and the storage capacitor Cst.

[0228] The orthogonal projection of the spacer 230 on the array substrate 100 covers the second signal line 32 in the signal line group 30. That is, the orthogonal projection of the spacer 230 on the array substrate 100 covers the second signal line 32 in the length range of the spacer 230.

[0229] Exemplarily, the width of the spacer 230 can be C4, the width of the second signal line 32 can be C1, the alignment deviation of the array substrate 100 and the color filter substrate 200 is e, that is, the maximum alignment deviation of the array substrate 100 and the color filter substrate 200 in the second direction Y during the alignment of the array substrate 100 and the color filter substrate 200 is e, and C4 is greater than C1. In some embodiments, C4 is greater than or equal to C1+2e, that is, the orthographic projection of the spacer 230 on the array substrate 100 covers the second signal line 32 in the signal line group 30, and the distance between the two sides of the second signal line 32 and the two sides of the orthographic projection of the spacer 230 on the array substrate 100 is greater than or equal to e. In this way, when a slight deviation occurs during the alignment of the array substrate 100 and the color filter substrate 200, the width of the overlapping part of the orthographic projection of the spacer 230 on the array substrate 100 and the second signal line 32 is always C1. In this way, it can be ensured that the spacer 230 can provide stable support for the liquid crystal layer 300, thereby ensuring that the liquid crystal layer 300 can maintain a stable thickness, thereby ensuring the display effect of the display substrate.

[0230] In some embodiments, the distance from the side of the spacer 230 away from the color filter substrate 200 to the color filter substrate 200 is equal. The overlapping area of the first signal line DL and the signal line group 30 forms a plurality of columnar structures 50 protruding towards the color filter substrate 200, and the side of the spacer 230 away from the color filter substrate 200 abuts against part of the columnar structures 50. In this way, the spacer 230 cooperates with the first signal line DL and the signal line group 30 to form different spacer regions. The part of the side of the spacer 230 away from the color filter substrate 200 abutting against part of the columnar structures 50 forms a main spacer region 201. The part of the orthographic projection of the spacer 230 on the array substrate 100 overlapping with the first signal line DL or the signal line group 30, but not overlapping with the columnar structures 50, forms a first auxiliary spacer region 202.

[0231] The part of the orthographic projection of the spacer 230 on the array substrate 100 overlapping with the area of the array substrate 100 other than the second signal line 32 forms a second auxiliary spacer region 203. The side of the columnar structure 50 close to the color filter substrate 200 abuts against the spacer 230. The distance between the area of the first signal line DL or the signal line group 30 other than the columnar structure 50 and the side of the spacer 230 close to the color filter substrate 200 is f. The distance between the part of the area of the array substrate 100 other than the second signal line 32 and the spacer 230 is g. g>f>0, so that the spacer 230 cooperates with the first signal line DL and the signal line group 30 to form the main spacer region 201, the first auxiliary spacer region 202 and the second auxiliary spacer region 203 with steps.

[0232] In the normal state, the main spacer region 201 of the spacer 230 provides support for the liquid crystal cell thickness. When the display substrate is pressed, the color filter substrate 200 is deflected towards the array substrate 100, and the first sub-spacer region 202 participates in the support of the liquid crystal cell thickness. When the display substrate is pressed with a large force, the color filter substrate 200 is deflected to a greater extent towards the array substrate 100, and at this time the second sub-spacer region 203 also begins to participate in the support of the liquid crystal cell thickness.

[0233] The signal line group 30 is provided with a plurality of winding regions 34 along the length direction thereof. At least one winding region 34 is provided at a position where the first signal line DL intersects with the signal line group 30. The spacer 230 has no overlapping region with the columnar structure 50 in the orthographic projection of the spacer 230 on the array substrate 100 in the winding region 34. Exemplarily, the signal line group 30 includes the second signal line 32, which extends along the length direction of the signal line group 30, i.e., the first direction X, in the non-winding region 35, is bent by a distance in a direction perpendicular to the length direction of the signal line group 30, i.e., the second direction Y, in the winding region 34, then extends along the length direction of the signal line group 30, is bent back after passing around the columnar structure 50 to a position where the second signal line 32 in the non-winding region 35 is collinear, and then continues to extend along the length direction of the signal line group 30, i.e., the second signal line 32 in the winding region 34 protrudes along the second direction Y to avoid the spacer 230. In this way, the original main spacer region 201 in the winding region 34 becomes the first sub-spacer region 202.

[0234] In some embodiments, the distance by which the second signal line 32 is bent in the winding region 34 in the direction perpendicular to the length direction of the signal line group 30, i.e., the second direction Y, is h, and the maximum alignment deviation of the array substrate 100 and the color filter substrate 200 in the second direction Y is e, and h is greater than or equal to e.

[0235] In some embodiments, one spacer 230 is provided in the display substrate for every twelve pixel regions 101 on average. Exemplarily, in twelve pixel regions 101 arranged in one row and twelve columns, one spacer 230 at least spans thirteen first signal lines DL in the length direction thereof, i.e., the spacer 230 spans the twelve pixel regions 101 in the length direction thereof. The orthographic projection of the spacer 230 on the array substrate 100 has overlapping regions with the thirteen first signal lines DL and overlapping regions with a group of signal line groups 30. At least eleven of the intersections of the thirteen first signal lines DL and the group of signal line groups 30 are provided with winding regions 34. In this way, the contact density ratio of the main spacer region 201 and the first sub-spacer region 202 is close to 1:100. The main spacer region 201 and the first sub-spacer region 202 with this proportional contact density can meet the requirements of support of the liquid crystal cell thickness and no dark spots under external force pressing.

[0236] In some embodiments, the arrangement of the spacers 230 can be determined according to requirements. For example, in an arrangement of twelve pixel regions 101 in two rows and six columns, one main spacer region 201 and six to twelve first sub-spacer regions 202 can be provided. Alternatively, in an arrangement of twenty-four pixel regions 101 in three rows and four columns, one main spacer region 201 and six to twelve first sub-spacer regions 202 can be provided, and so on. It is only required that the spacers 230 are arranged uniformly on the entire surface and that the ratio of the contact density of the main spacer region 201 to the first sub-spacer region 202 is close to 1:100. Of course, the arrangement of the spacers 230 and the arrangement of the winding regions 34 can be determined according to actual requirements. For example, one spacer 230 can be provided for an average of 12, 13, 14, 15 or 16 pixel regions 101. One spacer 230 spans 12, 13, 14, 15 or 16 first signal lines DL in the length direction of the spacer 230, i.e., the spacer 230 spans 11, 12, 13, 14 or 15 pixel regions 101 in the length direction of the spacer 230. The number of winding regions 34 can also be 11, 12, 13, 14 or 15. As long as the contact density of the main spacer region 201 is close to 200 μm 2 / mm 2 and the contact density of the first sub-spacer region 202 is close to 20000 μm 2 / mm 2 , the requirements can be met.

[0237] The spacers 230 span a plurality of first signal lines DL in the length direction (the first direction X) of the spacers 230. When the spacers 230 are displaced in the second direction Y by a large displacement, for example, the spacers 230 are displaced in the second direction Y to be out of alignment with the signal line group 30, the surface of the region where the first signal lines DL are located still supports the spacers 230. That is, when the spacers 230 are displaced in the second direction Y by a large displacement, the first sub-spacer regions 202 formed by the alignment of the main spacer region 201 and the signal line group 30 are lost, but the first sub-spacer regions 202 formed by the alignment of the spacers 230 and the first signal lines DL are not lost. Therefore, the large displacement of the spacers 230 in the second direction Y does not scratch the alignment film on the array substrate 100.

[0238] As shown in FIG. 27 and FIGS. 34-35, in some embodiments, the orthogonal projection of the spacers 230 on the array substrate 100 partially overlaps the signal line group 30. The distance from the color filter substrate 200 to the side of the spacers 230 away from the color filter substrate 200 is not equal. The spacers 230 include a main spacer region 201 having a first thickness and a first sub-spacer region 202 having a second thickness, the first thickness being greater than the second thickness. The orthogonal projection of the main spacer region 201 on the array substrate 100 overlaps the first signal line DL, and the orthogonal projection of the main spacer region 201 on the array substrate 100 does not overlap the signal line group 30. The orthogonal projection of the main spacer region 201 on the array substrate 100 covers at least two first signal lines DL in the length direction of the spacers 230. The partial orthogonal projection of the first sub-spacer region 202 on the array substrate 100 overlaps the first signal line DL, and the partial orthogonal projection of the first sub-spacer region 202 on the array substrate 100 overlaps the signal line group 30.

[0239] The signal line group 30 is provided with a plurality of winding regions 34 in the length direction thereof. At least one winding region 34 is provided at the position where the signal line group 30 crosses the first signal line DL. In the winding region 34, the signal line group 30 avoids the region where the spacers 230 overlap the first signal line DL. That is, the spacers 230, the signal line group 30, and the first signal line DL do not overlap at the same time. Meanwhile, the winding region 34 is also provided at the position of the orthogonal projection of the main spacer region 201 on the array substrate 100, and in the winding region 34, the signal line group 30 avoids the range covered by the orthogonal projection of the main spacer region 201 on the array substrate 100. The maximum alignment deviation of the array substrate 100 and the color filter substrate 200 in the second direction Y is e, and in the winding region 34, the distance from the signal line group 30 to the region where the spacers 230 overlap the first signal line DL is greater than e, and in the winding region 34, the distance from the signal line group 30 to the range covered by the orthogonal projection of the main spacer region 201 on the array substrate 100 is greater than e. That is, in the winding region 34, the orthogonal projection of the first sub-spacer region 202 on the array substrate 100 overlaps the first signal line DL, and in the non-winding region 35, the orthogonal projection of the first sub-spacer region 202 on the array substrate 100 overlaps the signal line group 30.

[0240] In some embodiments, one spacer 230 is provided in the display substrate for every twenty-four pixel regions 101 on average. For example, in twenty-four pixel regions 101 arranged in two rows and twelve columns, one spacer 230 spans at least thirteen first signal lines DL in the length direction of the spacer 230, i.e. the spacer 230 spans twelve pixel regions 101 in the length direction of the spacer 230. The orthogonal projection of the spacer 230 on the array substrate 100 has an overlapping region with the thirteen first signal lines DL and an overlapping region with one group of signal line groups 30. The position where the thirteen first signal lines DL and the one group of signal line groups 30 cross each other is provided with a winding region 34. One spacer 230 is provided with one main spacer region 201. In this way, the ratio of the contact density of the main spacer region 201 to the first auxiliary spacer region 202 is close to 1:100. The ratio of the contact density of the main spacer region 201 to the first auxiliary spacer region 202 can meet the requirements of supporting the thickness of the liquid crystal cell and the requirement of no dark spots under external pressure.

[0241] Exemplarily, the arrangement of the spacer 230 can be determined according to requirements. For example, in twenty-four pixel regions 101 arranged in three rows and eight columns, one main spacer region 201 and six to twelve first auxiliary spacer regions 202 can be provided. Alternatively, in twenty-four pixel regions 101 arranged in four rows and six columns, one main spacer region 201 and six to twelve first auxiliary spacer regions 202 can be provided. It is only required that the spacers 230 are arranged uniformly on the entire surface and that the ratio of the contact density of the main spacer region 201 to the first auxiliary spacer region 202 is close to 1:100. Of course, the arrangement of the spacers 230 and the arrangement of the winding regions 34 described above can be determined according to actual requirements. One spacer 230 can be provided for every 23, 24, 25, 26 or 27 pixel regions 101 on average. One spacer 230 spans 12, 13, 14, 15 or 16 first signal lines DL in the length direction of the spacer 230, i.e. the spacer 230 spans 11, 12, 13, 14 or 15 pixel regions 101 in the length direction of the spacer 230. The number of winding regions 34 can also be 11, 12, 13, 14 or 15. As long as the contact density of the main spacer region 201 is close to 200 μm 2 / mm 2 and the contact density of the first auxiliary spacer region 202 is close to 20000 μm 2 / mm 2Yes. The spacer 230 crosses the plurality of first signal lines DL in the length direction thereof. When the spacer 230 is displaced in the second direction Y by a large amount, for example, the spacer 230 is displaced in the second direction Y to be out of coincidence with the signal line group 30, the first signal line DL can still support the spacer 230. That is, when the spacer 230 is displaced in the second direction Y by a large amount, the spacer 230 loses the first sub-spacer region 202 formed by the main spacer region 201 being coincident with the signal line group 30, but does not lose the first sub-spacer region 202 formed by being coincident with the first signal line DL. Meanwhile, the main spacer region 201 of the spacer 230, which is coincident with the first signal line DL, does not lose the support capability due to the displacement of the spacer 230 in the second direction Y. Therefore, the large displacement of the spacer 230 in the second direction Y does not scratch the alignment film on the array substrate 100.

[0242] In some embodiments, referring to FIGS. 26 and 36, the orthographic projection of the black matrix 60 on the array substrate 100 covers the spacer 230, the first signal line DL, and the signal line group 30.

[0243] As shown in FIG. 36, the black matrix 60 further includes a first portion 61. The orthographic projection of the first portion 61 on the array substrate 100 covers the semiconductor pattern 10, the first pattern LS, the region where the signal line group 30 overlaps the first signal line DL, and the region where the signal line group 30 is disposed opposite to the semiconductor pattern 10 and the first pattern LS in the second direction Y. The first portion 61 and the spacer 230 are close to each other in the orthographic projection of the array substrate 100, and the border between the close-to-each-other regions has a fourth interval D4 of 20 μm to 40 μm. In this way, the first portion 61 can shield the semiconductor pattern 10, the first pattern LS, the region where the signal line group 30 overlaps the first signal line DL, and the region where the signal line group 30 is disposed opposite to the semiconductor pattern 10 and the first pattern LS in the second direction Y, and reduce the risk of light leakage around the above-mentioned regions.

[0244] Exemplarily, the fourth interval D4 can be in the range of 20 μm to 30 μm, or the fourth interval D4 can be in the range of 30 μm to 40 μm. For example, the fourth interval D4 can be 20 μm, 25 μm, 30 μm, 35 μm, or 40 μm, and the like. Embodiments of the present disclosure do not list all the values of the fourth interval D4.

[0245] In some embodiments, referring to FIGS. 26 and 37, the black matrix 60 further includes a second portion 62, a projection of the second portion 62 on the array substrate 100 covers a region of the signal line group 30 in the second direction Y that is offset from the first pattern LS and the semiconductor pattern 10, and the portion of the black matrix 60 covering the same signal line group 30 includes the first portion 61 and the second portion 62 staggered along the first direction X. The second portion 62 and the signal line group 30 have a fifth interval D5 between boundaries close to each other in the projection of the array substrate 100, and the fifth interval D5 is 3 μm to 6 μm. In this way, the second portion 62 can shield the region of the signal line group 30 in the second direction Y that is offset from the first pattern LS and the semiconductor pattern 10, and reduce the risk of light leakage from both sides of the region in the second direction Y. Exemplarily, the fifth interval D5 can be 3 μm, 4 μm, 3.5 μm, 5 μm, or 6 μm, and the like, and the embodiments of the present disclosure will not list them one by one.

[0246] In some embodiments, referring to FIGS. 26 and 38, in the case where the first insulating layer BUF is directly disposed on the first conductive layer SD, in the case where the first insulating layer BUF includes a first groove portion 41 recessed in a direction close to the first substrate 110, and the first groove portion 41 is at least partially located between the first signal line DL and the first pattern LS, the black matrix 60 further includes a third portion 63, a projection of the third portion 63 on the array substrate 100 covers the first signal line DL, and the third portion 63 and the first signal line DL have a sixth interval D6 between boundaries close to each other on the first substrate 110, and the sixth interval D6 is 0.5 μm to 2 μm. The third portion 63 can shield the reflection of ambient light by the first signal line DL, and also reduce the risk of light leakage from both sides of the first signal line DL due to the step difference of the first signal line DL. Exemplarily, the sixth interval D6 can be 0.5 μm, 1 μm, 1.5 μm, or 2 μm, and the like, and the embodiments of the present disclosure will not list them one by one.

[0247] In some embodiments, referring to FIG. 26 and FIG. 39, in the case that the array substrate 100 further comprises a planar layer SOG between the first conductive layer SD and the first insulating layer BUF, the planar layer SOG is a planar surface away from the surface of the first substrate 110, and the planar layer SOG comprises a first planar portion S1 covering the first signal line DL. The black matrix 60 comprises a third portion 63, a projection of the third portion 63 on the array substrate 100 covers the first planar portion S1, and the third portion 63 and the first planar portion S1 have a seventh interval D7 between mutually close boundaries in the projection of the third portion 63 and the first planar portion S1 on the first substrate 110, and the seventh interval D7 is 0.5 μm to 2 μm. The third portion 63 can shield the reflection of ambient light by the first signal line DL, and can also reduce the risk of light leakage on both sides of the first signal line DL due to the step formed by the planar layer SOG. Exemplarily, the seventh interval D7 can be 0.5 μm, 1 μm, 1.5 μm, or 2 μm, and the like, and the embodiments of the present disclosure will not list them one by one.

[0248] In some embodiments, in the case that the first insulating layer BUF of the array substrate 100 is directly disposed on the first conductive layer SD, and the display substrate comprises the array substrate and the color film substrate described in any of the above embodiments, the transmittance of the display substrate is greater than or equal to 6%. Exemplarily, the transmittance of the display substrate is 6%, 6.5%, 6.6%, 7%, 8%, or 8.5%, and the like, and the embodiments of the present disclosure will not list them one by one.

[0249] Exemplarily, in the case that the display substrate is lighted (the display substrate displays the maximum gray scale), the brightness of the display substrate is tested at more than 9 points by using a CCD device, and then the transmittance of the display substrate can be obtained by dividing the average value of the brightness detected at each point by the backlight brightness at the corresponding position. It is found through actual detection that the transmittance of the display substrate through the embodiments of the present disclosure can reach at least 6%, and compared with the conventional ADS display substrate, the transmittance can be improved by more than 50%. In some embodiments, in the case that the array substrate 100 further comprises a planar layer SOG between the first conductive layer SD and the first insulating layer BUF, and the display substrate comprises the array substrate and the color film substrate described in any of the above embodiments, the transmittance of the display substrate is greater than or equal to 9%. Exemplarily, the transmittance of the display substrate is 9%, 9.5%, 10%, 10.5%, or 11%, and the like, and the embodiments of the present disclosure will not list them one by one.

[0250] Exemplarily, in the case that the display substrate is lighted (the display substrate displays the maximum gray scale), the display substrate is tested for brightness at more than 9 points by using a CCD device, and then the detected brightness at each point is divided by the backlight brightness at the corresponding position, and the average value is obtained to obtain the transmittance of the display substrate. It is found through actual detection that the transmittance of the display substrate according to the embodiment of the present disclosure can reach at least 9%, and compared with the conventional display substrate, the transmittance can be improved by more than 40%.

[0251] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art who thinks of changes or replacements within the technical range disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising an array substrate and a color filter substrate; wherein, The array substrate includes: First substrate; A first conductive layer is disposed on one side of the first substrate and includes first signal lines and a first pattern spaced apart. A first insulating layer is disposed on the side of the first conductive layer away from the first substrate; The first via penetrates at least the first insulating layer and exposes at least a portion of the first signal line; A semiconductor layer is disposed on the side of the first insulating layer away from the first substrate, and includes a semiconductor pattern; the semiconductor pattern includes a first portion, a second portion, and a channel structure located between the first portion and the second portion; the orthographic projection of the first portion on the first substrate partially coincides with the orthographic projection of the first signal line on the first substrate, and the orthographic projection of the channel structure on the first substrate is located within the range of the orthographic projection of the first pattern on the first substrate; A connecting electrode is disposed on the side of the semiconductor layer away from the first substrate, at least a portion of the connecting electrode is located within the first via and is connected to the first part and the first signal line respectively; A first electrode is disposed on the side of the film layer where the connecting electrode is located away from the first substrate. The orthographic projection of the first electrode on the first substrate covers the orthographic projection of the first signal line on the first substrate. The first electrode includes a first extension segment, the extension direction of the first extension segment is the same as the extension direction of the first signal line, the orthographic projection of the first extension segment on the first substrate covers the orthographic projection of the first signal line on the first substrate, and there is a first gap between the boundaries of the first extension segment and the orthographic projection of the first signal line on the first substrate that are close to each other.

2. The display substrate according to claim 1, wherein, The first interval is 2μm~5μm.

3. The display substrate according to claim 1, wherein, The semiconductor layer further includes a second electrode, which is connected to and integrally formed with the second part.

4. The display substrate according to claim 3, wherein, The orthographic projection of the second electrode on the first substrate has a second interval with the orthographic projection of the first pattern on the first substrate, and a third interval with the orthographic projection of the first signal line on the first substrate.

5. The display substrate according to claim 4, wherein, The first insulating layer includes a first groove recessed in a direction close to the first substrate, the first groove being at least partially located between the first signal line and the first pattern; The second interval is greater than or equal to 2 μm; and / or, the third interval is greater than or equal to 5 μm.

6. The display substrate according to claim 4, wherein, The array substrate further includes a planarization layer, which is located between the first conductive layer and the first insulating layer, and the surface of the planarization layer away from the first substrate is a flat surface. The orthographic projections of the first conductive layer, the second spacing, and the third spacing onto the first substrate are located within the range of the orthographic projection of the planarization layer onto the first substrate; the second spacing is greater than or equal to 1 μm; and / or, the third spacing is greater than or equal to 3 μm.

7. The display substrate according to claim 1, wherein, The first insulating layer includes a first groove recessed inward toward the first substrate, at least a portion of the first groove being located between the first signal line and the first pattern; the first groove includes two first sidewalls disposed opposite to each other; The first part includes two first sub-parts covering the two first sidewalls, and a second sub-part covering other areas of the first insulating layer, wherein the thickness of the first sub-parts is less than the thickness of the second sub-parts.

8. The display substrate according to claim 7, wherein, The array substrate further includes a second insulating layer, which is disposed between the semiconductor layer and the film layer containing the connecting electrode; Of the two first sub-sections, the first sub-section closest to the first signal line is the target sub-section. The first via penetrates the second insulating layer and exposes the target sub-section. The connecting electrode covers the target sub-section. The dimension of the channel structure in the direction perpendicular to the first substrate is greater than or equal to 300 Å.

9. The display substrate according to claim 7, wherein, The array substrate further includes a second insulating layer, which is disposed between the semiconductor layer and the film layer containing the connecting electrode; Of the two first sub-parts, the first sub-part closer to the first signal line is the target sub-part. The first via also penetrates the second insulating layer, and the first via is spaced apart from the target sub-part. The dimension of the channel structure in the direction perpendicular to the first substrate is greater than or equal to 100 Å.

10. The display substrate according to claim 7, wherein, The array substrate further includes a second insulating layer, which is disposed between the semiconductor layer and the film layer containing the connecting electrode; Of the two first sub-sections, the first sub-section closest to the first signal line is the target sub-section. The first via penetrates the second insulating layer and exposes the target sub-section. The connecting electrode is spaced from the target sub-section. The dimension of the channel structure in the direction perpendicular to the first substrate is greater than or equal to 600 Å.

11. The display substrate according to claim 7, wherein, Along a direction perpendicular to the first substrate, the size of the first conductive layer is 0.4 μm to 0.8 μm; And / or, In a cross section extending perpendicular to the first substrate and perpendicular to the edge of the first conductive layer, the sidewall of the first conductive layer has a first included angle with the first substrate, the first included angle being less than or equal to 50°.

12. The display substrate according to claim 1, wherein, The array substrate further includes a planarization layer located between the first conductive layer and the first insulating layer, wherein the surface of the planarization layer away from the first substrate is a flat surface; the planarization layer at least covers the first signal line, the first pattern, and the spacing between the first signal line and the first pattern. The semiconductor layer further includes a second electrode, which is connected to and integrally disposed with the second part. The orthographic projection of the second electrode on the first substrate does not at least partially overlap with the orthographic projection of the planarization layer on the first substrate.

13. The display substrate according to claim 12, wherein, In a cross section perpendicular to the first substrate and perpendicular to the extension direction of the sidewall of the planarization layer, the sidewall of the planarization layer has a second included angle with the first substrate, the second included angle being less than or equal to 50°; and / or, the distance between the surface of the planarization layer away from the first substrate and the first substrate is 0.4 μm to 0.8 μm.

14. The display substrate according to any one of claims 1 to 13, wherein, The first conductive layer includes a plurality of first signal lines, which are spaced apart along a first direction and all extend along a second direction; The array substrate further includes multiple signal line groups, which are spaced apart along the second direction and all extend along the first direction. Multiple first signal lines and multiple signal line groups intersect to form a grid structure. The area where the orthographic projections of the signal line groups and the first signal lines on the first substrate overlap protrudes to the side away from the first substrate to form a columnar structure. The color filter substrate includes spacers; the spacers are strip-shaped and extend along the first direction, and the orthographic projection of the spacers on the array substrate partially coincides with the first signal line and the signal line group. The signal line group includes a winding area, and at least one of the signal line groups is provided at the position where it intersects with the first signal line. The orthogonal projection of the spacer in the winding area onto the array substrate does not coincide with the columnar structure.

15. The display substrate according to claim 14, wherein, The side of the spacer away from the color filter substrate abuts against a portion of the columnar structure.

16. The display substrate according to claim 15, wherein, The spacer is equidistant from the color filter substrate on the side away from the color filter substrate.

17. The display substrate according to claim 14, wherein, The signal line group within the winding area protrudes in the first direction.

18. The display substrate according to claim 14, wherein, The dimension of the spacer along the first direction is greater than the spacing between two adjacent first signal lines.

19. The display substrate according to claim 14, wherein, The signal line group and the connecting electrode are made of the same material and are arranged in the same layer.

20. The display substrate according to claim 16, wherein, The signal line group includes a second signal line, and the orthographic projection of the second signal line on the color filter substrate coincides with the spacer. The second signal line has a dimension of C1 in the second direction, and the end of the spacer near the array substrate has a dimension of C4 in the second direction, where C4 is greater than C1.

21. The display substrate according to claim 17, wherein, The signal line group includes a second signal line and a third signal line, and the orthographic projection of the spacer on the array substrate covers the area between the second signal line and the third signal line; The orthographic projection of the spacer on the array substrate partially coincides with the second signal line. The orthographic projection of the spacer on the array substrate partially coincides with the third signal line.

22. The display substrate according to claim 21, wherein, The second signal line has a dimension of C1 in the second direction, the third signal line has a dimension of C2 in the second direction, the interval between the second signal line and the third signal line is C3, and the end of the spacer near the array substrate has a dimension of C4 in the second direction. C1, C2, C3, and C4 satisfy: C2 > C1, C4 = C3 + C1; or, C1, C2, C3, and C4 satisfy the following conditions: C1 > C2, C4 = C3 + C2.

23. The display substrate according to claim 21, wherein, The winding area is provided at the location where at least one of the second signal lines and / or at least one of the third signal lines intersect with the first signal line.

24. The display substrate according to claim 23, wherein, The array substrate includes a first electrode, and the third signal line is connected to the first electrode on one side of the protrusion in the winding region along the first direction.

25. The display substrate according to claim 19, wherein, The orthographic projection of one of the spacers on the array substrate overlaps with at least thirteen of the first signal lines and with one of the signal line groups; the winding area is provided at at least eleven of the intersections of the at least thirteen first signal lines and the one signal line group.

26. The display substrate according to claim 25, wherein, A grid structure consisting of multiple first signal lines and multiple groups of signal lines defines multiple pixel areas; at least one of the spacers is provided in every twenty-four pixel areas.

27. The display substrate according to claim 15, wherein, The orthographic projection of the spacer on the array substrate coincides with the signal line group or the first signal line; the spacer includes a main spacer region with a first thickness and a secondary spacer region with a second thickness, the first thickness being greater than the second thickness; the orthographic projection of the main spacer region on the array substrate overlaps with the first signal line, and the orthographic projection of the main spacer region on the array substrate does not coincide with the signal line group.

28. The display substrate according to claim 27, wherein, The orthographic projection of the main spacer region onto the array substrate overlaps with at least two of the first signal lines.

29. The display substrate according to claim 15, wherein, The color filter substrate also includes a black matrix; the orthogonal projection of the black matrix onto the array substrate covers the spacer, the first signal line, and the signal line group.

30. The display substrate according to claim 29, wherein, The black matrix includes a first part, the orthographic projection of the first part on the array substrate covering the semiconductor pattern, the first pattern, and the overlapping area of ​​the signal line group and the first signal line; the surfaces of the first part and the spacer near the array substrate have a fourth gap between their adjacent boundaries in the orthographic projection on the array substrate, the fourth gap being 20μm~40μm.

31. The display substrate according to claim 29, wherein, The black matrix further includes a second part, the orthographic projection of which covers the area of ​​the signal line group that is offset from the first pattern and the semiconductor pattern in the second direction. The portion of the black matrix covering the same signal line group includes the first part and the second part, which are staggered along the first direction. In the orthographic projection of the second part and the signal line group on the array substrate, there is a fifth interval between their adjacent boundaries, the fifth interval being 3μm to 6μm.

32. The display substrate according to claim 29, wherein, The first insulating layer includes a first groove recessed in a direction close to the first substrate, at least a portion of the first groove being located between the first signal line and the first pattern; The black matrix further includes a third part, the orthographic projection of the third part on the array substrate covering the first signal line, and there is a sixth interval between the boundaries of the third part and the first signal line in their orthographic projections on the first substrate, the sixth interval being 0.5μm~2μm.

33. The display substrate according to claim 32, wherein, The transmittance of the display substrate is greater than or equal to 6%.

34. The display substrate according to claim 29, wherein, The array substrate further includes a planarization layer, which is located between the first conductive layer and the first insulating layer, and the surface of the planarization layer away from the first substrate is a flat surface; the planarization layer includes a first flat portion, which covers the first signal line. The black matrix includes a third part, the orthographic projection of the third part on the array substrate covers the first flat portion, and there is a seventh interval between the boundaries of the third part and the first flat portion that are close to each other in the orthographic projection on the first substrate, the seventh interval being 0.5μm~2μm.

35. The display substrate according to claim 34, wherein, The transmittance of the display substrate is greater than or equal to 9%.

36. A display device, comprising: The display substrate as described in any one of claims 1 to 35; A driver circuit board, electrically connected to the display substrate, is configured to transmit control signals to the display substrate.

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