Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device.A pixel circuit of the display panel comprises a semiconductor pattern, a first light-emitting control signal line and a second light-emitting control signal line, and the semiconductor pattern is formed by extending a semiconductor wire; a first light-emitting control signal line and a second light-emitting control signal line which extend in parallel are respectively overlapped with the projection of the semiconductor pattern, and the overlapped parts respectively form a first light-emitting control transistor and a second light-emitting control transistor; the first light-emitting control signal line is used for transmitting a first light-emitting control signal, the second light-emitting control signal line is used for transmitting a second light-emitting control signal, and the pulse change frequency of the first light-emitting control signal is smaller than that of the second light-emitting control signal. According to the embodiment of the invention, the coupling capacitance influence of the light-emitting control transistor is reduced, the abnormal light emitting of the light-emitting element is avoided, and the color brightness uniformity of the organic light-emitting display panel at a low gray scale in a PWM driving mode is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, organic light-emitting display technology has become more and more widely used in display panels with display functions such as mobile phones, computers, televisions, car displays or smart wearables due to its advantages such as self-luminescence, low driving voltage, high luminous efficiency, fast response speed, light weight and high contrast.

[0003] However, the existing organic light emitting display panel still has the problem of poor display effect in low brightness display mode and cannot fully meet the application requirements of the display panel. Summary of the invention

[0004] The present invention provides a display panel and a display device to improve the color brightness uniformity of an organic light emitting display panel at low gray scale under a pulse width modulation (PWM) driving mode.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, comprising a plurality of pixel circuits and a plurality of light-emitting elements, wherein the pixel circuits are electrically connected to the light-emitting elements and are used to drive the light-emitting elements to emit light;

[0006] The pixel circuit comprises a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving transistor, the second light-emitting control transistor and the light-emitting element are sequentially connected in series to a first power signal terminal and a second power signal terminal;

[0007] The pixel circuit further includes a semiconductor pattern, a first light-emitting control signal line and a second light-emitting control signal line, the semiconductor pattern is formed by extending a semiconductor wiring, the first light-emitting control signal line and the second light-emitting control signal line extend in parallel, the first light-emitting control signal line and the second light-emitting control signal line overlap with the semiconductor pattern respectively in projection, and the overlapping parts constitute the first light-emitting control transistor and the second light-emitting control transistor respectively;

[0008] The first light-emitting control signal line is used to transmit a first light-emitting control signal, the second light-emitting control signal line is used to transmit a second light-emitting control signal, and a pulse change frequency of the first light-emitting control signal is less than a pulse change frequency of the second light-emitting control signal.

[0009] In a second aspect, an embodiment of the present invention further provides a display device, comprising any display panel provided by an embodiment of the present invention.

[0010] The technical solution of the embodiment of the present invention is to set a semiconductor pattern, a first light-emitting control signal line and a second light-emitting control signal line in a pixel circuit, wherein the semiconductor pattern is formed by extending a semiconductor routing, the first light-emitting control signal line and the second light-emitting control signal line extend in parallel, the first light-emitting control signal line and the second light-emitting control signal line overlap with the projection of the semiconductor pattern respectively, and the overlapping parts constitute a first light-emitting control transistor and a second light-emitting control transistor respectively; the first light-emitting control signal line is used to transmit the first light-emitting control signal, and the second light-emitting control signal line is used to transmit the second light-emitting control signal, and the pulse change frequency of the first light-emitting control signal is less than the pulse change frequency of the second light-emitting control signal, which can reduce the voltage of the node between the first light-emitting control transistor and the driving transistor from being affected by the coupling effect of the first light-emitting control signal EmitA, thereby avoiding the anode of the light-emitting element from being affected by the voltage change of the node, preventing the light-emitting element from abnormally emitting light, and improving the color brightness uniformity of the organic light-emitting display panel at low grayscale under the PWM driving mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a pixel circuit diagram in a display panel of the related art;

[0012] Figure 2 yes Figure 1 The driving timing diagram of the pixel circuit shown;

[0013] Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0014] Figure 4 yes Figure 3 A schematic diagram of the structure of a pixel circuit and a light-emitting element in the display panel shown;

[0015] Figure 5 yes Figure 4 A schematic diagram of a partial layout structure of a pixel circuit shown;

[0016] Figure 6 yes Figure 4 The driving timing diagram of the pixel circuit shown;

[0017] Figure 7 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0018] Figure 8 is another schematic diagram of a layout structure of a pixel circuit provided by an embodiment of the present invention;

[0019] Fig. 9 It is another schematic diagram of a layout structure of a pixel circuit provided by an embodiment of the present invention;

[0020] Fig.10 is another schematic diagram of a layout structure of a pixel circuit provided by an embodiment of the present invention;

[0021] Fig.11 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0023] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes and do not represent any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances.

[0024] The term “including” and its variations used in the present invention are open inclusions, that is, “including but not limited to.” The term “based on” means “based at least in part on.” The term “one embodiment” means “at least one embodiment.”

[0025] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish the corresponding contents, and are not used to limit the order or interdependence.

[0026] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0027] Figure 1 is a pixel circuit diagram in a display panel of the related art, Figure 2 yes Figure 1 The driving timing diagram of the pixel circuit shown in FIG. 1 is a diagram showing the components and connection relationships in the pixel circuit of the display panel. Figure 1 As shown, no further details are given here. For the pixel circuit, in one display frame, reference Figure 2 , and its driving process may include a gate reset stage t1, a data writing stage t2, and a light emitting stage t3. In the gate reset stage t1, the first scanning signal S1 is at a low level, the transistor M5 is turned on, and the gate of the driving transistor M3, that is, the N1 node, is written with the reset signal Vref; in the data writing stage t2, the second scanning signal S2 is at a low level, the transistors M2 and M4 are turned on, and the data signal Vdata is sequentially written to the N1 node through the N2 node and the N3 node, and is stored in the capacitor Cst; in the light emitting stage t3, when the light emitting control signal Emit is at a low level, the transistors M1 and M6 are turned on, and a path is formed between the two power supply terminals PVDD and PVEE, and the light emitting element is controlled by the current to emit light. In addition, the data signal stored in the N1 node controls the source-drain current of M3, that is, the current on the path, thereby controlling the light emitting brightness of the light emitting element. In addition, the pixel circuit has a PWM drive mode. In the PWM drive mode, in the light-emitting stage t3, the light-emitting control signal EM will set the corresponding number of pulses according to the required light-emitting brightness, that is, it will form multiple low-level pulses, thereby realizing PWM pulse control of the brightness of the light-emitting element, thereby cooperating with the data signal Vdata to realize the adjustment of the brightness of the light-emitting element.

[0028] However, for transistor M1, there is a coupling capacitor, and the light-emitting control signal EM connected to the gate will affect the voltage of the N2 node due to the existence of the coupling capacitor. Specifically, during the time period when the Emit signal of the light-emitting stage t3 is at a high level, transistors M1 and M6 are both turned off, and due to the existence of the coupling capacitor, the voltage of the N2 node will be pulled up by the high-level Emit signal, and the N2 node with a pulled-up voltage will cause the charge to flow from the N2 node to the N3 node; during the time period when the Emit signal of the light-emitting stage t3 is at a low level, transistors M1 and M6 are both turned on, and a path is formed between the two power supply terminals PVDD and PVEE, and the excess charge of the N3 node will flow to the N4 node through the turned-on transistor M4. In the PWM driving mode, since there are multiple pulse signals in the light control signal Emit in one display frame, the Emit signal will have a low-level pulse, that is, there will be multiple processes of jumping from a high level to a low level. In each process of jumping from a high level to a low level, the voltage of the N4 node will continue to increase due to the influence of the capacitive coupling of the M1 transistor, and finally reach the start-up voltage of the light-emitting element 20, so that the light-emitting element 20 emits light. From the overall point of view, the N2 node, which is pulled up due to the influence of the coupling capacitor during the high-level period of the Emit signal, will cause the abnormal light emission of the light-emitting element 20, and will make the light-emitting brightness of the light-emitting element 20 in this display frame brighter. In addition, in the low-grayscale display frame, since the light-emitting brightness of the light-emitting element itself is not high, the increase in brightness caused by the high-level Emit signal will be more obvious than that of the high-grayscale display frame, and the low-grayscale display brightness will be distorted, resulting in poor color brightness uniformity of the display screen.

[0029] In view of the above technical problem, an embodiment of the present invention provides a display panel. Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 4 yes Figure 3 The schematic diagram of the structure of the pixel circuit and the light-emitting element in the display panel is shown. Figure 5 yes Figure 4 The schematic diagram of the partial layout structure of the pixel circuit shown in FIG. Figure 6 yes Figure 4 The driving timing diagram of the pixel circuit shown in the figure first refers to Figure 3 and Figure 4 The display panel includes a plurality of pixel circuits 10 and a plurality of light-emitting elements 20. The pixel circuits 10 are electrically connected to the light-emitting elements 20 for driving the light-emitting elements 20 to emit light. The pixel circuits 10 include a driving transistor T3, a first light-emitting control transistor T1 and a third light-emitting control transistor T6. The first light-emitting control transistor T1, the driving transistor T3, the third light-emitting control transistor T6 and the light-emitting element 20 are connected in series in sequence to a first power signal terminal PVDD and a second power signal terminal PVEE.

[0030] refer to Figure 4 and Figure 5 The pixel circuit 10 further includes a semiconductor pattern 11, a first light-emitting control signal line 12 and a second light-emitting control signal line 13. The semiconductor pattern 11 is formed by extending the semiconductor wiring. The first light-emitting control signal line 12 and the second light-emitting control signal line 13 extend in parallel. The first light-emitting control signal line 12 and the second light-emitting control signal line 13 overlap with the semiconductor pattern 11 respectively, and the overlapping parts constitute the first light-emitting control transistor T1 and the third light-emitting control transistor T6 respectively. Figure 6 , wherein the first light-emitting control signal line 12 is used to transmit the first light-emitting control signal EmitA, the second light-emitting control signal line 13 is used to transmit the second light-emitting control signal EmitB, and the pulse change frequency of the first light-emitting control signal EmitA is less than the pulse change frequency of the second light-emitting control signal EmitB.

[0031] Among them, the pixel circuit 10 is responsible for providing a driving current to the light-emitting element 20, so as to drive the light-emitting element 20 to emit light. In this process, the first light-emitting control transistor T1 and the third light-emitting control transistor T6 are responsible for controlling the light-emitting element 20 to emit light. They are connected in series with the light-emitting element 20 between the first power signal terminal PVDD and the second power signal terminal PVEE. When the two light-emitting control transistors are turned on, a path is formed between the first power signal terminal PVDD and the second power signal terminal PVEE, and the light-emitting element 20 located in the path emits light. For the entire display panel, each light-emitting element 20 is controlled to emit light by its corresponding pixel circuit 10, and light-emitting elements 20 of different colors can achieve color matching, so as to present a preset display screen in one display cycle.

[0032] In addition, the semiconductor pattern 11 refers to a wiring pattern made of semiconductor material, some of which can be used as wiring to transmit signals, and some of which can be used as active layers to form transistors by overlapping with signal lines, and the transmission of signals in the wiring pattern can be controlled by control signals on the signal lines. Figure 4 and Figure 5, the semiconductor pattern 11 can be understood as forming a semiconductor routing connecting the first power signal terminal PVDD and the second power signal terminal PVEE, wherein the first light-emitting control signal line 12 and the second light-emitting control signal line 13 respectively overlap with the semiconductor pattern 11 in projection, thereby forming a first light-emitting control transistor T1 and a third light-emitting control transistor T6, which are responsible for controlling the on-off of the path between the first power signal terminal PVDD and the second power signal terminal PVEE. It can be understood by those skilled in the art that an insulating layer is provided between the first light-emitting control signal line 12 and the second light-emitting control signal line 13 and the semiconductor pattern 11, and in the region where their projections overlap, the signals on the two light-emitting control signal lines will form an electric field, changing the carrier distribution in the semiconductor material in the semiconductor pattern 11, thereby changing its conductive properties and realizing on-off control. In other words, the first light-emitting control signal line 12 and the second light-emitting control signal line 13 actually constitute the first light-emitting control transistor T1 and the third light-emitting control transistor T6 together with the semiconductor pattern 11. The light-emitting control signals on the two light-emitting control signal lines can control the on or off state of the light-emitting control transistors, thereby realizing the on and off of the path between the first power signal terminal PVDD and the second power signal terminal PVEE, and controlling whether the light-emitting element 20 emits light or not.

[0033] In the embodiment of the present invention, two first light-emitting control signal lines 12 and second light-emitting control signal lines 13 are provided, the purpose of which is to control the first light-emitting control transistor T1 and the third light-emitting control transistor T6 respectively. Specifically, the first light-emitting control signal EmitA is transmitted on the first light-emitting control signal line 12, and the second light-emitting control signal EmintB is transmitted on the second light-emitting control signal line 13, and the pulse change frequency of the first light-emitting control signal EmitA is less than the pulse change frequency of the second light-emitting control signal EmitB, which is to control the conduction frequency of the first light-emitting control transistor T1 to be lower than the conduction frequency of the third light-emitting control transistor T6. As described in the background technology part, since there is a certain coupling capacitance on the first light-emitting control transistor T1, when the first light-emitting control signal EmitA produces a pulse change, the voltage of the node N2 between the first light-emitting control transistor T1 and the driving transistor T3 will be affected by the coupling effect of the first light-emitting control signal EmitA and change, and this change process will further affect the voltage of the node N4, i.e., the anode of the light-emitting element, and this influence will occur once in each pulse cycle. Based on this, in the embodiment of the present invention, the conduction frequency of the first light-emitting control transistor T1 is controlled to be lower than the conduction frequency of the third light-emitting control transistor T6, which is actually to reduce the coupling effect of the first light-emitting control signal EmitA received by the gate of the first light-emitting control transistor T1, thereby avoiding the N2 node being coupled by the first light-emitting control signal EmitA, thereby affecting the voltage of the N4 node, and preventing the light-emitting element 20 from being abnormally lit.

[0034] The above technical solution is achieved by setting a semiconductor pattern, a first light-emitting control signal line and a second light-emitting control signal line in a pixel circuit, wherein the semiconductor pattern is formed by extending a semiconductor routing line, the first light-emitting control signal line and the second light-emitting control signal line extend in parallel, the first light-emitting control signal line and the second light-emitting control signal line overlap with the projection of the semiconductor pattern respectively, and the overlapping parts constitute a first light-emitting control transistor and a second light-emitting control transistor respectively; the first light-emitting control signal line is used to transmit a first light-emitting control signal, and the second light-emitting control signal line is used to transmit a second light-emitting control signal, and the pulse change frequency of the first light-emitting control signal is less than the pulse change frequency of the second light-emitting control signal, which can reduce the voltage of the node between the first light-emitting control transistor and the driving transistor from being affected by the coupling effect of the first light-emitting control signal EmitA, thereby avoiding the anode of the light-emitting element from being affected by the voltage change of the node, preventing the light-emitting element from abnormally emitting light, and improving the color brightness uniformity of the organic light-emitting display panel at low grayscale under the PWM driving mode.

[0035] Continue to refer Figure 6 In an optional embodiment, the operation process of the pixel circuit includes multiple display cycles T; in one display cycle T, the first light-emitting control signal EmitA includes an invalid pulse (the example in the figure is a high-level pulse), and the second light-emitting control signal EmitB includes at least two invalid pulses (the example in the figure is a high-level pulse); wherein the first light-emitting control transistor T1 is turned off by the invalid pulse of the first light-emitting control signal EmitA, and the third light-emitting control transistor T6 is turned off by the invalid pulse of the second light-emitting control signal EmitB.

[0036] One display cycle means one display frame, and in one display cycle, the display panel displays one picture. In this embodiment, the first light-emitting control signal EmitA has one invalid pulse, and the second light-emitting control signal EmitB has at least two invalid pulses, which means that in this display frame, the first light-emitting control signal EmitA switches from a high level to a low level only once, thereby controlling the first light-emitting control signal EmitA to couple the N2 node only once in one display frame. For example, Figure 4As shown, the first light-emitting control transistor T1 and the third light-emitting control transistor T6 can be selected as P-type channel transistors, and correspondingly, the effective pulses of the first light-emitting control signal EmitA and the second light-emitting control signal EmitB are high-level pulses, and the invalid pulses are low-level pulses. In the high-level time period of the first light-emitting control signal EmitA, the first light-emitting control transistor T1 is turned off, and the pixel circuit can set the gate reset stage t1 and the data writing stage t2; in the low-level time period of the first light-emitting control signal EmitA, the first light-emitting control transistor T1 is turned on, and the pixel circuit can set the light-emitting stage t3, and in the light-emitting stage t3, the second light-emitting control signal EmitB can be set to have an effective pulse, that is, a low-level pulse, to control the third light-emitting control transistor T6 to turn on, to achieve the conduction of the path between the first power signal terminal PVDD and the second power signal terminal PVEE, and to control the light-emitting element 20 to emit light. Of course, considering the PWM driving mode, the number of effective pulses of the second light-emitting control signal EmitB can be set according to the light-emitting brightness requirement of the current display frame. Since the first light-emitting control signal EmitA has only one invalid pulse, i.e., a high-level stage, there is only one process of switching from a high level to a low level, and the N2 node, the N3 node, and the N4 node are only affected once by the coupling capacitance of the first light-emitting control transistor T1. Therefore, on the basis of realizing the PWM driving mode to drive the light-emitting element to emit light, the influence of the coupling capacitance of the first light-emitting control transistor T1 can be effectively reduced, thereby avoiding abnormal light emission of the light-emitting element 20 and improving the color brightness uniformity of the display panel.

[0037] Continue to refer Figure 5 Specifically, the semiconductor pattern 11 includes a central extension portion 111, a first extension portion 112 and a second extension portion 113; the first light-emitting control signal line 12 and the second light-emitting control signal line 13 extend in parallel along the first direction X, the first extension portion 112 and the second extension portion 113 both extend along the second direction Y, and the first direction X intersects with the second direction Y; the central extension portion 111 is in a "X" shape, and is used to form a driving transistor T3; the first light-emitting control signal line 12 and the first extension portion 112 have a projection overlap, and form a first light-emitting control transistor T1; the second light-emitting control signal line 13 and the second extension portion 113 have a projection overlap, and form a third light-emitting control transistor T6; the first extension portion 112 and the second extension portion 113 are respectively located on both sides of the central extension portion 111 in the second direction Y, and are respectively connected to the two ends of the central extension portion 111.

[0038] Figure 7 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, with reference to Figure 7The display panel also includes a substrate 100 and a display function layer 200; a plurality of pixel circuits 10 and a plurality of light-emitting elements 20 are formed in the display function layer 200; the display function layer 200 includes a semiconductor layer 210 and a first conductive layer 220; in the thickness direction, the semiconductor layer 210 is located between the first conductive layer 220 and the substrate 100; the semiconductor pattern 11 is located in the semiconductor layer 210, and the first light-emitting control signal line 12 and the second light-emitting control signal line 13 are located in the first conductive layer 210.

[0039] Among them, the central extension portion 111, the first extension portion 112 and the second extension portion 113 are all used as active layers of transistors, and are divided according to the different transistors in the pixel circuits they constitute. The central extension portion 111 is used to constitute the driving transistor T3, which can be formed by arranging a projection overlapping electrode plate (not shown in the figure) on the top as a gate to constitute the driving transistor T3. The central extension portion 111 is in a "X" shape, the purpose is to increase its aspect ratio, thereby increasing its current driving capability. The first extension portion 112 and the second extension portion 113 are respectively used as active layers of the first light-emitting control transistor T1 and the third light-emitting control transistor T6, and are respectively arranged on the top with a projection overlapping first light-emitting control signal line 12 and a second light-emitting control signal line 13 as gates to constitute the first light-emitting control transistor T1 and the third light-emitting control transistor T6.

[0040] It can be understood that since a plurality of pixel circuits 10 and a plurality of light emitting elements 20 are provided in the display panel, they are generally arranged in an array in rows and columns, such as Figure 5 As shown, the first direction X can be understood as the row direction, and the second direction Y can be understood as the column direction. For the first light-emitting control signal line 12 and the second light-emitting control signal line 13 extending in parallel along the first direction X, i.e., the row direction, they need to synchronously control the pixel circuits 10 of the entire row, that is, they need to overlap with the projection of the semiconductor pattern 11 in the pixel circuits 10 of the same row, and form a first light-emitting control transistor T1 and a third light-emitting control transistor T6 in each pixel circuit 10, respectively. In the embodiment of the present invention, based on the first light-emitting control signal line 12 and the second light-emitting control signal line 13 extending in parallel along the first direction X, i.e., the row direction, the first extension part 112 and the second extension part 113 are respectively arranged on both sides of the central extension part 111 in the second direction Y, i.e., the column direction, so that the first light-emitting control signal line 12 and the first extension part 112 overlap in projection to form the first light-emitting control transistor T1, and the second light-emitting control signal line 13 and the second light-emitting control signal line 13 overlap in projection to form the third light-emitting control transistor T6, the first light-emitting control signal line 12 and the second extension part 113 overlap in projection, and the second light-emitting control signal line 13 and the first extension part 112 overlap in projection. At the same time, the region between the first light-emitting control signal line 112 and the second light-emitting control signal line 113 can be provided with an electrode of the driving transistor T3.

[0041] It should be noted that, since the pixel circuit is also designed with a gate reset transistor T5, a data write transistor T2, a threshold compensation transistor T4 and an anode reset transistor T7, these transistors all need to be provided with corresponding control signal lines for conduction control. It can be understood that in the semiconductor pattern 11 provided in the embodiment of the present invention, a gate reset control signal line, a data write control signal line, a threshold compensation control signal line and an anode reset signal line extending along the first direction X can be provided correspondingly, and the semiconductor pattern 11 is projected and overlapped to form corresponding transistors, so as to realize the pixel circuit provided in the embodiment of the present invention or other feasible pixel circuits. In addition, the specific setting method of the above-mentioned control signal line can be to set a second conductive layer, a third conductive layer, etc. in the display function layer 200 to meet the wiring requirements of the control signal line, and the embodiment of the present invention does not limit this. In addition, in the layout design of the display panel, in addition to designing the control signal lines of the transistors, it is also necessary to provide the pixel circuit with a first power supply voltage signal PVDD, a second power supply voltage signal PVEE, a gate reset signal Vref1 and an anode reset signal Vref2, so the corresponding signal lines also need to be designed. Therefore, in the display function layer 200, the second conductive layer, the third conductive layer or even the fourth conductive layer can also be set to arrange the above-mentioned control signal lines, power signal lines, reset signal lines, etc., and the embodiments of the present invention do not limit this.

[0042] It should also be added that in the embodiments of the present invention, the specific design of the pixel circuit is not unique. Figure 4 The pixel circuit shown is only one embodiment of the present invention, in which except for the gate reset transistor T5 and the threshold compensation transistor T4 which are N-type channel transistors, the other transistors are P-type channel transistors, wherein the semiconductor pattern 11 can be a low temperature polysilicon (LTPS) semiconductor material, which is used to prepare P-type channel transistors. For the N-type channel gate reset transistor T5 and the threshold compensation transistor T4, their function is to prevent leakage current from causing changes in the voltage of the N1 node, thereby affecting the brightness of the light-emitting element during the light-emitting stage. Specifically, the two N-type channel transistors can be formed by setting another semiconductor layer in the display function layer 200, that is, using indium gallium zinc oxide (InGaZnO) semiconductor material to form another semiconductor pattern, and also by setting the corresponding control signal lines to overlap in projection. In addition, as Figure 4In the figure, the gate of the driving transistor of the pixel circuit, i.e., the N1 node, is exemplarily connected to the capacitor Cst, and another capacitor C is also provided to connect the N1 node and the gate of the data writing transistor T2 respectively, so as to stabilize the voltage of the N1 node through the control signal written into the gate of the data writing transistor T2, and avoid leakage current causing changes in the voltage of the N1 node, thereby affecting the luminous brightness.

[0043] Figure 8 is another schematic diagram of the layout structure of the pixel circuit provided by the embodiment of the present invention, referring to Figure 8 Optionally, in the first direction X, two adjacent semiconductor patterns 11 are axially symmetrically distributed. Further optionally, the first extension portions 112 in two adjacent semiconductor patterns 11 in the first direction X are connected.

[0044] refer to Figure 4 The first light emitting control transistor T1 formed by the first extension portion 112 is connected to the driving transistor T3 and the first power signal terminal PVDD. Figure 8 In the semiconductor pattern 11 shown, one end of the first extension portion 112 is connected to the central extension portion 111, and the other end needs to be used as the first power signal terminal PVDD and connected to the first power signal line (not shown in the figure). It can be understood by those skilled in the art that the interconnected signal lines and the semiconductor pattern 11 are usually arranged in different film layers, and generally need to be connected by punching. Based on this, in this embodiment, the two adjacent semiconductor patterns 11 in the first direction X, i.e., the row direction, are arranged to be axially symmetrically distributed, so that the first extension portions 112 in the two semiconductor patterns 11 can be adjacent, and then the two can be connected into one. When connecting to the first power signal line, only one through hole needs to be punched to achieve the connection, which reduces the number of punching holes, helps to save the layout design area of ​​the pixel circuit, and is beneficial to increase the resolution of the display panel to a certain extent.

[0045] Fig. 9 is another schematic diagram of a layout structure of a pixel circuit provided by an embodiment of the present invention, with reference to Fig. 9 In an optional embodiment, two adjacent semiconductor patterns 11 in the second direction Y are axially symmetrically distributed.

[0046] Continue to refer Fig. 9Further, two semiconductor patterns 11 adjacent to each other in the second direction Y include a first semiconductor pattern 1101 and a second semiconductor pattern 1102; in the first light-emitting control signal line 12 and the second light-emitting control signal line 13 respectively overlapping with the projection of the first semiconductor pattern 1101, the second light-emitting control signal line 13 is located on the side of the first light-emitting control signal line 12 away from the second semiconductor pattern 1102 in the second direction Y; in the first light-emitting control signal line 12 and the second light-emitting control signal line 13 respectively overlapping with the projection of the second semiconductor pattern 1102, the second light-emitting control signal line 13 is located on the side of the first light-emitting control signal line 12 away from the first semiconductor pattern 1101 in the second direction Y.

[0047] As described above, in the embodiment of the present invention, the first light-emitting control signal line 12 and the second light-emitting control signal line 13 respectively provide the first light-emitting control signal EmitA and the second light-emitting control signal EmitB, and the pulse change frequencies of the two light-emitting control signals are not the same. In this embodiment, in the second direction Y, i.e., the column direction, two adjacent semiconductor patterns 11 are arranged to be axially symmetrically distributed, and the essence is to arrange the two first extensions 112 in the two semiconductor patterns 11 between the two second extensions 113 in the column direction. Thus, the two first light-emitting control signal lines 12 corresponding to the two adjacent pixel circuits 10 in the column direction can be arranged between the two second light-emitting control signal lines 13. In other words, it can be avoided that the first light-emitting control signal lines 12 and the second light-emitting control signal lines 13 are completely alternately arranged in the column direction, and it can be avoided that each first light-emitting control signal line 12 is adjacent to two second light-emitting control signal lines 13, and each second light-emitting control signal line 13 is adjacent to two first light-emitting control signal lines 12. To a certain extent, it can be avoided that the first light-emitting control signal lines 12 and the second light-emitting control signal lines 13 with different pulse change frequencies are interfered with each other, and the pixel circuit is driven normally.

[0048] Fig.10 is another schematic diagram of a layout structure of a pixel circuit provided by an embodiment of the present invention, with reference to Fig.10 In an optional embodiment, two adjacent semiconductor patterns 11 in the second direction Y are centrally symmetrically distributed.

[0049] Continue to refer Fig.10 Furthermore, two semiconductor patterns 11 adjacent to each other in the second direction Y overlap with the projection of the same first light emitting control signal line 12 and form a first light emitting control transistor T1 respectively.

[0050] Continue to refer Fig.10Specifically, two adjacent semiconductor patterns 11 in the second direction Y include a first semiconductor pattern 1101 and a second semiconductor pattern 1102; in the first direction X, the second extension portion 113 in the first semiconductor pattern 1101 is located between the second extension portion 113 and the first extension portion 112 in the second semiconductor pattern 1102, and the second extension portion 113 in the second semiconductor pattern 1102 is located between the first extension portion 112 and the second extension portion 113 in the first semiconductor pattern 1101; in the second direction Y, the first extension portion 112 in the first semiconductor pattern 1101 and the first extension portion 112 in the second semiconductor pattern 1102 are located between the second extension portion 113 in the first semiconductor pattern 1101 and the second extension portion 113 in the second semiconductor pattern 1102.

[0051] In this embodiment, in the second direction Y, i.e., the column direction, two adjacent semiconductor patterns 11 are arranged to be centrally symmetrically distributed, and the essence is also to arrange the two first extensions 112 in the two semiconductor patterns 11 between the two second extensions 113 in the column direction. Furthermore, the two first extensions 112 can be located at the same position in the column direction, or in other words, they can overlap with the same signal line extending in the row direction. In the specific design, the first semiconductor pattern 1101 and the second semiconductor pattern 1102 can be staggered with each other, and the two first extensions 112 therein are in a cross-finger shape. Thus, the two first extensions 112 in the two adjacent semiconductor patterns 11 in the column direction can be overlapped by setting a first light-emitting control signal line 12, and a first light-emitting control transistor T1 is formed respectively. At this time, the two adjacent pixel circuits 10 in the column direction actually share a first light-emitting control signal line 12, and the arrangement of the two semiconductor patterns 11 in the column direction is also more compact, thereby saving the number of signal lines, improving the area utilization of the display panel, and helping to improve the resolution of the display panel.

[0052] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.11 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Figure 1 As shown, the display device includes the display panel 1 described in any of the above embodiments. Therefore, the display device provided in the embodiment of the present invention has the corresponding beneficial effects in the above embodiments, which will not be repeated here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, which is not limited in the embodiment of the present invention.

[0053] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: It comprises a plurality of pixel circuits and a plurality of light emitting elements, wherein the pixel circuits are electrically connected to the light emitting elements and are used to drive the light emitting elements to emit light; The pixel circuit comprises a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving transistor, the second light-emitting control transistor and the light-emitting element are sequentially connected in series to a first power signal terminal and a second power signal terminal; The pixel circuit further includes a semiconductor pattern, a first light-emitting control signal line and a second light-emitting control signal line, the semiconductor pattern is formed by extending a semiconductor wiring, the first light-emitting control signal line and the second light-emitting control signal line extend in parallel, the first light-emitting control signal line and the second light-emitting control signal line overlap with the semiconductor pattern respectively in projection, and the overlapping parts constitute the first light-emitting control transistor and the second light-emitting control transistor respectively; The first light-emitting control signal line is used to transmit a first light-emitting control signal, the second light-emitting control signal line is used to transmit a second light-emitting control signal, and a pulse change frequency of the first light-emitting control signal is less than a pulse change frequency of the second light-emitting control signal.

2. The display panel according to claim 1, characterized in that: The semiconductor pattern includes a central extension, a first extension, and a second extension; The first light-emitting control signal line and the second light-emitting control signal line extend in parallel along a first direction, the first extension portion and the second extension portion both extend along a second direction, and the first direction intersects the second direction; The central extension portion is in a "X" shape and is used to form the driving transistor; The first light emission control signal line overlaps with the first extension portion in projection, and forms the first light emission control transistor; The second light emission control signal line and the second extension portion have a projection overlap, and form the second light emission control transistor; The first extension portion and the second extension portion are respectively located at two sides of the central extension portion in the second direction, and are respectively connected to two ends of the central extension portion.

3. The display panel according to claim 2, characterized in that: In the first direction, two adjacent semiconductor patterns are distributed in an axisymmetric manner.

4. The display panel according to claim 3, characterized in that: The first extending portions in two adjacent semiconductor patterns in the first direction are connected.

5. The display panel according to claim 2, characterized in that: The two semiconductor patterns adjacent to each other in the second direction are axially symmetrically distributed.

6. The display panel according to claim 5, characterized in that: The two semiconductor patterns adjacent to each other in the second direction include a first semiconductor pattern and a second semiconductor pattern; Of the first light-emitting control signal line and the second light-emitting control signal line respectively overlapping with the projection of the first semiconductor pattern, the second light-emitting control signal line is located on a side of the first light-emitting control signal line away from the second semiconductor pattern in the second direction; Of the first light emitting control signal line and the second light emitting control signal line respectively overlapping with the projection of the second semiconductor pattern, the second light emitting control signal line is located on a side of the first light emitting control signal line away from the first semiconductor pattern in the second direction.

7. The display panel according to claim 2, characterized in that: The two semiconductor patterns adjacent to each other in the second direction are centrally symmetrically distributed.

8. The display panel according to claim 7, characterized in that: Two semiconductor patterns adjacent to each other in the second direction overlap with the same first light emission control signal line by projection, and form a first light emission control transistor respectively.

9. The display panel according to claim 7, characterized in that: The two semiconductor patterns adjacent to each other in the second direction include a first semiconductor pattern and a second semiconductor pattern; In the first direction, the second extension portion in the first semiconductor pattern is located between the second extension portion and the first extension portion in the second semiconductor pattern, and the second extension portion in the second semiconductor pattern is located between the first extension portion and the second extension portion in the first semiconductor pattern; In the second direction, the first extending portion in the first semiconductor pattern and the first extending portion in the second semiconductor pattern are located between the second extending portion in the first semiconductor pattern and the second extending portion in the second semiconductor pattern.

10. The display panel according to claim 1, characterized in that: The display panel further comprises a substrate and a display function layer; a plurality of the pixel circuits and a plurality of the light-emitting elements are formed in the display function layer; The display function layer includes a semiconductor layer and a first conductive layer; in the thickness direction, the semiconductor layer is located between the first conductive layer and the substrate; The semiconductor pattern is located in the semiconductor layer, and the first light emission control signal line and the second light emission control signal line are located in the first conductive layer.

11. The display panel according to claim 1, characterized in that: The working process of the pixel circuit includes a plurality of display cycles; in one display cycle, the first light emitting control signal includes one invalid pulse, and the second light emitting control signal includes at least two invalid pulses; The first light emitting control transistor is turned off by the invalid pulse of the first light emitting control signal, and the second light emitting control transistor is turned off by the invalid pulse of the second light emitting control signal.

12. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-11.

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