Indium arsenide quantum dot single-photon avalanche diode and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductor technologies, and discloses an indium arsenide quantum dot single-photon avalanche diode and a manufacturing method thereof. Comprising a substrate layer, a buffer layer, an N-type indium phosphide doping layer, an intrinsic indium gallium arsenic absorption layer, an N-type indium gallium arsenic phosphorus lightly-doped gradient layer, an N-type indium phosphide lightly-doped charge layer, an intrinsic indium arsenide quantum dot avalanche layer and a P-type indium phosphide lightly-doped contact layer which are stacked in sequence. The quantum dot size of the intrinsic indium arsenide quantum dot avalanche layer ranges from 2 nanometers to 10 nanometers. According to the invention, the response speed of the diode can be improved on the basis of reducing excessive noise and improving the bandwidth of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and in particular to an indium arsenide quantum dot single-photon avalanche diode and a method for manufacturing the same. Background Art

[0002] Single-photon avalanche photodetectors (SPADs) are a type of semiconductor photodetector that utilizes the carrier avalanche multiplication effect in semiconductors. When a large reverse bias voltage is applied to the device, the incidence of fewer photons or even a single photon can trigger the avalanche multiplication process, thereby causing a change in the photocurrent of the device on a macroscopic scale, and has extremely high sensitivity. Avalanche accumulation time is a key technical means to improve the gain-bandwidth product and avalanche noise of SPADs. Conventional SPADs usually use InP and InAlAs layers as avalanche regions, and their thickness is usually in the range of 0.3-1μm, resulting in a small bandwidth of the device. In order to further improve the performance of SPADs, some researchers have proposed the use of AlGaAsSb / InAs multiple quantum well superlattice structures as avalanche layers.

[0003] However, although the AlGaAsSb / InAs multiple quantum well superlattice structure can achieve lower noise by utilizing the fact that the conduction band discontinuity at the heterojunction boundary is much larger than the valence band discontinuity, the multiple quantum well structure is formed by the alternating growth of two different semiconductor materials, forming a potential well between them, which confines electrons or holes to a certain energy range, resulting in the movement direction and energy distribution of carriers being restricted, triggering a slow carrier avalanche process, and slow response speed. Summary of the invention

[0004] The present application provides an indium arsenide quantum dot single-photon avalanche diode and a method for manufacturing the same, which can improve the response speed of the diode while reducing excess noise and increasing the bandwidth of the device.

[0005] In a first aspect, an embodiment of the present application provides an indium arsenide quantum dot single-photon avalanche diode, comprising a substrate layer, a buffer layer, an N-type indium phosphide doped layer, an intrinsic indium gallium arsenic absorption layer, an N-type indium gallium arsenic phosphide lightly doped gradient layer, an N-type indium phosphide lightly doped charge layer, an intrinsic indium arsenide quantum dot avalanche layer, and a P-type indium phosphide lightly doped contact layer stacked in sequence; The quantum dot size of the intrinsic InAs quantum dot avalanche layer ranges from 2 nm to 10 nm; The lengths of the substrate layer, the buffer layer and the N-type indium phosphide doped layer are all first preset lengths; The lengths of the intrinsic InGaAs absorption layer, the N-type InGaAsP lightly doped gradient layer, the N-type InP lightly doped charge layer, the intrinsic InAs quantum dot avalanche layer and the P-type InP lightly doped contact layer are all the second preset length; The first preset length is greater than the second preset length; The passivation layer covers the N-type indium phosphide doped layer and the second mesa of a preset length; The N-type electrode is connected to the N-type indium phosphide doped layer through the passivation layer; The P-type electrode passes through the passivation layer and is connected to the P-type indium phosphide lightly doped contact layer.

[0006] Furthermore, the quantum dot spacing of the intrinsic InAs quantum dot avalanche layer ranges from 3 nanometers to 10 nanometers.

[0007] Furthermore, the thickness of the intrinsic InAs quantum dot avalanche layer ranges from 500 nanometers to 2000 nanometers.

[0008] Further, the thickness of the quantum dot layer in the intrinsic indium arsenide quantum dot avalanche layer ranges from 10 nanometers to 50 nanometers; The thickness of the spacer layer ranges from 20 nm to 100 nm; The number of periods ranges from 5 to 50, and the thickness of a single period ranges from 30 nm to 150 nm.

[0009] Furthermore, the buffer layer includes a low-temperature germanium layer, a high-temperature germanium layer, a gallium arsenide buffer layer and an indium phosphide buffer layer stacked in sequence; the substrate layer is a silicon substrate; the silicon substrate is a non-cut silicon substrate, a 6-degree beveled silicon substrate, a silicon-on-insulator substrate, a fully depleted silicon-on-insulator substrate, a sapphire substrate or a silicon-on-sapphire substrate.

[0010] Further, the buffer layer includes an indium phosphide layer on an insulator and an indium phosphide layer stacked in sequence; The substrate layer is an indium phosphide substrate on sapphire.

[0011] Further, the buffer layer includes a gallium arsenide on insulator layer, a gallium arsenide layer and an indium phosphide buffer layer stacked in sequence; The substrate layer is a gallium arsenide substrate on sapphire.

[0012] Further, the buffer layer includes a germanium-on-insulator layer, a germanium layer, a gallium arsenide buffer layer and an indium phosphide buffer layer stacked in sequence; The substrate layer is a germanium substrate on sapphire.

[0013] Furthermore, the buffer layer and the substrate layer are both N-type heavily doped structures.

[0014] Further, the thickness of the GaAs buffer layer ranges from 200 nanometers to 1000 nanometers; The thickness of the indium phosphide buffer layer ranges from 1000 nanometers to 1500 nanometers; the thickness of the low-temperature germanium layer ranges from 100 nanometers to 500 nanometers; and the thickness of the high-temperature germanium layer ranges from 1000 nanometers to 1500 nanometers.

[0015] Furthermore, the thickness of the N-type indium phosphide doped layer ranges from 200 nanometers to 1000 nanometers.

[0016] Furthermore, the thickness of the intrinsic InGaAs absorption layer ranges from 1000 nanometers to 1500 nanometers.

[0017] Furthermore, the thickness of the N-type InGaAsP lightly doped gradient layer and the N-type InP lightly doped charge layer are both in the range of 50 nanometers to 100 nanometers.

[0018] Furthermore, the thickness of the P-type InP lightly doped contact layer ranges from 200 nanometers to 1000 nanometers.

[0019] In a second aspect, an embodiment of the present application provides a method for manufacturing an indium arsenide quantum dot single photon avalanche diode, comprising: providing a substrate layer of a first predetermined length; A buffer layer, an N-type indium phosphide doping layer, an intrinsic indium gallium arsenic absorption layer, an N-type indium gallium arsenic phosphide lightly doped gradient layer, an N-type indium phosphide lightly doped charge layer, an intrinsic indium arsenide quantum dot avalanche layer with a quantum dot size ranging from 2 nanometers to 10 nanometers, and a P-type indium phosphide lightly doped contact layer are sequentially stacked on the substrate layer; The length of the intrinsic InGaAs absorption layer, the N-type InGaAsP lightly doped gradient layer, the N-type InP lightly doped charge layer, the intrinsic InAs quantum dot avalanche layer and the P-type InP lightly doped contact layer are etched to a second preset length to obtain a mesa of the second preset length; wherein the first preset length is greater than the second preset length; A passivation layer is covered on the N-type indium phosphide doped layer and the mesa of the second preset length; Allowing the N-type electrode to pass through the passivation layer and connect to the N-type indium phosphide doped layer; The P-type electrode is connected to the P-type indium phosphide lightly doped contact layer through the passivation layer.

[0020] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects: An indium arsenide quantum dot single-photon avalanche diode provided in an embodiment of the present application forms an InAs / InP quantum dot structure by sequentially stacking an N-type indium phosphide lightly doped charge layer, an intrinsic indium arsenide quantum dot avalanche layer, and a P-type indium phosphide lightly doped contact layer. First, the InAs / InP quantum dot material used in the present application has a high carrier collision ionization coefficient, which can enhance the collision ionization rate of the avalanche zone, reduce excess noise, and improve the bandwidth of the device; secondly, unlike the quantum well structure of the prior art, the quantum dot of the present application is a nanoscale semiconductor particle with a discrete energy level structure, and its avalanche multiplication begins with the excitation of carriers inside the quantum dot: when the quantum dot absorbs photons or obtains energy from the outside, the electrons or holes in the quantum dot are excited to a higher energy level. These excited carriers will interact with the medium or other quantum dots around the quantum dot under the action of a high electric field, resulting in the generation of new electron-hole pairs. Due to the discreteness of the quantum dots, the avalanche multiplication process is more like a quantum dot generating avalanches independently, and then influencing each other, thereby improving the response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A structural diagram of an indium arsenide quantum dot single-photon avalanche diode provided in one embodiment of the present application.

[0022] Figure 2 A flow chart of a method for manufacturing an indium arsenide quantum dot single-photon avalanche diode provided in one embodiment of the present application.

[0023] Figure 3 A schematic diagram of a separated absorption graded charge multiplication (SAGCM) structure provided in one embodiment of the present application.

[0024] Figure 4 A schematic diagram of a passivation layer coverage area provided in an embodiment of the present application.

[0025] Description of reference numerals: 101. substrate layer; 102. buffer layer; 103. N-type indium phosphide doped layer; 104. intrinsic indium gallium arsenic absorption layer; 105. N-type indium gallium arsenic phosphide lightly doped gradient layer; 106. N-type indium phosphide lightly doped charge layer; 107. intrinsic indium arsenide quantum dot avalanche layer; 108. P-type indium phosphide lightly doped contact layer; 201. N-type electrode; 202. P-type electrode. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0027] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0028] See also Figure 1 , the embodiment of the present application provides an indium arsenide quantum dot single photon avalanche diode, comprising: The substrate layer 101, the buffer layer 102, the N-type InP doped layer 103, the intrinsic InGaAs absorption layer 104, the N-type InGaAsP lightly doped gradient layer 105, the N-type InP lightly doped charge layer 106, the intrinsic InAs quantum dot avalanche layer 107 and the P-type InP lightly doped contact layer 108 are stacked in sequence.

[0029] The thickness of the N-type InP doped layer 103 is in a range of 200 nanometers to 1000 nanometers.

[0030] The thickness of the intrinsic InGaAs absorption layer 104 is in a range of 1000 nanometers to 1500 nanometers.

[0031] The thickness of the N-type InGaAsP lightly doped gradient layer 105 and the N-type InP lightly doped charge layer 106 are both in the range of 50 nanometers to 100 nanometers; the thickness of the P-type InP lightly doped contact layer 108 is in the range of 200 nanometers to 1000 nanometers.

[0032] The quantum dot size of the intrinsic InAs quantum dot avalanche layer 107 ranges from 2 nanometers to 10 nanometers.

[0033] Specifically, within such a quantum dot size range, the corresponding quantum dots have the best and most significant quantum confinement effect, and their energy levels are highly discretized, ensuring rapid response of the avalanche process.

[0034] The lengths of the substrate layer 101 , the buffer layer 102 and the N-type InP doped layer 103 are all first preset lengths.

[0035] The lengths of the intrinsic InGaAs absorption layer 104, the N-type InGaAsP lightly doped gradient layer 105, the N-type InP lightly doped charge layer 106, the intrinsic InAs quantum dot avalanche layer 107 and the P-type InP lightly doped contact layer 108 are all the second preset length.

[0036] The first preset length is greater than the second preset length.

[0037] The passivation layer covers the N-type InP doped layer 103 and the mesa of the second preset length.

[0038] Specifically, Figure 1As shown, an intrinsic InGaAs absorption layer 104 of a second preset length, an N-type InGaAsP lightly doped gradient layer 105, an N-type InP lightly doped charge layer 106, an intrinsic InAs quantum dot avalanche layer 107 and a P-type InP lightly doped contact layer 108 form a table on the N-type InP doped layer 103, and a passivation layer covers the upper surface and side surfaces of the table and the N-type InP doped layer 103 not covered by the table.

[0039] The N-type electrode 201 passes through the passivation layer and is connected to the N-type InP doped layer 103 .

[0040] The P-type electrode 202 passes through the passivation layer and is connected to the P-type InP lightly doped contact layer 108 .

[0041] Wherein, both the N-type electrode 201 and the P-type electrode 202 can be transparent electrodes.

[0042] The above embodiment provides an indium arsenide quantum dot single-photon avalanche diode, which forms an InAs / InP quantum dot structure by sequentially stacking an N-type indium phosphide lightly doped charge layer 106, an intrinsic indium arsenide quantum dot avalanche layer 107, and a P-type indium phosphide lightly doped contact layer 108. Firstly, the InAs / InP quantum dot material used in the present application has a high carrier collision ionization coefficient, which can enhance the collision ionization rate of the avalanche zone, reduce excess noise, and improve the bandwidth of the device; secondly, unlike the quantum well structure of the prior art, the quantum dot of the present application It is a nanoscale semiconductor particle with a discrete energy level structure. Its avalanche multiplication begins with the excitation of carriers inside the quantum dot: when the quantum dot absorbs photons or obtains energy from the outside, the electrons or holes in the quantum dot are excited to a higher energy level. These excited carriers will interact with the medium or other quantum dots around the quantum dot under the action of high electric fields, resulting in the generation of new electron-hole pairs. Due to the discreteness of quantum dots, the avalanche multiplication process is more like each quantum dot independently generates an avalanche, and then affects each other, thereby improving the response speed.

[0043] In some embodiments, the quantum dot spacing of the intrinsic InAs quantum dot avalanche layer 107 is in a range of 3 nanometers to 10 nanometers.

[0044] Specifically, quantum dots within this spacing range will not produce too many non-radiative recombination channels, which can reduce noise and increase avalanche gain, which is beneficial to improving the transport efficiency of carriers between quantum dots and further realizing efficient and rapid avalanche multiplication.

[0045] In some embodiments, the thickness of the intrinsic InAs quantum dot avalanche layer 107 ranges from 500 nanometers to 2000 nanometers.

[0046] Specifically, the intrinsic indium arsenide quantum dot avalanche layer 107 within this range can provide a sufficient avalanche multiplication region, and the carrier transit time is shorter, which can enable the single photon avalanche diode to have a faster response speed.

[0047] In some embodiments, the quantum dot layer thickness in the intrinsic indium arsenide quantum dot avalanche layer 107 ranges from 10 nanometers to 50 nanometers; the spacer layer thickness ranges from 20 nanometers to 100 nanometers; the number of periods is 5 to 50, and the thickness of a single period ranges from 30 nanometers to 150 nanometers. It can be considered that the quantum dot layer and the spacer layer constitute a period, and multiple such periods constitute the intrinsic indium arsenide quantum dot avalanche layer 107; the above-defined period thickness range helps to balance the interaction between quantum dots and the transport of carriers, so that the avalanche process can be effectively carried out in multiple periods while ensuring good optical and electrical properties.

[0048] In some embodiments, the buffer layer 102 includes a low-temperature germanium layer, a high-temperature germanium layer, a gallium arsenide buffer layer and an indium phosphide buffer layer stacked in sequence; the substrate layer 101 is a silicon substrate; the silicon substrate is a non-cornered silicon substrate, a 6-degree beveled silicon substrate, a silicon-on-insulator substrate, a fully depleted silicon-on-insulator substrate, a sapphire substrate or a silicon-on-sapphire substrate.

[0049] Among them, the thickness of the gallium arsenide buffer layer can range from 200 nanometers to 1000 nanometers; the thickness of the indium phosphide buffer layer can range from 1000 nanometers to 1500 nanometers; the thickness of the low-temperature germanium layer can range from 100 nanometers to 500 nanometers; and the thickness of the high-temperature germanium layer can range from 1000 nanometers to 1500 nanometers.

[0050] Here, low temperature and high temperature are relative concepts, usually referring to the standard growth temperature relative to a specific process step or material system. The values ​​of these temperatures will vary depending on different processes, materials and equipment.

[0051] In the present application, if the germanium layer is formed by molecular beam epitaxy, the low temperature is between 300°C and 500°C, and the high temperature is between 600°C and 900°C. If the metal organic chemical vapor deposition process is used, the low temperature is between 400°C and 600°C, and the high temperature is between 700°C and 1100°C.

[0052] Specifically, the lattice constant of the Si substrate is 5.43095 Å, the lattice constant of Ge is 5.65754 Å, the lattice constant of GaAs is 5.6419 Å, and the lattice constant of InP is about 5.8687 Å. Due to the large lattice mismatch, polarity mismatch, and thermal mismatch between Si and InP, if the InP layer is directly epitaxially grown on the Si substrate and the quantum dot avalanche photodiode is prepared using this substrate structure, the crystal quality of the InP layer will be poor. In this case, the quantum efficiency of the prepared device will be reduced, the dark count rate will increase, the detection bandwidth will be limited, and additional noise will be generated, which will affect the stability and reliability of the device. To this end, the present application introduces a low-temperature germanium layer, a high-temperature germanium layer, a gallium arsenide buffer layer and an indium phosphide buffer layer between the N-type indium phosphide doped layer 103 and the silicon substrate. The purpose is to improve the heterogeneous interface quality by introducing these buffer layers, solve the lattice mismatch, polarity mismatch and thermal mismatch problems between Si and InP, and finally obtain a high-quality N-type indium phosphide doped layer 103.

[0053] The substrate layer 101 of the present application is preferably a silicon substrate because silicon has outstanding advantages such as large wafer size, low manufacturing cost, compatibility with SiCMOS process, and easy mass production. In fact, in addition to the substrate layer 101 and the buffer layer 102 of the above-mentioned embodiment, the buffer layer 102 of the present application can also be replaced by an indium phosphide on insulator layer and an indium phosphide layer (InPOI above InP) stacked in sequence; in this case, the substrate layer 101 can be replaced by an indium phosphide substrate on sapphire (InPOS).

[0054] Furthermore, the buffer layer 102 can also be replaced by a gallium arsenide layer on an insulator, a gallium arsenide layer and an indium phosphide buffer layer stacked in sequence (that is, the low-temperature germanium layer, the high-temperature germanium layer and the gallium arsenide buffer layer are replaced by GaAsOI and GaAs, with GaAs on top); then the substrate layer 101 at this time can be a gallium arsenide substrate on sapphire.

[0055] Furthermore, the buffer layer 102 can also be replaced by a germanium on insulator layer, a germanium layer, a gallium arsenide buffer layer and an indium phosphide buffer layer stacked in sequence (that is, the low-temperature germanium layer and the high-temperature germanium layer are replaced by GOI and Ge, respectively, with Ge on the top); at this time, the substrate layer 101 can be replaced by a germanium on sapphire substrate (GOS).

[0056] Furthermore, the substrate layer 101 and the buffer layer 102 in the above-mentioned various replacement schemes can be heavily N-type doped.

[0057] See also Figure 2 Another embodiment of the present application provides a method for manufacturing an indium arsenide quantum dot single photon avalanche diode, which may specifically include the following steps: Step S1, providing a substrate layer 101 of a first preset length.

[0058] Step S2, stacking a buffer layer 102, an N-type indium phosphide doped layer 103, an intrinsic indium gallium arsenic absorption layer 104, an N-type indium gallium arsenic phosphide lightly doped gradient layer 105, an N-type indium phosphide lightly doped charge layer 106, an intrinsic indium arsenide quantum dot avalanche layer 107 with a quantum dot size ranging from 2 nanometers to 10 nanometers, and a P-type indium phosphide lightly doped contact layer 108 in sequence on the substrate layer 101.

[0059] Specifically, see Figure 3 , at this time, the length of each stacked layer is the first preset length. After the stacking is completed, a separated absorption gradient charge multiplication (SAGCM) structure on a Ge / Si substrate can be obtained.

[0060] Step S3, etching the intrinsic InGaAs absorption layer 104, the N-type InGaAsP lightly doped gradient layer 105, the N-type InP lightly doped charge layer 106, the intrinsic InAs quantum dot avalanche layer 107 and the P-type InP lightly doped contact layer 108 to a second preset length to obtain a table of the second preset length; wherein the first preset length is greater than the second preset length.

[0061] The thickness of the N-type InP doped layer 103 is in a range of 200 nanometers to 1000 nanometers.

[0062] The thickness of the intrinsic InGaAs absorption layer 104 is in a range of 1000 nanometers to 1500 nanometers.

[0063] The thickness of the N-type InGaAsP lightly doped gradient layer 105 and the N-type InP lightly doped charge layer 106 are both in the range of 50 nanometers to 100 nanometers; the thickness of the P-type InP lightly doped contact layer 108 is in the range of 200 nanometers to 1000 nanometers.

[0064] Step S4, covering the N-type InP doped layer 103 and the mesa of the second preset length with a passivation layer.

[0065] Specifically, see Figure 4 The passivation layer only covers the upper surface and the side surface of the mesa and the area of ​​the N-type indium phosphide doped layer 103 not covered by the mesa.

[0066] Step S5 , allowing the N-type electrode 201 to pass through the passivation layer and connect to the N-type InP doped layer 103 ; allowing the P-type electrode 202 to pass through the passivation layer and connect to the P-type InP lightly doped contact layer 108 .

[0067] The N-type electrode 201 and the P-type electrode 202 may both be transparent electrodes.

[0068] The specific limitations on the parameters or structures of each semiconductor layer provided in this embodiment can be found in the above embodiment of an indium arsenide quantum dot single-photon avalanche diode method, and will not be repeated here.

[0069] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An indium arsenide quantum dot single photon avalanche diode, characterized in that: It includes a substrate layer, a buffer layer, an N-type indium phosphide doped layer, an intrinsic indium gallium arsenic absorption layer, an N-type indium gallium arsenic phosphide lightly doped gradient layer, an N-type indium phosphide lightly doped charge layer, an intrinsic indium arsenide quantum dot avalanche layer and a P-type indium phosphide lightly doped contact layer stacked in sequence; The quantum dot size of the intrinsic indium arsenide quantum dot avalanche layer ranges from 2 nanometers to 10 nanometers; The lengths of the substrate layer, the buffer layer and the N-type indium phosphide doped layer are all first preset lengths; The lengths of the intrinsic InGaAs absorption layer, the N-type InGaAsP lightly doped gradient layer, the N-type InP lightly doped charge layer, the intrinsic InAs quantum dot avalanche layer and the P-type InP lightly doped contact layer are all a second preset length; The first preset length is greater than the second preset length; The passivation layer covers the N-type indium phosphide doped layer and the second mesa of the preset length; An N-type electrode passes through the passivation layer and is connected to the N-type indium phosphide doped layer; The P-type electrode passes through the passivation layer and is connected to the P-type indium phosphide lightly doped contact layer.

2. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The quantum dot spacing of the intrinsic indium arsenide quantum dot avalanche layer ranges from 3 nanometers to 10 nanometers.

3. The indium arsenide quantum dot single photon avalanche diode according to claim 2, characterized in that: The thickness of the intrinsic indium arsenide quantum dot avalanche layer ranges from 500 nanometers to 2000 nanometers.

4. The indium arsenide quantum dot single photon avalanche diode according to claim 3, characterized in that: The quantum dot layer thickness in the intrinsic indium arsenide quantum dot avalanche layer ranges from 10 nanometers to 50 nanometers; the spacing layer thickness ranges from 20 nanometers to 100 nanometers; the number of periods is 5 to 50, and the thickness of a single period ranges from 30 nanometers to 150 nanometers.

5. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The buffer layer comprises a low-temperature germanium layer, a high-temperature germanium layer, a gallium arsenide buffer layer and an indium phosphide buffer layer stacked in sequence; The substrate layer is a silicon substrate; the silicon substrate is a non-corner-cut silicon substrate, a 6-degree beveled silicon substrate, a silicon-on-insulator substrate, a fully depleted silicon-on-insulator substrate, a sapphire substrate or a silicon-on-sapphire substrate.

6. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The buffer layer comprises an indium phosphide on insulator layer and an indium phosphide layer stacked in sequence; and the substrate layer is an indium phosphide on sapphire substrate.

7. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The buffer layer comprises a gallium arsenide on insulator layer, a gallium arsenide layer and an indium phosphide buffer layer stacked in sequence; The substrate layer is a gallium arsenide substrate on sapphire.

8. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The buffer layer comprises a germanium-on-insulator layer, a germanium layer, a gallium arsenide buffer layer and an indium phosphide buffer layer stacked in sequence; The substrate layer is a germanium-on-sapphire substrate.

9. The indium arsenide quantum dot single photon avalanche diode according to any one of claims 5 to 8, characterized in that: The buffer layer and the substrate layer are both N-type heavily doped structures.

10. The indium arsenide quantum dot single photon avalanche diode according to claim 5, characterized in that: The thickness of the gallium arsenide buffer layer ranges from 200 nanometers to 1000 nanometers; The thickness of the indium phosphide buffer layer ranges from 1000 nanometers to 1500 nanometers; the thickness of the low-temperature germanium layer ranges from 100 nanometers to 500 nanometers; and the thickness of the high-temperature germanium layer ranges from 1000 nanometers to 1500 nanometers.

11. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The thickness of the N-type indium phosphide doped layer ranges from 200 nanometers to 1000 nanometers.

12. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The thickness of the intrinsic InGaAs absorption layer ranges from 1000 nanometers to 1500 nanometers.

13. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The thickness of the N-type InGaAsP lightly doped gradient layer and the N-type InP lightly doped charge layer are both in the range of 50 nanometers to 100 nanometers.

14. The indium arsenide quantum dot single photon avalanche diode according to claim 1, characterized in that: The thickness of the P-type indium phosphide lightly doped contact layer ranges from 200 nanometers to 1000 nanometers.

15. A method for manufacturing an indium arsenide quantum dot single photon avalanche diode, characterized in that: include: providing a substrate layer of a first predetermined length; A buffer layer, an N-type indium phosphide doped layer, an intrinsic indium gallium arsenic absorption layer, an N-type indium gallium arsenic phosphide lightly doped gradient layer, an N-type indium phosphide lightly doped charge layer, an intrinsic indium arsenide quantum dot avalanche layer with a quantum dot size ranging from 2 nanometers to 10 nanometers, and a P-type indium phosphide lightly doped contact layer are sequentially stacked on the substrate layer; The intrinsic InGaAs absorption layer, the N-type InGaAsP lightly doped gradient layer, the N-type InP lightly doped charge layer, the intrinsic InAs quantum dot avalanche layer and the P-type InP lightly doped contact layer are etched to a second preset length to obtain a mesa of a second preset length; wherein the first preset length is greater than the second preset length; Covering the N-type indium phosphide doped layer and the second mesa of the preset length with a passivation layer; Allowing an N-type electrode to pass through the passivation layer and connect to the N-type indium phosphide doped layer; The P-type electrode is connected to the P-type indium phosphide lightly doped contact layer through the passivation layer.

Images