Radar signal pulse width filtering method based on memory in FPGA

Abstract

The invention provides a radar signal pulse width filtering method based on a memory in an FPGA (Field Programmable Gate Array). Radar signals within a certain width are filtered by delaying radar signals and processing the delayed radar signals and original signals. The radar signal is sampled by an amplitude quantization ADC to obtain a discrete level; the data and a threshold comparison level synthesis data set of a radar signal are stored in a memory; calculating a read address corresponding to the write address of each clock period according to the pulse width requirement needing to be filtered; the data set in the memory is read by using the read address obtained through calculation in a continuous reading mode, and the data set is radar signal sampling data after time delay and threshold comparison level; and the delayed threshold comparison level and the original threshold comparison level are combined to obtain a signal within the specified pulse width, and the front edge of the read ADC sampling signal and the front edge of the final threshold signal after the pulse width is filtered keep the original relative time relation unchanged.

Description

Technical Field

[0001] The present application relates to the field of electronic information processing technology, and in particular to a radar signal pulse width filtering method based on memory in FPGA. Background Art

[0002] Electromagnetic environment refers to the sum of electromagnetic activities and phenomena in space that have an impact on combat. As an inseparable organic whole of electronic countermeasures, complex electromagnetic environment is both a requirement of electronic countermeasures and a challenge faced by electronic countermeasures. In a complex electromagnetic environment, electronic countermeasures need to accurately identify the target signals that need to be countered in high-density signals and take interference measures against them. This requires electronic countermeasures equipment to have multi-dimensional screening methods to quickly and accurately screen out target signals in this complex electromagnetic environment, including azimuth, pitch, amplitude, repetition rate, pulse width, signal type, etc.

[0003] Pulse width filtering is widely used in various jamming devices as an effective means to identify different pulse width signals in complex electromagnetic environments. This function can eliminate narrow pulse width or wide pulse width as needed. For self-defense jamming devices, when the wide pulse to be interfered cannot be accurately distinguished from the narrow pulse signals of other radars by frequency, azimuth, elevation and amplitude, the required jamming resources are large, and the jamming signal caused by the false triggering of narrow pulse width will greatly waste the jamming resources. Therefore, how to safely and effectively filter out narrow pulse width signals is particularly important.

[0004] The traditional narrow pulse width filtering method counts the radar detection signal. When the count value is greater than the pulse width currently required to be filtered, the interference signal generation module is notified through the flag bit to start the module. In order to ensure that the generation of the flag bit is synchronized with the arrival of the radar sampling signal at the interference signal generation module, the radar signal sampled by the ADC needs to be delayed at the same time. The length of the delay is the filtered pulse width. In fact, depending on the task, the narrow pulse width required to filter out each interference is different. Therefore, the traditional method of using D flip-flops to delay the signal at different times and then select data according to requirements consumes a large number of D flip-flops and data selectors, which greatly wastes the logic resources of the FPGA. Therefore, how to achieve finer step control of the pulse width filtering function while saving resources has become an urgent problem that needs to be solved. Summary of the invention

[0005] The present application provides a radar signal pulse width filtering method based on memory in FPGA, which can be used to solve the technical problem that the prior art cannot realize the control of pulse width filtering function with finer steps under the premise of controlling resources.

[0006] The method of the present application comprises the following steps:

[0007] The first step is ADC sampling and quantization, that is, sampling the input RF signal through the amplitude quantization ADC, and obtaining a discrete level representing the input signal amplitude according to the amplitude of the input analog signal. The level can be represented by a binary code, and the detection threshold signal describing the pulse width is obtained by amplitude comparison, and sent to the FPGA together;

[0008] The second step is to combine the sampled data and the detection threshold into a data set, establish a data memory, and store the data set into the memory in a continuous storage manner, that is, regardless of whether the sampling signal or the detection threshold is valid, the write enable signal of the memory is always high, and the write address is continuously accumulated;

[0009] The third step is data reading. The delay t is calculated according to the minimum pulse width of the signal to be filtered out, and the delay is converted into the number of clock beats of the memory. This value is the difference between the write address and the read address of the memory. The continuous reading method is also used when reading data. The read address of each beat is the write address minus the difference, and the read enable is always high. In this way, there is a fixed delay between the data read and the data written in each beat.

[0010] The fourth step is threshold processing. The threshold signal is extracted from the data read from the memory. Compared with the original threshold, the signal has been delayed by t. If the width meets the requirements after being ANDed with the original threshold, the rising edge of the signal generated by the ANDing is the rising edge of the delayed signal. The time relationship with the ADC sampling data after the delay remains unchanged, and the rising edge can be used for subsequent signal processing.

[0011] Compared with the prior art, the present invention has the following significant advantages: (1) the ADC sampling data or the threshold signal are stored in the memory regardless of whether they are valid or not by adopting the continuous storage method, and there is no need to count and calculate the width of the continuous high level of the threshold signal; (2) the delay time determines the difference between the read and write addresses, and by changing this value, different delays of the signal can be achieved, avoiding the situation that the delay value cannot be changed arbitrarily after the traditional use of D flip-flops for delay; (3) after reading the data according to the read address calculated by the delay value, the delay between the data read from the memory and the original data meets the requirements, and no data selection is required; (4) after the read threshold detection signal is ANDed with the original threshold detection signal, the pulse signal that does not meet the requirements can be filtered out, and the relative relationship between the rising edge of the original threshold signal and the ADC sampling data time can also be retained. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The pulse width filtering module algorithm diagram provided in the embodiment of the present application;

[0013] Figure 2 An example diagram of a data storage device provided in an embodiment of the present application;

[0014] Figure 3A schematic diagram of wide pulse width signal processing provided in an embodiment of the present application;

[0015] Figure 4 A schematic diagram of narrow pulse width signal processing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0017] The following first introduces the embodiments of the present application in conjunction with the accompanying drawings.

[0018] This application is different from the traditional method of filtering out pulse widths less than the requirement by counting the threshold signal of the radar signal, and is implemented by delaying the threshold signal and performing an AND operation. In order to meet different small pulse width filtering requirements in practical applications and save resources at the same time, a memory-based method is used to store the radar signal sampling data and the threshold comparison level in the memory together, and then read them out after a delay, and the threshold levels before and after the delay are processed to finally filter out other signals with pulse widths less than the signal requirement, while ensuring that the relationship between the delayed sampling data and the leading edge of the filtered threshold signal is consistent with that before the delay, which is convenient for subsequent signal processing.

[0019] In the first step, the RF signal is continuously sampled through the amplitude quantization ADC to convert the signal from analog to digital. At the same time, the RF analog signal is detected to obtain the corresponding detection threshold signal, which is sent to the FPGA.

[0020] The second step is to combine the sampled data and the detection threshold into a data set, establish a data storage device, and store the data set into the storage device in a continuous storage manner;

[0021] There is no need to count and detect the width of the radar threshold comparison signal. Instead, the ADC sampling data is combined into a data set, and a memory that can be read and written at the same time is set. The bit width of the memory is equal to the sum of the bit width of the ADC sampling data and the signal detection level. The capacity of the memory is greater than the maximum pulse width to be filtered and meets the Nth power of 2, such as Figure 2 As shown,

[0022] The digital signal data obtained after ADC conversion adc And the detection signal data dlva Synthesized data data, that is: data = {data dlva , data dlva}, as the input data of the memory;

[0023] The write enable signal of the memory is always valid. The write address is accumulated in units of 1 and the clock signal is used as the beat from the start of the program. When the memory size is exceeded, it starts to accumulate again from zero. The size of the memory is the number of beats converted by the maximum pulse width that needs to be filtered and is 2 to the power of N. The memory write address and write enable generation module are as follows: Figure 1 shown.

[0024] The third step is data reading, which uses a pipeline reading method. The read enable is always valid, and a constant difference relationship is maintained between the read address and the write address.

[0025] The required filtered pulse width is converted into the number of memory clock beats, which is the difference between the write address and the read address. When reading data, a pipeline reading method is adopted, and the read enable is always valid. The difference between the read address and the write address is kept constant. Taking the filtered pulse width τ as an example, the read and write clock frequency is f clk , then the difference between the read and write addresses is Δaddr = τ × f clk , the read address is addr read =addr write -Δaddr, when the write address is less than Δaddr, the read address addr read =addr max +addr write -Δaddr, where addr max is the size of the memory.

[0026] Assume that the pulse width to be filtered is t, and the internal clock frequency of the FPGA is f clk , the pulse width value is converted into the clock beat number as τ×f clk At this time, the read address of the memory is taken as the read address by subtracting this value from the write address. At the same time, the read enable signal is always valid. The time that the read data q lags behind the data written into the memory is the pulse width τ. By changing the size of τ, different delays for data are achieved, and the step is the internal clock frequency of the FPGA. The memory read address and read enable generation module is as follows: Figure 1 shown.

[0027] Step 4: Threshold signal processing

[0028] The delay length of the data read from the memory compared with the original data is the pulse width that needs to be filtered out. After the detection signal is delayed by t, when the pulse signal width does not meet the minimum pulse width requirement, compared with the original detection signal, there is no overlapping part between the two threshold detection signals. After the AND operation, the signal becomes a low level, and the signal less than the minimum pulse width is filtered out;

[0029] When the pulse signal width is greater than the minimum pulse width requirement, the signal is retained and used as the threshold signal for final use.

[0030] Specifically, after the pulse width filter and the detection signal pass through the memory, there is a delay of τ compared with the original signal. When there is a radar pulse signal, the delay between the two pulses is also τ. When the width of the radar pulse signal is greater than τ, there is an overlap between the original detection level and the delayed detection level. After the two signals are ANDed, the rising edge is the position of the delayed detection signal, such as Figure 3 As shown, the relationship between the delayed ADC sampling data is maintained. At this time, the edge is used as the reference to re-store the DRFM signal and delay count; when the width of the radar pulse signal is less than τ, the two signals are low level after the AND operation, and the detection signal no longer exists, as shown in Figure 4 As shown, the stored ADC sampling data is discarded at the same time, and the pulse signal smaller than the pulse width is successfully filtered out.

[0031] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. A radar signal pulse width filtering method based on memory in FPGA, characterized in that: The method comprises: In the first step, the RF signal is continuously sampled through the amplitude quantization ADC to convert the signal from analog to digital. At the same time, the RF analog signal is detected to obtain the corresponding detection threshold signal, which is then sent to the FPGA. The second step is to combine the sampled data and the detection threshold into a data set, establish a data storage device, and store the data set into the storage device in a continuous storage manner; The third step is data reading, which uses pipeline reading. The read enable is always valid, and the difference between the read address and the write address is kept constant. The fourth step is threshold signal processing.

2. The method according to claim 1, characterized in that The second step is to combine the sampled data and the detection threshold into a data set, establish a data storage device, and store the data set into the storage device in a continuous storage manner; including: Set up a memory that can read and write at the same time. The bit width of the memory is equal to the sum of the bit width of the ADC sampling data and the signal detection level. The capacity of the memory is greater than the maximum pulse width to be filtered and satisfies the Nth power of 2. The digital signal data obtained after ADC conversion adc And the detection signal data dlva Synthetic data data, that is: data = {data dlva , data dlva }, as the input data of the memory; The write enable signal of the memory is always valid. The write address is accumulated in units of 1 and in rhythm with the clock signal from the start of the program. When the memory size is exceeded, it starts to accumulate again from zero.

3. The method according to claim 1, characterized in that The third step is data reading, which uses pipeline reading. The read enable is always valid, and the difference between the read address and the write address is kept constant, including: The required filtered pulse width is converted into the number of clock beats of the memory, which is the difference between the write address and the read address. When reading data, a pipeline reading method is adopted, and the read enable is always valid. The difference relationship between the read address and the write address is kept constant; the filtered pulse width τ, the read and write clock frequency is f clk , then the difference between the read and write addresses is Δaddr = τ × f clk , the read address is addr read =addr write -Δaddr, when the write address is less than Δaddr, the read address addr read =addr max +addr write -Δaddr, where addr max is the size of the memory. By changing the size of τ, different delays for data can be achieved, and the step is the internal clock frequency of the FPGA.

4. The method according to claim 1, characterized in that: The fourth step is threshold signal processing, including: The delay length of the data read from the memory compared with the original data is the pulse width that needs to be filtered out. After the detection signal is delayed by t, when the pulse signal width does not meet the minimum pulse width requirement, compared with the original detection signal, there is no overlapping part between the two threshold detection signals. After the AND operation, the signal becomes a low level, and the signal less than the minimum pulse width is filtered out; When the pulse signal width is greater than the minimum pulse width requirement, the signal is retained and used as the threshold signal for final use.

Images