Voltage drop control method and device, electronic equipment, storage medium and chip

Abstract

The invention provides a voltage drop control method, which comprises the steps of acquiring a to-be-executed instruction path, determining whether the to-be-executed instruction path is a marked instruction path or not, and starting a preset current limiting strategy to execute the to-be-executed instruction path under the condition that the to-be-executed instruction path is determined to be the marked instruction path, the current limiting strategy is used for adjusting the voltage before triggering the voltage drop. According to the embodiment of the invention, before the to-be-executed instruction path is executed, the control voltage is suppressed in advance, the voltage drop is suppressed at relatively low performance cost, and the triggering probability of underclocking suppression of the voltage drop is reduced, so that the running voltage of the CPU can be further reduced to obtain the power consumption benefit.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a voltage drop control method, device, electronic device, storage medium and chip. Background Art

[0002] With the popularization of mobile terminal devices, users have put forward higher requirements on the performance of mobile System On Chip (SOC). At present, after detecting a voltage drop, suppressing the voltage drop by reducing the frequency is a post-event remedy, and suppressing the voltage drop by reducing the frequency requires a large SOC performance cost to quickly suppress the drop, which has a great impact on the performance of the SOC. Summary of the invention

[0003] The present disclosure provides a voltage drop control method and device, an electronic device, a storage medium and a chip to solve the problems in the related art. The voltage drop can be suppressed in advance through suppression control at a lower performance cost, and the triggering probability of frequency reduction to suppress the drop can be reduced, which can further reduce the operating voltage of the CPU to obtain power consumption benefits.

[0004] A first aspect of the present disclosure provides a method for controlling a voltage drop, the method comprising:

[0005] Get the path of the instructions to be executed;

[0006] Determine whether the instruction path to be executed is a marked instruction path;

[0007] In the case where it is determined that the instruction path to be executed is the marked instruction path, a preset current limiting strategy is enabled to execute the instruction path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

[0008] In some embodiments, determining whether the instruction path to be executed is a marked instruction path includes:

[0009] Comparing the to-be-executed instruction path with preset record information; the preset record information records the instruction path that triggers the voltage drop and the preset instruction path;

[0010] According to the comparison result between the instruction path to be executed and the preset record information, it is determined whether the instruction path to be executed is a marked instruction path.

[0011] In some embodiments, the determining whether the to-be-executed instruction path is a marked instruction path according to the comparison result between the to-be-executed instruction path and the preset record information includes:

[0012] If it is determined that the to-be-executed instruction path is recorded in the preset record information, then determining that the to-be-executed instruction path is the marked instruction path;

[0013] If it is determined that the to-be-executed instruction path is not recorded in the preset record information, it is determined that the to-be-executed instruction path is not the marked instruction path.

[0014] In some embodiments, before comparing the to-be-executed instruction path with the preset record information, the method further includes:

[0015] Monitoring whether there is a target instruction fragment that triggers a voltage drop;

[0016] After there is a target instruction segment that triggers a voltage drop, recording an execution path that enters the target instruction segment;

[0017] The execution path entering the target instruction segment is stored in the preset record information.

[0018] In some embodiments, after there is a target instruction segment that triggers a voltage drop, recording an execution path that enters the target instruction segment includes:

[0019] The target instruction fragment corresponds to an execution function call path and a jump path within the execution function.

[0020] In some embodiments, enabling a preset current limiting strategy to execute the to-be-executed instruction path includes:

[0021] Controlling the number of executions of an instruction execution unit of a processor per unit time, wherein the instruction execution unit is used to execute the instruction path to be executed;

[0022] And / or, controlling the available number of instruction execution units of the processor.

[0023] In some embodiments, before comparing the to-be-executed instruction path with the preset record information, the method further includes:

[0024] Determine whether power is shared between multiple processors;

[0025] If so, the multiple processors are configured to share the same preset record information.

[0026] In some embodiments, after enabling the preset current limiting strategy to execute the instruction path to be executed, the method further includes:

[0027] Determine whether there is an address corresponding to the instruction path to be executed in the return stack;

[0028] When it is determined that the address corresponding to the to-be-executed instruction path does not exist in the return stack, the preset current limiting strategy is switched to a closed state.

[0029] A second aspect of the present disclosure provides a voltage drop control device, the device comprising:

[0030] An acquisition unit, used for acquiring a path of instructions to be executed;

[0031] A first determining unit, configured to determine whether the instruction path to be executed is a marked instruction path;

[0032] A control unit is used to enable a preset current limiting strategy to execute the instruction path to be executed when it is determined that the instruction path to be executed is the marked instruction path.

[0033] In some embodiments, the first determining unit includes:

[0034] A comparison module, used for comparing the instruction path to be executed with preset record information; the preset record information records the instruction path that triggers the voltage drop and the preset instruction path;

[0035] The determination module is used to determine whether the instruction path to be executed is a marked instruction path according to the comparison result between the instruction path to be executed and the preset record information.

[0036] In some embodiments, the determining module is further configured to:

[0037] If it is determined that the to-be-executed instruction path is recorded in the preset record information, then determining that the to-be-executed instruction path is the marked instruction path;

[0038] If it is determined that the to-be-executed instruction path is not recorded in the preset record information, it is determined that the to-be-executed instruction path is not the marked instruction path.

[0039] In some embodiments, the apparatus further comprises:

[0040] A monitoring unit, used for monitoring whether there is a target instruction segment that triggers a voltage drop before comparing the instruction path to be executed with preset record information;

[0041] A recording unit, used for recording an execution path entering the target instruction segment after there is a target instruction segment that triggers a voltage drop;

[0042] The storage unit is used to store the execution path entering the target instruction fragment in the preset record information.

[0043] In some embodiments, the recording unit is further used to:

[0044] The target instruction fragment corresponds to an execution function call path and a jump path within the execution function.

[0045] In some embodiments, the control unit is further configured to:

[0046] Controlling the number of executions of an instruction execution unit of a processor per unit time, wherein the instruction execution unit is used to execute the instruction path to be executed;

[0047] And / or, controlling the available number of instruction execution units of the processor.

[0048] In some embodiments, the apparatus further comprises:

[0049] A second determination unit, used for determining whether a power supply is shared between the multiple processors before comparing the to-be-executed instruction path with the preset record information;

[0050] A configuration unit is used to configure the multiple processors to share the same preset record information if yes.

[0051] In some embodiments, the apparatus further comprises:

[0052] A third determining unit is used to determine whether there is an address corresponding to the instruction path to be executed in the return stack after the preset current limiting strategy is enabled to execute the instruction path to be executed;

[0053] The switching unit is used to switch the preset current limiting strategy to a closed state when it is determined that the address corresponding to the to-be-executed instruction path does not exist in the return stack.

[0054] The third aspect embodiment of the present disclosure proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in the first aspect embodiment of the present disclosure.

[0055] The fourth aspect embodiment of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the method described in the first aspect embodiment of the present disclosure.

[0056] The fifth aspect embodiment of the present disclosure proposes a chip, which includes one or more interfaces and one or more processors; the interface is used to receive signals from a memory of an electronic device and send signals to the processor, the signals include computer instructions stored in the memory, and when the processor executes the computer instructions, the electronic device executes the method described in the first aspect embodiment of the present disclosure.

[0057] In summary, according to the voltage drop control method proposed in the present disclosure, the method includes obtaining an instruction path to be executed, determining whether the instruction path to be executed is a marked instruction path, and in the case where it is determined that the instruction path to be executed is the marked instruction path, enabling a preset current limiting strategy to execute the instruction path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop. In the embodiment of the present application, before the instruction path to be executed is executed, the voltage drop is suppressed in advance by suppressing the control voltage at a relatively small performance cost, and the triggering probability of suppressing the voltage drop by frequency reduction is reduced, which can further reduce the operating voltage of the CPU to obtain power consumption benefits.

[0058] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0060] Figure 1 A schematic diagram of a voltage drop control system provided by an embodiment of the present disclosure;

[0061] Figure 2 A flow chart of a voltage drop control method provided by an embodiment of the present disclosure;

[0062] Figure 3 A flow chart of a voltage drop control method provided by an embodiment of the present disclosure;

[0063] Figure 4 A flow chart of a voltage drop control method provided by an embodiment of the present disclosure;

[0064] Figure 5 A flow chart of a voltage drop control method provided by an embodiment of the present disclosure;

[0065] Figure 6 A schematic diagram of the structure of a voltage drop control device provided in an embodiment of the present disclosure;

[0066] Figure 7 A schematic diagram of the structure of a voltage drop control device provided in an embodiment of the present disclosure;

[0067] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure;

[0068] Fig. 9 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0070] With the popularization of mobile terminal devices, users have put forward higher requirements on the performance of mobile System On Chip (SOC). At present, after detecting a voltage drop, suppressing the voltage drop by reducing the frequency is a post-event remedy, and suppressing the voltage drop by reducing the frequency requires a large SOC performance cost to quickly suppress the drop, which has a great impact on the performance of the SOC.

[0071] Therefore, in order to solve the problems existing in the related technology, the present disclosure proposes a voltage drop control method, obtains the instruction path to be executed, determines whether the instruction path to be executed is a marked instruction path, and when it is determined that the instruction path to be executed is the marked instruction path, enables a preset current limiting strategy to execute the instruction path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

[0072] This solution suppresses the voltage drop in advance before the execution of the instruction path to be executed, at a small performance cost, by suppressing the control voltage, reducing the probability of triggering the frequency reduction to suppress the voltage drop, and can further reduce the CPU's operating voltage to obtain power consumption benefits.

[0073] The embodiments of the present disclosure are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present disclosure. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a certain embodiment can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementation methods in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0074] In each embodiment of the present disclosure, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0075] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0076] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0077] In some embodiments, terms such as "in response to ...", "in response to determining ...", "in the case of ...", "at the time of ...", "when ...", "if ...", "if ...", etc. can be used interchangeably.

[0078] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", and "above" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0079] The prefixes such as "first" and "second" in the embodiments of the present disclosure are only for distinguishing different description objects and do not constitute any restrictions on the position, order, priority, quantity or content of the description objects. For the statement of the description objects, please refer to the description in the context of the claims or embodiments, and no unnecessary restrictions should be constituted due to the use of prefixes.

[0080] In the embodiments of the present disclosure, “plurality” refers to two or more.

[0081] In the embodiments of the present disclosure, terms such as "import", "input", and "read in" can be used interchangeably.

[0082] In some embodiments, devices, etc. can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", and "subject" can be used interchangeably.

[0083] In some embodiments, the term “terminal”, “terminal device”, “user equipment (UE)”, “user terminal”, “mobile station

[0084] The terms "mobile station, MS", "mobile terminal, MT", subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriber station, access terminal, mobile terminal, wireless terminal, remote terminal, handset, user agent, mobile client, client and the like may be used interchangeably.

[0085] like Figure 1 As shown, Figure 1 A schematic diagram of a voltage drop control system provided by an embodiment of the present disclosure includes: a voltage drop detection module 11, a frequency modulation controller 12, a jump recording unit 13, a return stack recording unit 14, a central processing unit (CPU) 15, and a path detection unit 16. The voltage drop detection module 11 is used to detect the operating voltage of the CPU, and when a trigger voltage drop is detected, a notification message is sent to the frequency modulation controller 12.

[0086] The voltage drop is suppressed by the frequency modulation controller 12 through the frequency reduction operation. At the same time, the voltage drop detection module 11 sends a notification message to the jump recording unit 13 and the return stack recording unit 14, so that the jump recording unit 13 and the return stack recording unit 14 record and mark the current return stack and jump record of the CPU.

[0087] Figure 2This is a flow chart of a voltage drop control method provided by an embodiment of the present disclosure. The method can be applied to application scenarios such as smart terminals, for example, executed by a mobile terminal with an integrated SOC function or a processor in the terminal, or executed by other devices suitable for CPU voltage drop suppression processing, and the present disclosure is not limited thereto. Figure 2 As shown, the voltage drop control method includes steps 201-203.

[0088] Step 201, obtaining the path of the instruction to be executed.

[0089] The embodiments of the present application can be applied to scenarios where the CPU operates with large current changes, and can suppress the drop of the CPU operating voltage at a small performance cost.

[0090] During the CPU instruction execution process, the instruction path that has not been executed is called the pending instruction path.

[0091] Step 202: Determine whether the instruction path to be executed is a marked instruction path.

[0092] The marked instruction path described in the embodiment of the present application indicates that the instruction path is a high-power instruction path, and the marked instruction path will trigger a CPU voltage drop.

[0093] Therefore, when the CPU executes the instruction path to be executed, it is determined in real time whether the instruction path to be executed is a marked instruction path, that is, whether a voltage drop will be triggered when executing the instruction path to be executed.

[0094] In some embodiments, the marked instruction path may be marked when the instruction path triggers a voltage drop for the first time. In other embodiments, the marked instruction path may also be a command path that may be triggered based on a priori settings. Specifically, the marking method of the marked instruction path is not limited in the embodiments of the present application.

[0095] In actual application, the marked paths may also be stored in a table, and when the CPU executes instructions, the table storing the marked paths may be queried in real time to improve real-time efficiency. Alternatively, the marked paths may be stored in other forms, which are not specifically limited.

[0096] Step 203: when it is determined that the instruction path to be executed is the marked instruction path, a preset current limiting strategy is enabled to execute the instruction path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

[0097] When the instruction path to be executed is determined to be a marked instruction path, it indicates that the execution of the instruction path to be executed may trigger a voltage drop. Therefore, in order to prevent the occurrence of voltage drops, the embodiment of the present application adopts a method of suppressing voltage drops in advance, that is, before the voltage drop is triggered, the voltage drop is suppressed in advance through a preset current limiting strategy inside the CPU, and the current limiting strategy is used to adjust the voltage before the voltage drop is triggered.

[0098] The specific preset current limiting strategy is used to limit the current and stagger the execution of high-power instruction paths to be executed, control the CPU load in advance, and achieve the purpose of suppressing voltage drops. Through targeted suppression in advance, voltage drops can be suppressed at a lower cost and the probability of frequency reduction triggering can be reduced.

[0099] In some embodiments, the preset current limiting strategy includes but is not limited to limiting the number of executions of the instruction execution unit of the processor per unit time and / or limiting whether the instruction execution unit can be executed simultaneously, etc. It can be dynamically adjusted according to the actual power consumption of the instruction path to be executed. For example, when the power consumption of the instruction path to be executed is relatively low, a current limiting strategy that limits the number of executions of the instruction execution unit of the processor per unit time, or, limits whether the processor can be executed simultaneously, is adopted. When the power consumption of the instruction path to be executed is relatively high, a current limiting strategy that limits the number of executions of the instruction execution unit of the processor per unit time, and, limits whether the instruction execution unit of the processor can be executed simultaneously, is adopted at the same time.

[0100] In summary, according to the voltage drop control method proposed in the present disclosure, the method includes obtaining an instruction path to be executed, determining whether the instruction path to be executed is a marked instruction path, and in the case where it is determined that the instruction path to be executed is the marked instruction path, enabling a preset current limiting strategy to execute the instruction path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop. In the embodiment of the present application, before the instruction path to be executed is executed, the voltage drop is suppressed in advance by suppressing the control voltage at a relatively small performance cost, and the triggering probability of frequency reduction to suppress the voltage drop is reduced, which can further reduce the operating voltage of the CPU to obtain power consumption benefits.

[0101] Figure 3 The following is a flow chart of a method for controlling voltage drop proposed by the present disclosure. Figure 2 The embodiment shown further explains step 202. Figure 3 The following steps may be included:

[0102] Step 301, comparing the to-be-executed instruction path with preset record information; the preset record information records the instruction path that triggers the voltage drop and the preset instruction path;

[0103] Step 302: Determine whether the instruction path to be executed is a marked instruction path based on a comparison result between the instruction path to be executed and the preset record information.

[0104] If it is determined that the instruction path to be executed is recorded in the preset record information, step 303 is executed; if it is determined that the instruction path to be executed is not recorded in the preset record information, step 304 is executed.

[0105] Step 303, determining that the instruction path to be executed is the marked instruction path;

[0106] Step 304: determine that the instruction path to be executed is not the marked instruction path.

[0107] Figure 4 A flow chart of a voltage drop control method proposed in the present disclosure is further shown. Figure 4 The following steps may be included:

[0108] Step 401 , monitoring whether there is a target instruction segment that triggers a voltage drop.

[0109] In an embodiment of the present disclosure, a target instruction fragment includes an instruction fragment or a combination of two or more instructions.

[0110] Please continue reading Figure 1 During the process of CPU 15 executing instructions, the voltage drop detection module 11 monitors whether there is a target instruction fragment that triggers the voltage drop. When the voltage drop detection module 11 detects the existence of a target instruction fragment that triggers the voltage drop, it sends notification messages to the jump recording unit 13 and the return stack recording unit 14 respectively.

[0111] In some embodiments, the target instruction fragment includes but is not limited to: floating-point operations, matrix operations, vector operations, etc. The embodiments of the present application do not limit the type of the target instruction fragment.

[0112] In addition to determining the target instruction fragment through real-time monitoring, high-power target instruction fragments can also be obtained through preliminary testing, microarchitecture analysis, etc.

[0113] Step 402 : after there is a target instruction segment that triggers a voltage drop, record an execution path that enters the target instruction segment.

[0114] In actual applications, the target instruction fragment can be a hot code function with high power consumption, so the target instruction fragment may occur in the function call or in the jump process within the function. Therefore, after determining the target instruction fragment, it is necessary to obtain the entry path to the target instruction fragment, that is, to obtain and record the execution function call path and the jump path within the execution function corresponding to the target instruction fragment.

[0115] The target instruction fragment corresponds to the execution function call path recorded in the current return stack of the CPU, and the jump path within the execution function is recorded in the most recent jump record.

[0116] Step 403: Store the execution path of entering the target instruction segment in the preset record information.

[0117] The target instruction fragment corresponds to the execution function call path and the jump path within the execution function, which are respectively stored in the preset record information. The embodiment of the present application does not limit the form of the preset record information. For example, it can be in the form of a table, a log, etc.

[0118] Step 404, obtaining the path of the instruction to be executed.

[0119] Step 405: Determine whether the instruction path to be executed is recorded in the preset record information.

[0120] If it is determined that the instruction path to be executed is recorded in the preset record information, step 406 is executed; if it is determined that the instruction path to be executed is not recorded in the preset record information, step 407 is executed.

[0121] For instructions on steps 404 and 405, please refer to Figure 1 The relevant detailed description of the embodiments of the present application will not be repeated here.

[0122] Step 406: Enable the preset current limiting strategy to execute the instruction path to be executed.

[0123] The preset current limiting strategy (also called the current limiting peak-shifting strategy) includes: limiting the number of executions of the instruction execution unit of the processor per unit time; and / or controlling the available number of instruction execution units of the processor.

[0124] When executing the instruction path to be executed through the preset current limiting strategy, the number of executions in the instruction execution unit of the processor per unit time can be dynamically set. The number of executions can be controlled by setting a threshold value of the instruction execution unit, and / or, the available number of processor instruction execution units can be dynamically set, that is, the number of instruction execution units that can be executed simultaneously is limited.

[0125] In another implementation method of the embodiment of the present application, the fixed number of executions of high-power consumption pending instructions per unit time is limited, and / or the fixed number of high-power consumption pending instructions that can be executed simultaneously is limited. The fixed number of executions and the fixed number can be set according to the test results, and the specific embodiment of the present application is not limited.

[0126] The method provided in the embodiment of the present application will not trigger a large voltage drop due to the advance current limiting, and therefore will not trigger the voltage drop suppression by frequency reduction in the related technical solution.

[0127] Step 407: execute the instruction path to be executed.

[0128] In the specific implementation process of the embodiment of the present application, after enabling the preset current limiting strategy to execute the instruction path to be executed, the method also includes: determining whether there is an address corresponding to the instruction path to be executed in the return stack, and when it is determined that there is no address corresponding to the instruction path to be executed in the return stack, switching the preset current limiting strategy to an off state.

[0129] When the address corresponding to the instruction path to be executed does not exist in the CPU return stack, it means that the CPU has completed executing the high-power code (the instruction path to be executed). Therefore, the current limiting peak shifting inside the CPU can be canceled, that is, the preset current limiting strategy can be switched to the off state to restore the system processing performance in time.

[0130] In actual application, there may be an application scenario where multiple CPUs share a power supply. In this scenario, when the instruction executed by CPU1 may call the high-power execution function A, the instruction executed by CPU2 may call the high-power execution function A and execution function C, that is, there is a shared marked instruction path. Therefore, in order to facilitate the current limiting management of multiple CPUs, the embodiment of the present application also provides the following supplementary solution. Figure 5 As shown, the method includes:

[0131] Step 501, determining whether multiple processors share a common power supply.

[0132] In the scenario where it is determined that there are multiple processors, determine whether the multiple processors share a power supply. The number of processors has been set at the factory. By reading the relevant configuration information, it can be determined whether the smart device contains multiple processors, that is, whether the multiple processors share a power supply.

[0133] Step 502: If yes, configure the multiple processors to share the same preset record information.

[0134] Therefore, different CPUs may call the same execution function, and therefore, multiple CPUs are configured to share the same preset record information. It should be noted that the multiple CPUs can be all CPUs in the smart terminal, or multiple CPUs currently enabled in the smart terminal, or multiple CPUs in the smart terminal that are higher than a preset load threshold, etc., and the specific details are not limited.

[0135] Corresponding to the above voltage drop control method, the present invention also provides a voltage drop control device. Since the device embodiment of the present invention corresponds to the above method embodiment, the details not disclosed in the device embodiment can be referred to the above method embodiment, and will not be repeated in the present invention.

[0136] Figure 6 The schematic diagram of the structure of a voltage drop control device 600 provided in an embodiment of the present disclosure includes:

[0137] An acquisition unit 61 is used to acquire a path of instructions to be executed;

[0138] A first determining unit 62, configured to determine whether the instruction path to be executed is a marked instruction path;

[0139] The control unit 63 is used to enable a preset current limiting strategy to execute the instruction path to be executed when it is determined that the instruction path to be executed is the marked instruction path, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

[0140] In summary, according to the voltage drop control device proposed in the present disclosure, the device includes obtaining an instruction path to be executed, determining whether the instruction path to be executed is a marked instruction path, and in the case where it is determined that the instruction path to be executed is the marked instruction path, enabling a preset current limiting strategy to execute the instruction path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop. Before the execution of the instruction path to be executed, the embodiment of the present application suppresses the voltage drop at a relatively small performance cost by suppressing the control voltage in advance, thereby reducing the probability of triggering the voltage drop by reducing the frequency, and can further reduce the operating voltage of the CPU to obtain power consumption benefits.

[0141] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the first determining unit 62 includes:

[0142] The comparison module 621 is used to compare the instruction path to be executed with the preset record information; the preset record information records the instruction path that triggers the voltage drop and the preset instruction path;

[0143] The determination module 622 is used to determine whether the instruction path to be executed is a marked instruction path according to the comparison result between the instruction path to be executed and the preset record information.

[0144] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the determining module 622 is further used for:

[0145] If it is determined that the to-be-executed instruction path is recorded in the preset record information, then determining that the to-be-executed instruction path is the marked instruction path;

[0146] If it is determined that the to-be-executed instruction path is not recorded in the preset record information, it is determined that the to-be-executed instruction path is not the marked instruction path.

[0147] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the device also includes:

[0148] A monitoring unit 64, used for monitoring whether there is a target instruction segment that triggers a voltage drop before comparing the instruction path to be executed with the preset record information;

[0149] A recording unit 65, configured to record an execution path of entering the target instruction segment after there is a target instruction segment that triggers a voltage drop;

[0150] The storage unit 66 is used to store the execution path entering the target instruction fragment in the preset record information.

[0151] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the recording unit 65 is also used for:

[0152] The target instruction fragment corresponds to an execution function call path and a jump path within the execution function.

[0153] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the control unit 63 is also used for:

[0154] Controlling the number of executions of an instruction execution unit of a processor per unit time, wherein the instruction execution unit is used to execute the instruction path to be executed;

[0155] And / or, controlling the available number of instruction execution units of the processor.

[0156] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the device also includes:

[0157] A second determination unit 67, used to determine whether a power supply is shared between the multiple processors before comparing the to-be-executed instruction path with the preset record information;

[0158] The configuration unit 68 is configured to, if yes, configure the multiple processors to share the same preset record information.

[0159] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the device also includes:

[0160] A third determining unit 69 is used to determine whether there is an address corresponding to the instruction path to be executed in the return stack after the preset current limiting strategy is enabled to execute the instruction path to be executed;

[0161] The switching unit 610 is used to switch the preset current limiting strategy to a closed state when it is determined that the address corresponding to the to-be-executed instruction path does not exist in the return stack.

[0162] Since the device provided in the embodiment of the present disclosure corresponds to the methods provided in the above-mentioned embodiments, the implementation of the method is also applicable to the device provided in the embodiment and will not be described in detail in this embodiment.

[0163] In the embodiments provided in the present application, the methods and devices provided in the embodiments of the present application are introduced. In order to implement the functions in the methods provided in the embodiments of the present application, the electronic device may include a hardware structure and a software module, and implement the functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. A function of the functions may be executed in the form of a hardware structure, a software module, or a hardware structure plus a software module.

[0164] Figure 8 8 is a block diagram of an electronic device 800 for implementing the above-mentioned voltage drop control method according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0165] Reference Figure 8 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0166] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 1020 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0167] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEP ROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0168] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0169] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0170] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0171] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0172] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800, and the sensor assembly 814 can also detect the position change of the electronic device 800 or a component of the electronic device 800, the presence or absence of contact between the user and the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0173] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio) or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0174] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0175] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the above instructions can be executed by the processor 1020 of the electronic device 800 to perform the above method for image processing. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0176] The embodiments of the present disclosure further provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the method described in the above embodiments of the present disclosure.

[0177] For electronic devices that may be chips or chip systems, see Fig. 9 Schematic diagram of the chip structure shown. Fig. 9 The chip shown includes a processor 901 and an interface 902. The number of the processor 901 may be one or more, and the number of the interface 902 may be multiple.

[0178] Optionally, the chip further includes a memory 903, and the memory 903 is used to store necessary computer programs and data.

[0179] Those skilled in the art may also understand that the various illustrative logical blocks and steps listed in the embodiments of the present application may be implemented by electronic hardware, computer software, or a combination of the two. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art may use various methods to implement the functions for each specific application, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present application.

[0180] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0181] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0182] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0183] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processing module, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (control method), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0184] It should be understood that the various parts of the embodiments of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0185] A person skilled in the art may understand that all or part of the steps in the above-mentioned embodiment method may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0186] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0187] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for controlling voltage drop, characterized in that: The method comprises: Get the path of the instructions to be executed; Determine whether the instruction path to be executed is a marked instruction path; In the case where it is determined that the instruction path to be executed is the marked instruction path, a preset current limiting strategy is enabled to execute the instruction path to be executed, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

2. The method according to claim 1, characterized in that: Determining whether the instruction path to be executed is a marked instruction path includes: Comparing the to-be-executed instruction path with preset record information; the preset record information records the instruction path that triggers the voltage drop and the preset instruction path; According to the comparison result between the instruction path to be executed and the preset record information, it is determined whether the instruction path to be executed is a marked instruction path.

3. The method according to claim 2, characterized in that The determining, according to the comparison result between the instruction path to be executed and the preset record information, whether the instruction path to be executed is a marked instruction path comprises: If it is determined that the to-be-executed instruction path is recorded in the preset record information, then determining that the to-be-executed instruction path is the marked instruction path; If it is determined that the to-be-executed instruction path is not recorded in the preset record information, it is determined that the to-be-executed instruction path is not the marked instruction path.

4. The method according to claim 2, characterized in that: Before comparing the to-be-executed instruction path with the preset record information, the method further includes: Monitoring whether there is a target instruction fragment that triggers a voltage drop; After there is a target instruction segment that triggers a voltage drop, recording an execution path that enters the target instruction segment; The execution path entering the target instruction segment is stored in the preset record information.

5. The method according to claim 4, characterized in that After there is a target instruction segment that triggers a voltage drop, recording an execution path that enters the target instruction segment includes: The target instruction fragment corresponds to an execution function call path and a jump path within the execution function.

6. The method according to claim 2, characterized in that The enabling of the preset current limiting strategy to execute the instruction path to be executed includes: Controlling the number of executions of an instruction execution unit of a processor per unit time, wherein the instruction execution unit is used to execute the instruction path to be executed; And / or, controlling the available number of instruction execution units of the processor.

7. The method according to claim 6, characterized in that Before comparing the to-be-executed instruction path with the preset record information, the method further includes: Determine whether power is shared between multiple processors; If so, the multiple processors are configured to share the same preset record information.

8. The method according to claim 1, characterized in that: After enabling the preset current limiting strategy to execute the instruction path to be executed, the method further includes: Determine whether there is an address corresponding to the instruction path to be executed in the return stack; When it is determined that the address corresponding to the to-be-executed instruction path does not exist in the return stack, the preset current limiting strategy is switched to a closed state.

9. A voltage drop control device, characterized in that: The device comprises: An acquisition unit, used for acquiring a path of instructions to be executed; A first determining unit, configured to determine whether the instruction path to be executed is a marked instruction path; A control unit is used to enable a preset current limiting strategy to execute the instruction path to be executed when it is determined that the instruction path to be executed is the marked instruction path, wherein the current limiting strategy is used to adjust the voltage before triggering the voltage drop.

10. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

11. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-8.

12. A chip, characterized in that: It comprises one or more interfaces and one or more processors; the interface is used to receive a signal from a memory of an electronic device and send the signal to the processor, the signal includes a computer instruction stored in the memory, and when the processor executes the computer instruction, the electronic device executes the method described in any one of claims 1 to 8.

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