Manufacturing method of ETOX Nor flash memory

Abstract

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of an ETOX Nor flash memory. The method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a flash memory cell region and a peripheral circuit region; forming a tunneling oxide layer, a first polycrystalline silicon layer, an inter-polycrystalline silicon dielectric layer and a second polycrystalline silicon layer which are sequentially stacked from bottom to top on the semiconductor substrate at the position of the storage cell area; sequentially etching a second polycrystalline silicon layer, an inter-polycrystalline silicon dielectric layer and a second polycrystalline silicon layer in the storage cell region to form flash memory units, wherein a source region lead-out space is formed in each flash memory unit; etching the second polycrystalline silicon layer in the peripheral circuit region to form logic device polycrystalline silicon; and according to the thickness of the inter-polycrystalline silicon dielectric layer, injecting foreign ions of which the dosage is matched with the thickness of the inter-polycrystalline silicon dielectric layer into the semiconductor substrate at the source region lead-out space position to form a flash memory unit source region.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing an ETOX NOR flash memory. Background Art

[0002] ETOX Nor flash memory has a fast reading speed and is used as the main device for code storage. It is widely used in intelligent fields such as automotive electronics, IoT, and wearable devices. It has extremely high requirements for product reliability. DRB (data retention) is one of the most important performance indicators and must meet the requirement of at least 20 years. With the increase in capacity and the reduction in process nodes, the challenge to DRB is greater and it faces the risk of assessment failure.

[0003] DRB tailing rate (Vt≤7V ratio) is an important means to measure DRB performance. Big data analysis found that the data tailing rate is strongly correlated with the inter-polysilicon dielectric layer, that is, the thickness of the inter-polysilicon dielectric layer has a greater impact on the data tailing rate. The thinner the thickness, the more obvious the data tailing rate. However, the thickness of the inter-polysilicon dielectric layer in the related technology fluctuates, and it is difficult to solve its impact on the CNC tailing rate by adjusting the thickness. Summary of the invention

[0004] The present application provides a method for manufacturing an ETOX NOR flash memory, which can solve the problem of data tailing rate in the related art.

[0005] In order to solve the technical problem in the background technology, the present application provides a method for manufacturing an ETOX NOR flash memory, and the method for manufacturing an ETOX NOR flash memory comprises the following steps:

[0006] Providing a semiconductor substrate, the semiconductor substrate comprising a flash memory cell region and a peripheral circuit region;

[0007] Forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region;

[0008] In the storage cell region, a second polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer are sequentially etched to form flash memory units, wherein a source region lead-out space is formed in each of the flash memory units;

[0009] Etching the second polysilicon layer in the peripheral circuit area to form logic device polysilicon;

[0010] According to the thickness of the inter-polysilicon dielectric layer, impurity ions with a dosage matching the thickness of the inter-polysilicon dielectric layer are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory cell source region.

[0011] Optionally, the step of implanting impurity ions having a dosage matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at the spatial position where the source region is led out according to the thickness of the inter-polysilicon dielectric layer to form the flash memory cell source region comprises:

[0012] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the first target thickness, impurity ions are injected into the semiconductor substrate at the source region lead-out space position with a first injection dose to form a flash memory unit source region;

[0013] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, impurity ions are injected into the semiconductor substrate at the source region lead-out space position with a second injection dose to form a flash memory cell source region;

[0014] When the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region;

[0015] The first target thickness is greater than the second target thickness, the first implantation dose is less than the second implantation dose, and the second implantation dose is less than the third implantation dose.

[0016] Optionally, the first target thickness is 176A, and the first implantation dose range is 2.8E14atoms / cm 2 To 2.2E14atoms / cm 2 ;

[0017] The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a first implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the first target thickness, comprises:

[0018] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 176A, the 2 To 2.2E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

[0019] Optionally, the first target thickness is 176A, the second target thickness is 174A, and the second implantation dose is in the range of 2.4E14atoms / cm 2 To 3.0E14atoms / cm 2 ;

[0020] The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a second implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, comprises:

[0021] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 174A and less than 176A, the 2 To 3.0E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

[0022] Optionally, the second target thickness is 174A, and the third implantation dose is in the range of 2.6E14atoms / cm 2 To 3.2E14atoms / cm 2 ;

[0023] The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, comprises:

[0024] When the thickness of the inter-polysilicon dielectric layer is less than 174A, the 2 To 3.2E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

[0025] Optionally, the step of forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region includes:

[0026] Forming a plurality of first shallow trench isolation structures in the semiconductor substrate of the storage cell region, wherein the first shallow trench isolation structures extend in a longitudinal direction to divide the storage cell region into a plurality of columns of storage cells;

[0027] forming a tunneling oxide layer on the semiconductor substrate by a thermal oxidation process;

[0028] Depositing a first polysilicon layer on the tunneling oxide layer, and etching and removing the first polysilicon layer covering the first shallow trench isolation structure, so that the remaining first polysilicon layer in the storage cell area is the floating gate polysilicon of the flash memory, and the floating gate polysilicon extends in the longitudinal direction;

[0029] forming a second shallow trench isolation structure in the peripheral circuit region;

[0030] Forming a dielectric layer between polysilicon layers;

[0031] Etching and removing the inter-polysilicon dielectric layer and the first polysilicon layer at the location of the peripheral circuit area;

[0032] A second polysilicon layer is formed by deposition, and the second polysilicon layer fills up the gap between two adjacent columns of memory cells.

[0033] Optionally, after the step of forming a source region lead-out space in each of the flash memory cells by sequentially etching the second polysilicon layer, the inter-polysilicon dielectric layer, and the second polysilicon layer in the storage cell region to form a flash memory unit is completed, the following steps are further performed before the step of etching the second polysilicon layer in the peripheral circuit region to form polysilicon of a logic device is performed:

[0034] Impurities are implanted into the drain region of the flash memory unit through an ion implantation process to form a lightly doped drain region.

[0035] Optionally, after the step of etching the second polysilicon layer in the peripheral circuit area to form polysilicon of the logic device is completed, according to the thickness of the inter-polysilicon dielectric layer, impurity ions with a dosage matching the thickness of the inter-polysilicon dielectric layer are implanted into the semiconductor substrate at the spatial position of the source region, and before the step of forming the flash memory unit source region is performed, the following steps are further performed:

[0036] Impurities are implanted into the source and drain regions on both sides of the high-voltage device of the logic device through an ion implantation process to form low-doped source and drain regions of the high-voltage device.

[0037] The technical solution of the present application includes at least the following advantages: the present application injects impurity ions with a dosage matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at the spatial position where the source region is led out according to the thickness of the inter-polysilicon dielectric layer, so as to form a flash memory unit source region, and adjusts the dosage injected into the source region to match the polysilicon dielectric layers of different thicknesses, that is, when the polysilicon dielectric layer is thin, the injection dosage of the source region is increased to compensate for the problem of data tailing caused by the thin polysilicon dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A flow chart of a method for manufacturing an ETOX NOR flash memory provided by an embodiment of the present application is shown;

[0040] Figure 2 A schematic cross-sectional structure diagram of a provided semiconductor substrate is shown;

[0041] Figure 3 A schematic diagram of a cross-sectional structure of a device after a tunneling oxide layer is formed is shown;

[0042] Figure 4 A schematic diagram of a cross-sectional structure of a device after forming a dielectric layer between polysilicon crystals is shown;

[0043] Figure 5 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S5 is completed. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0046] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0048] Figure 1 The flowchart of the manufacturing method of ETOX NOR flash memory provided by an embodiment of the present application is shown. Figure 1 As can be seen, the manufacturing method of the ETOX Nor flash memory includes the following steps:

[0049] Step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage cell region and a peripheral circuit region.

[0050] Reference Figure 2 , which shows a cross-sectional structural schematic diagram of a provided semiconductor substrate. Figure 2 It can be seen that the semiconductor substrate 100 includes a storage cell region 110 and a peripheral circuit region 120. The peripheral circuit region 120 includes a high voltage device region and a low voltage device region. The high voltage device region includes an N-type high voltage device region HVNMOS and a P-type high voltage device region HVPMOS, and the low voltage device region includes an N-type low voltage device region LVNMOS and a P-type low voltage device region LVPMOS. Figure 2 The storage cell region 110 shown includes two different cross-sectional directions, namely a Y-direction cross-sectional direction and an X-direction cross-sectional direction.

[0051] A deep N-type well region 111 is formed by doping in the semiconductor substrate 100 at the location of the storage cell region 110 and in the semiconductor substrate 100 at the location of the high-voltage device region 120. A first high-voltage P-type well region 112 is also formed by doping in the semiconductor substrate 100 at the location of the storage cell region 110, and the depth of the first high-voltage P-type well region 112 is less than the deep N-type well region 111. A threshold voltage adjustment region 113 is also formed by doping in the semiconductor substrate 100 at the location of the storage cell region 110, and the threshold voltage adjustment region 113 extends downward from the surface of the semiconductor substrate 100, and the depth of the threshold voltage adjustment region 113 is less than the first high-voltage P-type well region 112.

[0052] A high-voltage N-type well region 121 is also formed by doping in the semiconductor substrate 100 at the location of the P-type high-voltage device region HVPMOS, and a high-voltage P-type well region 122 is also formed by doping in the semiconductor substrate 100 of the N-type high-voltage device region HVNMOS. The depths of the high-voltage N-type well region 121 and the high-voltage P-type well region 122 are both smaller than the deep N-type well region 111.

[0053] Step S2: forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer and a second polysilicon layer stacked in sequence from bottom to top on the semiconductor substrate at the location of the storage cell region.

[0054] The step S2 can be implemented by the following steps:

[0055] First, a plurality of first shallow trench isolation structures are formed in a semiconductor substrate of a storage cell region. The first shallow trench isolation structures extend in a longitudinal direction to divide the storage cell region into a plurality of columns of storage units.

[0056] Then, a tunneling oxide layer is formed on the semiconductor substrate by a thermal oxidation process, wherein the material of the tunneling oxide layer is silicon oxide. Figure 3 , which shows a schematic diagram of the cross-sectional structure of the device after the tunneling oxide layer is formed. Figure 3 It can be seen from the figure that a plurality of first shallow trench isolation structures 310 are formed in the semiconductor substrate 100 , and a tunneling oxide layer 210 is formed on the semiconductor substrate 100 .

[0057] A first polysilicon layer is then deposited on the tunneling oxide layer, and the first polysilicon layer covering the first shallow trench isolation structure is removed by etching, so that the remaining first polysilicon layer in the storage cell area is the floating gate polysilicon of the flash memory, and the floating gate polysilicon extends in the longitudinal direction.

[0058] A second shallow trench isolation structure is formed in the peripheral circuit area. The second shallow trench isolation structure in the peripheral circuit area isolates the adjacent high-voltage device area and the low-voltage device area, and isolates the adjacent N-type high-voltage device area and the P-type high-voltage device area in the high-voltage device area, and isolates the adjacent N-type low-voltage device area and the P-type low-voltage device area in the low-voltage device area. The second shallow trench isolation structure in the peripheral circuit area extends downward from the upper surface of the first polysilicon layer into the semiconductor substrate.

[0059] The inter-polysilicon dielectric layer is formed, and the material of the inter-polysilicon dielectric layer can be ONO material, that is, it includes silicon oxide, silicon nitride and silicon oxide stacked in sequence from bottom to top. The inter-polysilicon dielectric layer is covered on the surface of the first polysilicon layer according to the surface morphology of the first polysilicon layer.

[0060] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after the polysilicon inter-dielectric layer is formed. Figure 4 It can be seen that the floating gate polysilicon of the flash memory formed by the remaining first polysilicon layer 220 in the storage cell area 110 is spaced to form a gap 300, and the floating gate polysilicon extends in the longitudinal direction, that is, the Y direction. The inter-polysilicon dielectric layer 230 covers the surface of the first polysilicon layer 220 according to the surface morphology of the first polysilicon layer 220. A second shallow trench isolation structure 320 is formed in the peripheral circuit area 120. The second shallow trench isolation structure 320 in the peripheral circuit area 120 isolates the adjacent high-voltage device area and the low-voltage device area, and isolates the adjacent N-type high-voltage device area HVNMOS and P-type high-voltage device area HVPMOS in the high-voltage device area, and isolates the adjacent N-type low-voltage device area LVNMOS and P-type low-voltage device area LVPMOS in the low-voltage device area. The second shallow trench isolation structure 320 in the peripheral circuit area 120 extends downward from the upper surface of the first polysilicon layer 220 into the semiconductor substrate 100.

[0061] A low-voltage N-type well region is formed in the semiconductor substrate at the location of the P-type low-voltage device region by an ion implantation process, and the low-voltage N-type well region extends downward from the upper surface of the semiconductor substrate at the location of the P-type low-voltage device region. A low-voltage P-type well region is formed in the semiconductor substrate at the location of the N-type low-voltage device region, and the low-voltage P-type well region extends downward from the upper surface of the semiconductor substrate at the location of the N-type low-voltage device region.

[0062] The inter-polysilicon dielectric layer and the first polysilicon layer at the location of the peripheral circuit area are removed by etching.

[0063] A second polysilicon layer is deposited to fill the gap between two adjacent columns of memory cells.

[0064] Step S3: etching the second polysilicon layer, the inter-polysilicon dielectric layer and the second polysilicon layer in sequence in the storage cell region to form flash memory units, and forming a source region lead-out space in each of the flash memory units.

[0065] After step S3 is completed and before step S4 is performed, impurities are implanted into the drain region of the flash memory unit through an ion implantation process to form a lightly doped drain region.

[0066] Step S4: etching the second polysilicon layer in the peripheral circuit area to form logic device polysilicon.

[0067] The logic device polysilicon includes N-type high-voltage device polysilicon located in the N-type high-voltage device area, P-type high-voltage device polysilicon located in the P-type high-voltage device area, N-type low-voltage device polysilicon located in the N-type low-voltage device area, and P-type low-voltage device polysilicon located in the P-type low-voltage device area.

[0068] After step S4 is completed and before step S5 is performed, impurities are implanted into the source and drain regions on both sides of the polysilicon of the high-voltage logic device through an ion implantation process to form low-doped source and drain regions of the high-voltage device.

[0069] Step S5: According to the thickness of the inter-polysilicon dielectric layer, impurity ions with a dosage matching the thickness of the inter-polysilicon dielectric layer are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory cell source region.

[0070] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed, from Figure 5It can be seen that a source region lead-out space 400 is formed in the flash memory unit, impurities are injected into the drain region of the flash memory unit 110 to form a lightly doped drain 510, and the second polysilicon layer 240 is etched in the peripheral circuit area 120 to form logic device polysilicon. The logic device polysilicon includes an N-type high-voltage device polysilicon 610 located in the N-type high-voltage device area HVNMOS, a P-type high-voltage device polysilicon 320 located in the P-type high-voltage device area HVPMOS, an N-type low-voltage device polysilicon 630 located in the N-type low-voltage device area LVNMOS, and a P-type low-voltage device polysilicon 640 located in the P-type low-voltage device area LVPMOS.

[0071] A low voltage N-type well region 123 is formed in the semiconductor substrate 100 at the location of the P-type low voltage device region LVPMOS, and the low voltage N-type well region 123 extends downward from the upper surface of the semiconductor substrate 100 at the location of the P-type low voltage device region LVPMOS. A low voltage P-type well region 124 is formed in the semiconductor substrate 100 at the location of the N-type low voltage device region LVNMOS, and the low voltage P-type well region 124 extends downward from the upper surface of the semiconductor substrate 100 at the location of the N-type low voltage device region LVNMOS.

[0072] When performing step S5, the present application can be implemented by the following steps:

[0073] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the first target thickness, impurity ions are injected into the semiconductor substrate at the source region lead-out space position with a first injection dose to form a flash memory unit source region;

[0074] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, impurity ions are injected into the semiconductor substrate at the source region lead-out space position with a second injection dose to form a flash memory cell source region;

[0075] When the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region;

[0076] The first target thickness is greater than the second target thickness, the first implantation dose is less than the second implantation dose, and the second implantation dose is less than the third implantation dose.

[0077] The first target thickness is 176A, and the first implantation dose range is 2.8E14atoms / cm 2 To 2.2E14atoms / cm 2 ;

[0078] The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a first implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the first target thickness, comprises:

[0079] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 176A, the 2 To 2.2E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

[0080] The first target thickness is 176A, the second target thickness is 174A, and the second implantation dose range is 2.4E14atoms / cm 2 To 3.0E14atoms / cm 2 ;

[0081] The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a second implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, comprises:

[0082] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 174A and less than 176A, the 2 To 3.0E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

[0083] The second target thickness is 174A, and the third implant dose is in the range of 2.6E14atoms / cm 2 To 3.2E14atoms / cm 2 ;

[0084] The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, comprises:

[0085] When the thickness of the inter-polysilicon dielectric layer is less than 174A, the 2 To 3.2E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

[0086] According to the thickness of the inter-polysilicon dielectric layer, the present application injects impurity ions with a dosage matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at the spatial position where the source region is led out, so as to form a flash memory unit source region, and adjusts the dosage injected into the source region to match the polysilicon dielectric layers of different thicknesses, that is, increases the injection dosage of the source region when the polysilicon dielectric layer is thin, so as to compensate for the problem of data tailing caused by the thin polysilicon dielectric layer.

[0087] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing an ETOX NOR flash memory, characterized in that: The manufacturing method of the ETOX Nor flash memory comprises the following steps: Providing a semiconductor substrate, the semiconductor substrate comprising a flash memory cell region and a peripheral circuit region; Forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region; In the storage cell region, a second polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer are sequentially etched to form flash memory units, wherein a source region lead-out space is formed in each of the flash memory units; Etching the second polysilicon layer in the peripheral circuit area to form logic device polysilicon; According to the thickness of the inter-polysilicon dielectric layer, impurity ions with a dosage matching the thickness of the inter-polysilicon dielectric layer are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory cell source region.

2. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The step of implanting impurity ions having a dosage matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at the source region lead-out space position according to the thickness of the inter-polysilicon dielectric layer to form a flash memory cell source region comprises: When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the first target thickness, impurity ions are injected into the semiconductor substrate at the source region lead-out space position with a first injection dose to form a flash memory unit source region; When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, impurity ions are injected into the semiconductor substrate at the source region lead-out space position with a second injection dose to form a flash memory cell source region; When the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region; The first target thickness is greater than the second target thickness, the first implantation dose is less than the second implantation dose, and the second implantation dose is less than the third implantation dose.

3. The method for manufacturing the ETOX NOR flash memory according to claim 1, characterized in that: The first target thickness is 176A, and the first implantation dose range is 2.8E14atoms / cm 2 To 2.2E14atoms / cm 2 ; The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a first implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the first target thickness, comprises: When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 176A, the 2 To 2.2E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

4. The method for manufacturing the ETOX NOR flash memory according to claim 2, wherein: The first target thickness is 176A, the second target thickness is 174A, and the second implantation dose range is 2.4E14atoms / cm 2 To 3.0E14atoms / cm 2 ; The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a second implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, comprises: When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 174A and less than 176A, the 2 To 3.0E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

5. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The second target thickness is 174A, and the third implant dose is in the range of 2.6E14atoms / cm 2 To 3.2E14atoms / cm 2 ; The step of injecting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, comprises: When the thickness of the inter-polysilicon dielectric layer is less than 174A, the 2 To 3.2E14atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position of the source region to form a flash memory unit source region.

6. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The step of forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region comprises: Forming a plurality of first shallow trench isolation structures in the semiconductor substrate of the storage cell region, wherein the first shallow trench isolation structures extend in a longitudinal direction to divide the storage cell region into a plurality of columns of storage cells; forming a tunneling oxide layer on the semiconductor substrate by a thermal oxidation process; Depositing a first polysilicon layer on the tunneling oxide layer, and etching and removing the first polysilicon layer covering the first shallow trench isolation structure, so that the remaining first polysilicon layer in the storage cell area is the floating gate polysilicon of the flash memory, and the floating gate polysilicon extends in the longitudinal direction; forming a second shallow trench isolation structure in the peripheral circuit region; Forming a dielectric layer between polysilicon layers; Etching and removing the inter-polysilicon dielectric layer and the first polysilicon layer at the location of the peripheral circuit area; A second polysilicon layer is formed by deposition, and the second polysilicon layer fills up the gap between two adjacent columns of memory cells.

7. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: After the step of sequentially etching the second polysilicon layer, the inter-polysilicon dielectric layer and the second polysilicon layer in the storage cell region to form a flash memory unit, and forming a source region lead-out space in each of the flash memory units, the following steps are further performed before the step of etching the second polysilicon layer in the peripheral circuit region to form polysilicon of a logic device is performed: Impurities are implanted into the drain region of the flash memory unit through an ion implantation process to form a lightly doped drain region.

8. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: After the step of etching the second polysilicon layer in the peripheral circuit area to form polysilicon of the logic device is completed, according to the thickness of the dielectric layer between the polysilicon, the impurity ions with a dosage matching the thickness of the dielectric layer between the polysilicon are implanted into the semiconductor substrate at the spatial position of the source region, and before the step of forming the flash memory unit source region is performed, the following steps are further performed: Impurities are implanted into the source and drain regions on both sides of the high-voltage device of the logic device through an ion implantation process to form low-doped source and drain regions of the high-voltage device.

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