A memory expansion system, method and apparatus

Abstract

The application relates to a memory expansion system, method and device. The memory expansion system comprises a plurality of memory modules, a host module for accessing the memory modules according to system operation requirements, a signal exchange module corresponding to the memory modules, the signal exchange module being used for establishing an access link between the host module and the memory modules, so that the host module accesses the memory modules, an interconnection control module connected to the host module and the signal exchange module, the interconnection control module being used for determining a current interconnection topology network between the host module and the signal exchange module and a current bandwidth of the host module, and being used for monitoring a real-time demand bandwidth of the host module in real time, and selecting the signal exchange module connected to the host module based on the current bandwidth and the real-time demand bandwidth, so as to re-allocate the accessed memory modules to the host module. Compared with the prior art, the application can dynamically adjust the operation memory allocated on each host module in real time.

Description

Technical Field

[0001] This application relates to the field of server interconnect technology, and in particular to a memory expansion system, method and apparatus. Background Technology

[0002] With the rapid development of information technology, the demand for memory capacity and performance in computer systems is constantly increasing. In modern computing environments, data processing volume is rising exponentially, and various complex applications, such as big data analysis, artificial intelligence, and high-performance computing, have increasingly higher requirements for memory. Especially in recent years, the number of processor cores has continued to increase. For example, ARM (Advanced RISC Machine) architecture processors have as many as 256 cores. The memory capacity and bandwidth of each core are limited by traditional local DDR (Double Data Rate) bus memory, which has severely limited the performance of the processor. The growth rate of CPU (Central Processing Unit) core count is faster than the growth rate of memory bandwidth and capacity. The memory bandwidth and capacity per core have become a bottleneck, prompting applications to demand memory expansion (flexibility).

[0003] Currently, due to the low memory utilization rate in data centers, resulting in idle memory resources, it is usually necessary to decouple memory resources through memory pooling technology to improve the utilization rate of data center memory resources. However, the traditional method of expanding memory by adding memory modules or using memory expansion cards is limited by the specific structure of the motherboard and interface, resulting in poor flexibility, low expansion efficiency, and inability to meet the ever-increasing demand. Summary of the Invention

[0004] Therefore, it is necessary to provide a memory expansion system, method, apparatus, device, and storage medium that is highly flexible and has high expansion efficiency to address the above-mentioned technical problems.

[0005] In a first aspect, the present invention provides a memory expansion system, the system comprising:

[0006] Multiple memory modules;

[0007] The host module is used to access the memory module according to system operation requirements;

[0008] A signal exchange module is provided, which is configured in a one-to-one correspondence with the memory module. The signal exchange module is used to establish an access link between the host module and the memory module, enabling the host module to access the memory module.

[0009] An interconnection control module is connected to both the host module and the signal exchange module. The interconnection control module is used to determine the current interconnection topology between the host module and the signal exchange module and the current bandwidth of the host module; and to monitor the real-time bandwidth demand of the host module in real time, and select the signal exchange module connected to the host module based on the current bandwidth and the real-time bandwidth demand, so as to reallocate the memory module accessed by the host module.

[0010] In one embodiment, the host module includes:

[0011] Multiple processors are used to access different memory modules according to system operation requirements during system operation; the multiple processors communicate with each other through a high-speed interconnect bus;

[0012] Multiple connection ports are provided for connecting the processor and the signal exchange module; the processor is connected to at least one connection port.

[0013] The first interconnect control terminal is connected to the interconnect control module and is used to realize data transmission between the processor and the interconnect control module.

[0014] In one embodiment, the signal switching module has multiple selectable uplink ports, a downlink port connected to the memory module, and a second interconnect control terminal connected to the interconnect control module. Each uplink port of the signal switching module is connected to any connection port of a different host module through an interface module. When the uplink port of the signal switching module is selected, an access link is established between the host module connected to the uplink port and the corresponding memory module, enabling the host module to access the corresponding memory module.

[0015] The processor is also used to respond to access requests from the interconnection control module and encapsulate Ethernet data packets based on the current network topology information; the current network topology information includes the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module;

[0016] In one embodiment, the interconnection control module includes:

[0017] The data parsing unit is used to parse the received Ethernet data packets to obtain the current network topology information, and to determine the current connection status between the connection port and the signal uplink port and the current bandwidth when the host module's processor accesses the memory module based on the host module's host ID, host module's processor ID, host module's port ID, and interface module's interface ID.

[0018] The data monitoring unit is used to monitor the running status of the processor of the host module in real time and obtain the real-time bandwidth requirements of the host module.

[0019] A memory allocation unit is used to determine the bandwidth difference of the processor based on the real-time required bandwidth and the current bandwidth, and to add or reduce the allocated memory modules for the host module based on the bandwidth difference, and to determine the added or reduced allocated memory modules as mobile memory modules.

[0020] The gating control unit is used to select one of the signal uplink ports of the signal exchange module connected to the motor memory module, so as to increase or decrease the number of memory modules accessed by the host module.

[0021] In one embodiment, it further includes:

[0022] The protocol switching module is used to enable the host module to access the memory module; the protocol switching module has an uplink switching port and a downlink switching port, the uplink switching port is connected to the downlink switching port in a one-to-one correspondence, the downlink switching port is connected to the memory module in a one-to-one correspondence, and the convergence ratio of the uplink switching port and the downlink switching port is 1:1.

[0023] In a second aspect, the present invention provides a memory expansion method applied to an interconnect control module, wherein the interconnect control module is connected to at least one host module and multiple signal exchange modules respectively, and the multiple signal exchange modules are connected to multiple memory modules in a one-to-one correspondence; the method includes:

[0024] Obtain the Ethernet data packets from the host module;

[0025] The current network topology information of the host module and the signal exchange module is determined based on the Ethernet data packet, and the current signal exchange module that is exchanging signals with the host module at the current moment is determined based on the current network topology information;

[0026] Monitor the real-time bandwidth requirements of the host module.

[0027] Based on the current bandwidth of the host module and the real-time bandwidth requirement, the signal switching module connected to the host module is selected to reallocate the memory module to be accessed by the host module.

[0028] In one embodiment, the Ethernet data packet is encapsulated based on the current network topology information of the host module, the current network topology information including the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module;

[0029] The step of obtaining the Ethernet data packets of the host module includes:

[0030] Access each host module of the memory expansion system via IP address and send data acquisition requests to the host module;

[0031] Receive and parse the Ethernet data packets sent by the host module to obtain the host module's host ID, host module's processor ID, host module's port ID, interface module's interface ID, and the host module's current bandwidth.

[0032] In one embodiment, the host module has multiple connection ports, each of the signal switching modules has a downlink signal port and multiple uplink signal ports, the downlink signal ports are connected to the memory modules one by one, and the multiple uplink signal ports are connected to any connection port of different host modules respectively.

[0033] The step of determining the current network topology information of the host module and the signal exchange module based on the Ethernet data packet, and determining the current signal exchange module that is currently exchanging signals with the host module based on the current network topology information, includes:

[0034] The current connection status between the connection port and the signal uplink port, as well as the current bandwidth when the host module's processor accesses the memory module, are determined based on the host module's host ID, host module's processor ID, host module's port ID, and interface module's interface ID.

[0035] The current signal exchange module that is exchanging signals with the host module at the current moment is determined based on the current connection status and the current bandwidth.

[0036] In one embodiment, the step of selecting a signal switching module connected to the host module based on the host module's current bandwidth and the real-time bandwidth demand to reallocate access to a memory module for the host module includes:

[0037] The bandwidth difference of the host module's processor is determined based on the real-time required bandwidth and the current bandwidth. The memory modules allocated to the host module are increased or decreased based on the bandwidth difference, and the increased or decreased memory modules are identified as mobile memory modules.

[0038] Select one of the signal uplink ports of the signal exchange module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module.

[0039] Thirdly, the present invention provides a memory expansion device applied to an interconnect control module, wherein the interconnect control module is connected to at least one host module and multiple signal exchange modules respectively, and the multiple signal exchange modules are connected to multiple memory modules in a one-to-one correspondence; the device includes:

[0040] A data acquisition module is used to acquire Ethernet data packets from the host module;

[0041] An information construction module is used to determine the current network topology information between the host module and the signal exchange module based on the Ethernet data packet, and to determine the current signal exchange module that is currently exchanging signals with the host module based on the current network topology information.

[0042] The monitoring module is used to monitor the real-time bandwidth requirements of the host module.

[0043] A memory expansion module is used to select a signal switching module connected to the host module based on the host module's current bandwidth and the real-time bandwidth requirement, so as to reallocate access to memory modules for the host module.

[0044] Fourthly, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method described above.

[0045] Fifthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0046] The aforementioned memory expansion system, method, and apparatus acquire Ethernet data packets from the host module through an interconnection control module. Based on the Ethernet data packets, they determine the current network topology information between the host module and the signal exchange module. Based on this network topology information, they identify the current signal exchange module exchanging signals with the host module at the current moment, thus determining the host module's current operating status. Next, by monitoring the host module's real-time bandwidth requirements, they select the signal exchange module connected to the host module based on the current bandwidth and the real-time bandwidth requirements, thereby reallocating memory modules for the host module to access. In this way, the allocated memory on each host module can be dynamically adjusted in real-time during operation, facilitating the expansion of memory bandwidth and capacity, meeting the needs of elastic memory expansion, and solving the problem of low memory utilization in certain situations. Memory pooling decouples memory resources, improves the utilization rate of data center memory resources, and reduces the overall cost of the data center. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a block diagram of a memory expansion system in one embodiment;

[0049] Figure 2 This is a structural block diagram of the host module in one embodiment;

[0050] Figure 3 This is a structural block diagram of the interconnection control module in one embodiment;

[0051] Figure 4 This is a flowchart illustrating a memory expansion method in one embodiment;

[0052] Figure 5 This is a block diagram of a memory expansion system based on CXL bus technology in an application example.

[0053] Figure 6 This is a block diagram of a memory expansion system based on CXL bus technology in Example 1 of an application instance.

[0054] Figure 7 This is a block diagram of a memory expansion system based on CXL bus technology in Example 2 of an application instance.

[0055] Figure 8 This is a structural block diagram of a memory expansion device in one embodiment;

[0056] Figure 9 This is an internal structural diagram of a computer device in one embodiment.

[0057] Explanation of reference numerals in the attached figures:

[0058] 101-Memory module, 102-Host module, 103-Signal exchange module, 104-Interconnection control module, 105-Interface module, 105-Protocol exchange module;

[0059] 201 - Processor; 202 - Connection port;

[0060] 301 - Data parsing unit, 302 - Data monitoring unit, 303 - Memory allocation unit, 304 - Selection control unit. Detailed Implementation

[0061] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0063] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0064] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0065] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0066] As described in the background section, existing methods for expanding memory by adding memory modules require designing more memory slots on the motherboard to accommodate more memory modules, and using memory expansion cards requires connecting to the motherboard via specific interfaces and installing memory modules on the expansion card to increase memory capacity using the server's internal space. Both of these methods are limited by the specific structure of the server and motherboard, as well as the support of the memory controller, thus restricting capacity and bandwidth expansion. Furthermore, the bandwidth between the host node and the memory expansion node is fixed; changing the bandwidth requires powering off both nodes, compromising service continuity and flexibility. Moreover, when application software (such as databases or supercomputing) needs to allocate more memory units to the host node, a bandwidth bottleneck exists, preventing the full realization of the performance advantages of expanded memory.

[0067] Based on the above reasons, the present invention provides a memory expansion scheme that can adjust the bandwidth of each host in real time without interrupting the system according to the actual system performance requirements, so as to realize the flexible access and use of the memory on the downlink memory module by the processor on the uplink host module.

[0068] In one embodiment, such as Figure 1 As shown, a memory expansion system is provided, including multiple memory modules 101, a host module 102, a signal exchange module 103, and an interconnection control module 104.

[0069] The memory module 101 provides bandwidth (or RAM) for the host module 102, ensuring its stable operation. The host module 102 accesses the memory on the memory module 101 according to system requirements to run applications. The signal exchange module 103 establishes an access link between the host module 102 and the memory module 101, facilitating access and use of the memory on the memory module 101 by the host module 102 when running application software. The interconnection control module 104 is used to determine the current interconnection topology between the host module 102 and the signal exchange module 103 and the current bandwidth of the host module 102; and to monitor the real-time bandwidth demand of the host module 102 in real time, and select the signal exchange module 103 connected to the host module 102 based on the current bandwidth and the real-time bandwidth demand, so as to reallocate the memory module 101 accessed by the host module 102; that is, by analyzing the current interconnection topology, current bandwidth and real-time bandwidth demand, when the host module 102 needs more bandwidth (or memory) or less bandwidth, the module controls the selection of the signal exchange module 103, so that the host module 102 can access and use more or less memory modules 101 according to the system's operating requirements, so as to optimize resource allocation.

[0070] The signal exchange module 103 is configured to correspond to the memory module 101, meaning that multiple signal exchange modules 103 are configured. Typically, the signal exchange module 103 and the memory module 101 are configured in a one-to-one correspondence. The host module 102 can be configured in one or more ways, so that a host module 102 can access and use the memory on one or more memory modules 101 through the access link formed by one or more signal exchange modules 103. This allows for flexible adjustment of the bandwidth of the host module 102 as needed, thereby changing the bandwidth of the host module 102, solving the problem of fixed bandwidth bottleneck, fully leveraging the performance advantages of extended memory, achieving link redundancy between different host modules 102 and memory modules 101, and improving the high availability of the system.

[0071] The interconnection control module 104 is connected to the host module 102 to obtain the current bandwidth of the host module 102 and the connection and operation status between the host module 102 and the signal exchange module 103, thereby constructing the current interconnection topology network. The interconnection control module 104 is also connected to the signal exchange module 103 to send control commands or signals to the signal exchange module 103 when it is necessary to adjust the bandwidth of the host module 102, so as to turn the signal exchange module 103 on or off, thereby enabling the host module 102 to access the memory module 101 as needed.

[0072] The access link refers to the signal transmission channel formed when the host module 102 accesses the memory module 101.

[0073] The current interconnection topology refers to the communication connection between the host module 102 and the signal exchange module 103 at the current moment. The current bandwidth refers to the bandwidth or memory used by the host module 102 while running the application at the current moment.

[0074] For example, in the case of arranging multiple host modules 102, four signal switching modules 103 and four memory modules 101.

[0075] If, at a certain moment, a host module 102 connects to the first and third memory modules 101 via the first and third signal exchange modules 103 respectively, so that the host module 102 can jointly access and use the two downlink memory modules 101 through these two signal exchange modules 103, the interconnection control module 104 determines which two signal exchange modules 103 and their corresponding memory modules 101 are currently connected to the host module 102 by obtaining the number and access status of the host module 102's access to the memory modules 101. This allows the current interconnection topology to be constructed, and the current bandwidth of the host module 102 to be determined based on these two memory modules 101. That is, the first and third memory modules 101 provide memory for the operation of the host module 102. The interconnection control module 104 determines, through relevant information sent by the host module 102, that the host module 102 is connected to the first and third signal exchange modules 103 and the first and third memory modules 101, thereby constructing the current interconnection topology and determining the current bandwidth as the sum of the bandwidth jointly provided by the first and third memory modules 101.

[0076] If, at the next moment, the interconnection control module 104 detects that the application running on the host module 102 requires more bandwidth or running memory (i.e., determines the real-time bandwidth requirement), then, based on the current interconnection topology, it determines the memory module 101 (such as the fourth memory module 101) that can be allocated to the host module 102, and sends this instruction to the fourth signal exchange module 103 to control the fourth signal exchange module 103 to connect, so that the fourth memory module 101 can provide memory for the host module 102. Conversely, when the interconnection control module 104 detects that the application running on the host module 102 requires less memory or bandwidth, it can also control the corresponding signal exchange module 103 to disconnect based on the current interconnection topology, so as to free up more memory modules 101 for other host modules 102 to use, thereby achieving the purpose of dynamic adjustment of the bandwidth of the host module 102.

[0077] It is understood that the data of the host module 102, signal exchange module 103 and memory module 101 described above are merely an example and are not intended to limit this embodiment; in specific implementation, the number of each module can be set according to actual needs to achieve the purpose of memory expansion.

[0078] In the aforementioned memory expansion system, the interconnection control module 104 monitors the operation of the host module 102, thereby determining the bandwidth requirements of the host module 102 in real time. Combined with the signal switching module 103 that controls the current interconnection topology network, the bandwidth between each host module 102 can be flexibly configured according to actual needs. This is beneficial for meeting the needs of elastic memory expansion. Furthermore, the entire process does not require power outages or service interruptions, ensuring the continuity of the service process.

[0079] In one embodiment, such as Figure 2 As shown, the host module 102 includes multiple processors 201, multiple connection ports 202, and a first interconnect control terminal. The processors 201 are used to access different memory modules 101 according to system operation requirements during system operation, ensuring the normal and stable operation of applications running on the corresponding processors 201. The connection ports 202 are used to connect the processors 201 and the signal exchange module 103, ensuring that the processors 201 can access and use the memory on the memory modules 101. The first interconnect control terminal is used to implement data transmission between the processors 201 and the interconnect control module 104.

[0080] The connection port 202 is connected to the signal exchange module 103 through the interface module 105 to establish a connection between the processor 201 and the signal exchange module 103, thereby establishing an access link between the processor 201 and the memory module 101.

[0081] The uplink signal of the interface module 105 is connected to the connection port 202 of the host module 102, and the downlink signal is connected to the signal exchange module 103 to establish a connection between the host module 102 and the signal exchange module 103.

[0082] The processors 201 communicate and expand with each other via a high-speed interconnect bus, and each processor 201 is connected to at least one connection port 202. Specifically, the processor 201 can connect to one or more connection ports 202 according to actual operational needs, to route the processor 201's signals to the signal exchange module 103, enabling the processor 201 to access the memory of one or more memory modules 101 in parallel. The processor 201 is also used to respond to access requests from the interconnect control module 104 by encapsulating Ethernet data packets based on the current network topology information.

[0083] Ethernet packets refer to the units of data transmission in computer networks. In order to ensure that all computers sharing network resources can use the network fairly and quickly, the transmitted data is divided into several small blocks for transmission.

[0084] The current network topology information refers to the identification information of each module corresponding to the current interconnection topology network lock, in order to determine the connection and correspondence between the modules. The current network topology information includes the host ID of host module 102, the processor ID of host module 102, the port ID of host module 102, the interface ID of interface module 105, and the current bandwidth of host module 102.

[0085] Among them, the host ID is used to distinguish different host modules 102 in the whole system; the processor ID is used to identify the processor 201 inside the host module 102; the port ID is used to identify the connection port 202 to which the processor 201 is connected; the interface ID is used to identify the physical cable interconnection relationship between the connection port 202 of the host module 102 and the signal exchange module 103; and the current bandwidth is used to identify the interconnection information of signal pairs between the host module 102 and the interface module 105, which can be 4 pairs, 8 pairs, 16 pairs, etc.

[0086] The first interconnect control terminal is connected to the interconnect control module 104 to realize data transmission between the interconnect control module 104 and the host module 102 (or processor 201). Normally, the data transmission between the interconnect control module 104 and the host module 102 is bidirectional, including the interconnect control module 104 sending access requests to the host module 102 through the first interconnect control terminal and the host module 102 sending running data to the interconnect control module 104 through the first interconnect control terminal.

[0087] For example, with Figure 1Taking the illustrated structure as an example, the host IDs of host modules 102 are sequentially recorded as Z1 to ZN, where Z1 represents the first host module 102 and ZN represents the Nth host module 102; the processor IDs of processors 201 are sequentially recorded as C1.1 to CN.n, where C1.1 represents the first processor 201 of the first host module 102 and CN.n represents the nth processor 201 of the Nth host module 102; the port IDs are sequentially recorded as CXL1.1 to CXLN.n (in the case where there is a one-to-one correspondence between processors 201 and connection ports 202), where CXL1.1 represents the first connection port 202 of the first host module 102 and CXLN.n represents the nth connection port 202 of the Nth host module 102; and the interface IDs of interface modules 105 are sequentially recorded as J1 to JM, where J1 represents the first interface module 105 and JM represents the Mth interface module 105.

[0088] When the application runs on the first processor 201 (C1.1) of the first host module 102 (Z1), C1.1 connects to the corresponding interface module 105 (J1) through the first connection port 202 (CXL1.1) connected to it, and then accesses the corresponding memory module 101 through the signal exchange module 103 connected to J1, thereby realizing access and use of the memory on the memory module 101; during this process, C1.1 can respond to the access request of the interconnection control module 104 and send the host ID (i.e., Z1) of the host module 102 to which C1.1 belongs. The processor ID of C1.1 (i.e., C1.1), the port ID of the connection port 202 connected to C1.1 (i.e., CXL1.1), the interface ID of the interface module 105 connected to CXL1.1 (i.e., J1), and the current bandwidth of C1.1 are encapsulated into an Ethernet data packet and sent to the interconnection control module 104 via the first interconnection control terminal. At the same time, when the bandwidth requirement of C1.1 changes, C1.1 can respond to the listening request of the interconnection control module 104 and send the real-time bandwidth requirement to the interconnection control module 104 so that the interconnection control module 104 can perform data processing.

[0089] In this embodiment, by setting multiple processors 201 and multiple connection ports 202, multiple external connection ports can be provided for the host module 102, so as to dynamically adjust the connection between the connection port 202 and the interface module 105 during operation and realize dynamic adjustment of bandwidth.

[0090] In one embodiment, such as Figure 1As shown, the signal switching module 103 has multiple selectable uplink ports, one downlink port, and a second interconnection control terminal. The uplink ports are used to connect to the connection port 202 of the host module 102 via the interface module 105; the downlink ports are used to connect to the corresponding storage modules to form an access link between the host module 102 and the storage modules. The second interconnection control terminal is used for data transmission with the interconnection control module 104.

[0091] Each signal uplink port is connected to any connection port 202 of a different host module 102 via an interface module 105. When the signal uplink port of the signal switching module 103 is selected, an access link is established between the host module 102 connected to that signal uplink port and the corresponding memory module 101, enabling the host module 102 to access the corresponding memory module 101.

[0092] The second interconnection control terminal is connected to the interconnection control module 104 to realize data transmission between the interconnection control module 104 and the signal transmission module. Normally, the data transmission between the interconnection control module 104 and the signal exchange module 103 is unidirectional. The interconnection control module 104 sends control commands to the signal transmission module through the second interconnection control terminal to control the selection of the signal uplink port.

[0093] For example, taking the signal exchange module 103 as having two signal uplink ports, each signal uplink port is connected to different connection ports 202 of different host modules 102 through an interface module 105. The interconnection control module 104 controls one of the two signal uplink ports to be selected, so that the processor 201 connected to the selected signal uplink port can access the memory module 101, while the processor 201 connected to the unselected signal uplink port cannot access the memory module 101, so as to achieve the purpose of memory allocation.

[0094] In this embodiment, by setting multiple uplink ports on the signal switching module 103, and by enabling one of the multiple uplink ports of each signal switching module 103 to be selected, the host module 102 connected to the signal switching module 103 can be dynamically adjusted to achieve the purpose of dynamically adjusting the bandwidth of the host module 102 and optimizing the bandwidth configuration.

[0095] In one embodiment, such as Figure 3 As shown, the interconnection control module 104 includes a data parsing unit 301, a data monitoring unit 302, a memory allocation unit 303, and a gating control unit 305.

[0096] The data parsing unit 301 parses received Ethernet packets to obtain current network topology information. Based on the host ID, processor ID, port ID, and interface ID of the host module 102, it determines the current connection status between the connection port 202 and the signal uplink port, as well as the current bandwidth when the processor 201 of the host module 102 accesses the memory module 101. The data monitoring unit 302 monitors the operating status of the processor 201 of the host module 102 in real time to obtain the real-time bandwidth requirement of the host module 102. The memory allocation unit 303 determines the bandwidth difference of the processor 201 based on the real-time bandwidth requirement and the current bandwidth. Based on the bandwidth difference, it adds or removes the allocated memory modules 101 for the host module 102, and identifies the added or removed memory modules 101 as mobile memory modules 101. The gating control unit 305 selects one of the signal uplink ports of the signal switching module 103 connected to the mobile memory module 101 to increase or decrease the number of memory modules 101 accessed by the host module 102.

[0097] The current connection status refers to the connection relationship between the processor 201 of the host module 102 and the connection port 202, the connection port 202 and the interface module 105, and the selection status between the interface module 105 and each signal uplink port at the current moment.

[0098] The real-time demand bandwidth refers to the bandwidth required to ensure the processor 201 can execute the application when the application running on the processor 201 of the host module 102 changes. The bandwidth difference is the difference between the current bandwidth and the actual demand bandwidth, i.e., the actual demand bandwidth minus the current bandwidth. The bandwidth difference can be positive or negative. When the bandwidth difference is positive, it means that the host module 102 needs more bandwidth, and more memory modules 101 need to be allocated for the host module 102 to use and access. Conversely, when the bandwidth difference is negative, it means that there is spare memory on the host module 102 that can be released for other host modules 102 to access, and less memory needs to be allocated. This achieves the purpose of dynamic adjustment.

[0099] Among them, the mobile memory module 101 refers to the memory module 101 that needs to be added or removed when the bandwidth requirements of the host module 102 change.

[0100] For example, in the case where a host module 102 corresponds to multiple signal exchange modules 103 and multiple memory modules 101; taking one host module 102, four signal exchange modules 103, four memory modules 101, and each signal exchange module 103 having two uplink ports as an example, the two uplink ports of the first signal exchange module 103 are respectively denoted as the first uplink port (UP1.1) and the second uplink port (UP1.2), the uplink ports of the second signal exchange module 103 are UP2.1 and UP2.2, and so on. The first to fourth connection ports CXL1.1~CXL1.4 of the processor 201 (C1.1) of the host module 102 (Z1) are connected to UP1.1, UP2.1, UP3.1 and UP4.1 through J1, J3, J5 and J7 respectively. At time T1, the first memory module 101 is allocated to the host module 102 for access, i.e., UP1.1 is selected. At this time, the data parsing unit 301 can obtain the host ID, processor ID, port ID, and interface ID by parsing the Ethernet data packet to determine the topology at time T1, and can determine the current bandwidth based on the data of the accessed memory module 101. Subsequently, the data monitoring unit 302 continuously monitors the operating status of the host module 102 (Z1). If, at time T2, the application running on the host module 102 (Z1) needs to allocate more bandwidth, such as requiring the bandwidth provided by the two memory modules 101, i.e., the real-time bandwidth requirement is the bandwidth that the two memory modules 101 can provide; at this time, the memory allocation unit 303 will determine the bandwidth difference (i.e., the bandwidth provided by one memory module 101), and determine the need to add bandwidth for one port based on the bandwidth difference. Then, it will find the free memory module 101, signal exchange module 103 and corresponding interface module 105 among the remaining three interface modules 105 (e.g., to allocate the second memory module 101 to the host module 102 at this time). The gating control unit 305 controls the UP2.1 on the second signal exchange module 103 connected to the host module 102 to be turned on, so that the first memory module 101 and the second memory module 101 provide running memory for the host module 102 in parallel.

[0101] In this embodiment, by setting the data parsing unit 301 to construct the interconnection topology network at the current moment, the connection relationship between the connection port 202 of the host module 102 and the interface module 105 can be determined. Based on this, it can be determined whether the host module 102 needs to allocate more connection ports 202 to access memory or needs to reduce the number of connection ports 202 in the current state. This can achieve link redundancy between different host nodes and the memory module 101 and improve the high availability of the system.

[0102] In one embodiment, such as Figure 1 As shown, the memory expansion system also includes a protocol switching module 106.

[0103] The protocol switching module 106 is used to enable the host module 102 to access the memory module 101. The protocol switching module 106 has an uplink switching port and a downlink switching port. The uplink switching port is connected to the downlink switching port in a one-to-one correspondence, and the downlink switching port is connected to the memory module 101 in a one-to-one correspondence, ensuring that the processor 201 on the uplink host module 102 can access and use the memory on the downlink memory module 101. In this embodiment, the convergence ratio of the uplink switching port to the downlink switching port is 1:1, meaning that data is transmitted in a one-to-one ratio during data transmission.

[0104] In this embodiment, by setting a protocol switching unit between the signal switching module 103 and the memory module 101, high-bandwidth, low-latency data transmission can be provided for both, thereby achieving high-speed data transmission and resource sharing and improving access efficiency.

[0105] In one embodiment, such as Figure 4 As shown, a memory expansion method is provided, and the method is described using the interconnection control module of the above embodiment as an example. In specific implementation, the interconnection control module can be implemented based on a controller, server, or other device or equipment capable of performing data processing and calculation.

[0106] The above memory expansion method includes the following steps S401 to S404. Wherein:

[0107] Step S401: Obtain the Ethernet data packets of the host module.

[0108] In this context, an Ethernet packet refers to a transmission unit where data is divided into smaller chunks for transmission to ensure fair and rapid network access for all computers sharing network resources. Specifically, in this embodiment, an Ethernet packet refers to a data packet encapsulated by the host module based on the current network topology information.

[0109] For example, when the host module responds to the acquisition request of the interconnection control module, it encapsulates the current network topology information into an Ethernet data packet and sends it to the interconnection control module, so that the interconnection control module can obtain the Ethernet data packet from the first interconnection control terminal of the host module.

[0110] Step S402: Determine the current network topology information of the host module and the signal exchange module based on the Ethernet data packet, and determine the current signal exchange module that is exchanging signals with the host module at the current moment based on the current network topology information.

[0111] The current network topology information refers to the identification information of each module corresponding to the current interconnection topology network lock, in order to determine the connection and correspondence between the modules. The current network topology information includes the host module's host ID, the host module's processor ID, the host module's port ID, the interface module's interface ID, and the host module's current bandwidth.

[0112] The current signal switching module refers to the signal switching module that connects to the host module and forms an access link between the host module and the memory module at the moment the interconnection control module acquires Ethernet packets. For example, at time T1, the interconnection control module acquires Ethernet packets from the host module Z1. At this time, the connection port 202 (CXL1.1) of the host module Z1 is connected to the uplink port UP1.1 of a signal switching module through interface J1. This signal switching module is the current signal switching module.

[0113] For example, after acquiring an Ethernet data packet, the interconnection control module can parse the Ethernet data packet and determine the current network topology information between the host module and the signal exchange module based on the parsed Ethernet data packet, that is, determine the connection relationship between the host module and the signal exchange module; then, the interconnection control module determines the current signal exchange module that is exchanging signals with the host module at the current moment based on the current network topology information, so as to further determine which memory modules provide running memory for which host modules at the current moment.

[0114] Step S403: Monitor the real-time bandwidth requirements of the host module.

[0115] Real-time bandwidth requirements refer to the bandwidth required to ensure the processor can execute applications when the applications running on the host module's processor change.

[0116] For example, during the operation of the host module, the interconnection control module monitors the host module's operation in real time to obtain the host module's real-time bandwidth requirements. Specifically, during operation, the host module can determine how much bandwidth is needed at a certain moment to ensure the normal and stable operation of the applications running on it, and encapsulates the required bandwidth into Ethernet packets in the same way as the current network topology information and sends them to the interconnection control module, enabling the interconnection control module to monitor the host module's real-time bandwidth requirements.

[0117] Step S404: Based on the current bandwidth and real-time bandwidth requirements, select the signal switching module connected to the host module to reallocate the memory module to be accessed by the host module.

[0118] Among them, selecting the signal exchange module connected to the host module refers to selecting the signal exchange module connected to the host module according to the real-time needs of the host module, so as to change the number of memory modules accessed by the host module and thus adjust the bandwidth.

[0119] For example, the interconnection control module determines the number of memory modules needed after the bandwidth change based on the current bandwidth and the real-time bandwidth demand. Based on the required number of memory modules and the memory modules that are currently communicating with the host module, it determines which memory modules need to be added or removed. Based on this, it selects the signal exchange module connected to the host module to reallocate the memory modules that the host module can access.

[0120] The aforementioned memory expansion method, by acquiring Ethernet data packets from the host module, determines the current network topology information between the host module and the signal exchange module based on the Ethernet data packets, and identifies the current signal exchange module exchanging signals with the host module at the current moment based on the current network topology information, thus determining the operating status of the host module at the current moment. Next, by monitoring the real-time bandwidth demand of the host module, the method selects the signal exchange module connected to the host module based on the current bandwidth and the real-time bandwidth demand, thereby reallocating memory modules for the host module to access. In this way, the allocated memory on each host module can be dynamically adjusted in real time during the operation of the host module, which is beneficial for expanding memory bandwidth and capacity, meeting the needs of elastic memory expansion. Simultaneously, it can also solve the problem of low memory utilization in certain situations, achieving memory pooling to decouple memory resources, improving the utilization rate of data center memory resources, and reducing the overall cost of the data center.

[0121] In one embodiment, step S401 involves obtaining Ethernet data packets from the host module. These Ethernet data packets are encapsulated based on the host module's current network topology information, which includes the host module's host ID, processor ID, port ID, interface ID, and current bandwidth. Step S401 includes:

[0122] Access each host module of the memory expansion system via IP address and send data acquisition requests to the host module; receive and parse Ethernet packets sent by the host module to obtain the host ID, processor ID, port ID, interface ID, and current bandwidth of the host module.

[0123] Among them, IP address (Internet Protocol Address) is the logical address assigned to each host module on the Internet to mask the differences in physical addresses so that the interconnection control module can query and access each host module.

[0124] Among them, a data acquisition request refers to a request or instruction from the host module to send Ethernet data packets to the interconnection control module.

[0125] Parsing Ethernet packets refers to extracting the current network topology information from Ethernet packets to obtain the host ID, processor ID, port ID, interface ID, and current bandwidth.

[0126] For example, the interconnection control module accesses each host module through the IP address corresponding to each host module in the memory expansion system, and sends a data acquisition request to each host module after the access is established; subsequently, after the host module responds to the data acquisition request and sends an Ethernet data packet to the interconnection control module, the Ethernet data packet is received, and the host ID, processor ID, port ID, interface ID, and current bandwidth of the host module are extracted from the Ethernet data packet.

[0127] In this embodiment, by accessing and acquiring data from the host module, the operating data of the host module at the current moment can be obtained, so as to subsequently construct the interconnection topology network between the host module and the signal exchange module.

[0128] In one embodiment, the host module has multiple connection ports, and each signal switching module has a downlink port and multiple uplink ports. The downlink ports are connected to memory modules one-to-one, and the multiple uplink ports are connected to any connection port of different host modules. In step S402, the current network topology information between the host module and the signal switching modules is determined based on Ethernet data packets. The current signal switching module that is currently exchanging signals with the host module based on the current network topology information includes:

[0129] The current connection status between the connection port and the signal uplink port, as well as the current bandwidth when the host module's processor accesses the memory module, are determined based on the host module's host ID, host module's processor ID, host module's port ID, and interface module's interface ID. Based on the current connection status and current bandwidth, the current signal exchange module that is exchanging signals with the host module at the current moment is determined.

[0130] For example, the interconnection control module determines the corresponding connection relationship between the connection port and the signal uplink port at the current moment based on the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module, so as to determine the current connection state between the connection port and the signal uplink port, and determine the current bandwidth when the host module's processor accesses the memory module; then, the interconnection control module determines the current signal exchange module that is exchanging signals with the host module at the current moment based on the current connection state and the current bandwidth, so as to determine the corresponding memory module.

[0131] In this embodiment, by determining the current connection status between the host module and the signal exchange module and the current bandwidth of the host module, the memory module that provides running memory for the host module can be further determined, so as to achieve the purpose of dynamic bandwidth adjustment with minimal adjustment cost in subsequent adjustment process.

[0132] In one embodiment, step S404, which involves selecting a signal switching module connected to the host module based on the current bandwidth and real-time bandwidth demand, to reallocate access to a memory module for the host module, includes:

[0133] The bandwidth difference between the host module's processor and the current bandwidth is determined based on the real-time required bandwidth. The host module is then allocated memory modules based on this bandwidth difference, and these allocated memory modules are designated as mobile memory modules. The uplink port of the signal exchange module connected to the mobile memory module is selected to increase or decrease the number of memory modules accessed by the host module.

[0134] Among them, the signal uplink port of the signal exchange module connected to the mobile memory module refers to the fact that only one signal uplink port of the same signal exchange module can communicate with the connection port of a host module through the corresponding interface module at one time. That is, only one host module is allowed to access a memory module. However, this does not mean that a signal exchange module can only be connected to one host module. It can be connected to multiple different host modules through different signal uplink ports. It just means that during the operation of the host module, only one signal uplink port is allowed to be connected, so that the corresponding memory module can only be accessed or used by one host module to avoid conflicts.

[0135] For example, the interconnect control module determines the bandwidth difference between the host module's processor and the real-time required bandwidth and the current bandwidth. Based on the bandwidth difference, it determines whether to increase or decrease the bandwidth for the host module, and then increases or decreases the allocated memory modules for the host module, designating the increased or decreased memory modules as mobile memory modules. Subsequently, the interconnect control module selects an uplink port of the signal switching module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module. The specific process of memory module reallocation by the interconnect control module in this embodiment can be found in the description of the interconnect control module in the above embodiment, and will not be repeated here.

[0136] In this embodiment, by selecting one of the uplink signal ports, the memory module can be accessed and used by only one host module at a time, so as to avoid access conflicts and occupation and ensure the stable operation of the application. At the same time, by controlling the selection of the uplink signal ports, the bandwidth of each host module can be adjusted without interrupting the system, thereby effectively ensuring the continuity of services.

[0137] In a specific application example, such as Figure 5 As shown, this embodiment provides a memory expansion system and method based on CXL bus technology. The system includes:

[0138] I. The host unit mainly includes the CPU processor and the CXL port. The CPU processors communicate and expand with each other through a high-speed interconnect bus. The CXL port is where the CXL signal from the CPU processor is connected to the connector.

[0139] II. The CXL interface unit can be connected to the CXL port of the host unit for uplink and to the input of the CXL signal switching unit for downlink.

[0140] III. The CXL signal switching unit contains two CXL signal input terminals, one CXL signal output terminal, and a control terminal, and only performs physical signal switching. The CXL signal input terminals are connected to the CXL signal of the CPU processor on the host computer, and the CXL signal output terminal is connected to the input of the CXL protocol switching unit. The CXL signal switching unit switches the signal control of the two CXL signal input terminals to one output terminal according to the control commands of the interconnection network control unit.

[0141] IV. The Interconnection Network Control Unit is primarily responsible for obtaining the required CXL bus bandwidth from the host unit and converting this bandwidth information into control logic code, including the host ID, port ID, and interface ID. This code then controls the CXL signal switching units, enabling the interconnection of signals between each switching unit. The communication bus between the Interconnection Network Control Unit and the host unit is mainly responsible for the interactive transmission of the entire memory pool's CXL interconnection topology information. The interconnection bus can be selected from various types, such as PCIe, UART, or Ethernet. Considering versatility and transmission distance, Ethernet can be used. The Interconnection Network Control Unit and the host unit each have their own IP address as a unique access identifier. Information such as the host unit's current location and required CXL bus bandwidth is encapsulated in Ethernet packets and sent to the Interconnection Network Control Unit. This packet includes the host ID (to distinguish different hosts within the CXL memory expansion system), the processor ID (to identify a specific processor within a host unit), the port ID (to identify a specific CXL port of the processor), the interface ID of the CXL interface unit (to identify the physical cable interconnection), and bandwidth information (to identify the status of interconnected signal pairs).

[0142] The specific control process of the interconnection network control unit is as follows: First, the interconnection network control unit accesses all host units of the memory expansion system via IP addresses and sends data acquisition information. Each host unit sends the data segment information defined in this invention to the interconnection network control unit via Ethernet packets. The interconnection control unit parses the data packets to obtain the necessary information such as host ID, processor ID, and port ID. Using this information, the CXL network topology information between each host unit and the CXL interface unit within the current memory expansion system can be established. When a host unit requires a change in CXL interconnection bandwidth, the interconnection network control unit controls the CXL signal switching unit according to the new CXL network topology information, realizing the switching control of the CXL network topology.

[0143] V. The CXL protocol switching unit provides high-bandwidth, low-latency data transmission, enabling high-speed data transmission and resource sharing. The uplink connects to the CXL signal switching unit, and the downlink connects to the memory module. The uplink and downlink ports use a 1:1 convergence ratio, primarily enabling the CPU processor on the uplink host unit to access and use the memory on the downlink memory module.

[0144] VI. Memory module unit, including CXL controller and memory medium, can be allocated to the CPU processors of different host units through the CXL protocol exchange unit.

[0145] Example 1

[0146] like Figure 6As shown, the implementation process of this method in a specific embodiment is provided. The details are as follows:

[0147] This embodiment uses four host units as an example. Host unit 1 has four CXL ports connected to four CXL interface units. Each CXL interface unit can have 16 signal pairs, 8 signal pairs, or 4 signal pairs, depending on the actual host bandwidth requirements. In this embodiment, each CXL port has 16 signal pairs. Under the default configuration, the interconnection network control unit controls the CXL signal switching unit to allocate one CXL port to each host unit. Each host unit can access the downlink memory module through the CXL protocol switching unit. If the application running on host unit 1 needs more CXL bandwidth, such as the bandwidth of two CXL ports, the interconnection network control unit can control the CXL signal switching unit 2 to enable the CXL interface unit 3 signal. This allows the host unit to access the downlink memory module through both CXL interface unit 1 and CXL interface unit 3, thus increasing bandwidth. Therefore, in this embodiment, host unit 1 can support a maximum bandwidth of 4 ports × 16 signal pairs, reaching 64 signal pairs.

[0148] Example 2

[0149] like Figure 7 As shown, another specific embodiment of the implementation process of this method is provided. Specifically, it is as follows:

[0150] This embodiment uses four host units as an example. Host unit 1 and host unit 3 are connected to CXL signal switching unit 1 and CXL signal switching unit 2 respectively via one CXL port, and host unit 2 and host unit 4 are connected to CXL signal switching unit 3 and CXL signal switching unit 4 respectively via one CXL port. In the default configuration, the interconnection network control unit controls the CXL signal switching units to assign CXL signal switching units 1 and 2 to host unit 1, and CXL signal switching units 3 and 4 to host unit 2. Host unit 3 acts as a backup host for host unit 1, and host unit 4 acts as a backup host for host unit 2. The interconnection network control unit monitors the status of host units 1 and 2; if any abnormality occurs, it controls the CXL signal switching units to switch the signal links to backup host units 3 and 4, thus achieving high system availability.

[0151] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0152] Based on the same inventive concept, this application also provides a memory expansion device for implementing the memory expansion method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more memory expansion device embodiments provided below can be found in the limitations of the memory expansion method described above, and will not be repeated here.

[0153] In one embodiment, such as Figure 8 As shown, a memory expansion device is provided, including: a data acquisition module 801, an information construction module 802, a monitoring module 803, and a memory expansion module 804, wherein:

[0154] The data acquisition module 801 is used to acquire Ethernet data packets from the host module.

[0155] The information construction module 802 is used to determine the current network topology information between the host module and the signal exchange module based on the Ethernet data packets, and to determine the current signal exchange module that is currently exchanging signals with the host module based on the current network topology information.

[0156] The monitoring module 803 is used to monitor the real-time bandwidth requirements of the host module.

[0157] The memory expansion module 804 is used to select the signal switching module connected to the host module based on the current bandwidth and real-time bandwidth demand, so as to reallocate the memory module accessed by the host module.

[0158] In an optional embodiment, the data acquisition module 801 is further configured to access each host module of the memory expansion system via IP address and send a data acquisition request to the host module; and to receive and parse the Ethernet data packets sent by the host module to obtain the host ID, processor ID, port ID, interface ID, and current bandwidth of the host module.

[0159] In an optional embodiment, the information construction module 802 is further configured to determine the current connection status between the connection port and the signal uplink port and the current bandwidth when the processor of the host module accesses the memory module based on the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module; and to determine the current signal exchange module that is currently exchanging signals with the host module based on the current connection status and the current bandwidth.

[0160] In an optional embodiment, the memory expansion module 804 is further configured to determine the bandwidth difference of the host module's processor based on the real-time required bandwidth and the current bandwidth, add or reduce the allocated memory modules for the host module based on the bandwidth difference, and determine the added or reduced allocated memory modules as mobile memory modules; and select one of the signal uplink ports of the signal exchange module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module.

[0161] Each module in the aforementioned memory expansion device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0162] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data such as the host module's host ID, the host module's processor ID, the host module's port ID, the interface module's interface ID, the host module's current bandwidth, and its IP address. The network interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a memory expansion method.

[0163] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0164] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the memory expansion method of the above embodiment.

[0165] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the memory expansion method of the above embodiment.

[0166] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0167] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0168] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0169] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0170] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A memory expansion system, characterized in that, The system includes: Multiple memory modules; The host module is used to access the memory module according to system operation requirements; A signal exchange module is provided, which is configured in a one-to-one correspondence with the memory module. The signal exchange module is used to establish an access link between the host module and the memory module, enabling the host module to access the memory module. An interconnection control module is connected to both the host module and the signal exchange module. The interconnection control module is used to determine the current interconnection topology network between the host module and the signal exchange module and the current bandwidth of the host module; and to monitor the real-time bandwidth demand of the host module in real time, and select the signal exchange module connected to the host module based on the current bandwidth and the real-time bandwidth demand, so as to reallocate the memory module accessed by the host module. The host module includes: Multiple processors are used to access different memory modules according to system operation requirements during system operation; the multiple processors communicate with each other through a high-speed interconnect bus; Multiple connection ports are provided for connecting the processor and the signal exchange module; the processor is connected to at least one connection port. The first interconnect control terminal is connected to the interconnect control module and is used to realize data transmission between the processor and the interconnect control module.

2. The system according to claim 1, characterized in that, The signal switching module has multiple selectable uplink ports, downlink ports connected to the memory module, and a second interconnection control terminal connected to the interconnection control module. Each uplink port of the signal switching module is connected to any connection port of a different host module through an interface module. When the uplink port of the signal switching module is selected, an access link is established between the host module connected to the uplink port and the corresponding memory module, enabling the host module to access the corresponding memory module.

3. The system according to claim 2, characterized in that, The processor is also used to respond to access requests from the interconnection control module and encapsulate Ethernet data packets based on the current network topology information; the current network topology information includes the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module; The interconnection control module includes: The data parsing unit is used to parse the received Ethernet data packets to obtain the current network topology information, and to determine the current connection status between the connection port and the signal uplink port and the current bandwidth when the host module's processor accesses the memory module based on the host module's host ID, host module's processor ID, host module's port ID, and interface module's interface ID. The data monitoring unit is used to monitor the running status of the processor of the host module in real time and obtain the real-time bandwidth requirements of the host module. A memory allocation unit is used to determine the bandwidth difference of the processor based on the real-time required bandwidth and the current bandwidth, and to add or reduce the allocated memory modules for the host module based on the bandwidth difference, and to determine the added or reduced allocated memory modules as mobile memory modules. The gating control unit is used to select one of the signal uplink ports of the signal exchange module connected to the motor memory module, so as to increase or decrease the number of memory modules accessed by the host module.

4. The system according to any one of claims 2 to 3, characterized in that, Also includes: A protocol exchange module is used to enable the host module to access the memory module; The protocol switching module has an uplink switching port and a downlink switching port. The uplink switching port is connected to the downlink signal port in a one-to-one correspondence, and the downlink switching port is connected to the memory module in a one-to-one correspondence. The convergence ratio of the uplink switching port and the downlink switching port is 1:

1.

5. A memory expansion method, characterized in that, The method is applied to an interconnect control module, which is connected to at least one host module and multiple signal exchange modules, with each of the multiple signal exchange modules corresponding to a multiple memory module; the method includes: The Ethernet data packets of the host module are acquired; the host module has multiple connection ports, each of the signal switching modules has a downlink port and multiple uplink ports, the downlink ports are connected to the memory modules one by one, and the multiple uplink ports are connected to any connection port of different host modules respectively. Based on the Ethernet data packets, obtain the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module; The current connection status between the connection port and the signal uplink port, as well as the current bandwidth when the host module's processor accesses the memory module, are determined based on the host module's host ID, host module's processor ID, host module's port ID, and interface module's interface ID. The current signal exchange module that is currently exchanging signals with the host module is determined based on the current connection status and the current bandwidth. Monitor the real-time bandwidth requirements of the host module. Based on the current bandwidth of the host module and the real-time bandwidth requirement, the signal switching module connected to the host module is selected to reallocate the memory module to be accessed by the host module.

6. The method according to claim 5, characterized in that, The Ethernet data packet is encapsulated based on the current network topology information of the host module, which includes the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module. The step of obtaining the Ethernet data packets of the host module includes: Access each host module of the memory expansion system via IP address and send data acquisition requests to the host module; Receive and parse the Ethernet data packets sent by the host module.

7. The method according to claim 5, characterized in that, The method of selecting a signal switching module connected to the host module based on the host module's current bandwidth and the real-time bandwidth demand, in order to reallocate access to a memory module for the host module, includes: The bandwidth difference of the host module's processor is determined based on the real-time required bandwidth and the current bandwidth. The memory modules allocated to the host module are increased or decreased based on the bandwidth difference, and the increased or decreased memory modules are identified as mobile memory modules. Select one of the signal uplink ports of the signal exchange module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module.

8. A memory expansion device, characterized in that, An interconnect control module is applied to an interconnect control module, which is connected to at least one host module and multiple signal exchange modules, with each of the multiple signal exchange modules corresponding to a multiple memory module; the device includes: A data acquisition module is used to acquire Ethernet data packets of the host module; the host module has multiple connection ports, each of the signal switching modules has a downlink port and multiple uplink ports, the downlink ports are connected to the memory modules one by one, and the multiple uplink ports are connected to any connection port of different host modules respectively. An information construction module is used to: obtain the host ID, processor ID, port ID, interface ID, and current bandwidth of the host module; determine the current connection status between the connection port and the signal uplink port, and the current bandwidth of the host module's processor when accessing the memory module, based on the host ID, processor ID, port ID, and interface ID; and determine the current signal exchange module that is currently exchanging signals with the host module based on the current connection status and the current bandwidth. The monitoring module is used to monitor the real-time bandwidth requirements of the host module. A memory expansion module is used to select a signal switching module connected to the host module based on the host module's current bandwidth and the real-time bandwidth requirement, so as to reallocate access to memory modules for the host module.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 5 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 5 to 7.

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