Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate is provided with a plurality of first signal lines extending in the first direction and a plurality of patch cords extending in the second direction. Each patch cord is connected with one first signal line; the array substrate is further provided with a plurality of shielding structures, and the shielding structures are arranged between the first signal lines and the patch cords which intersect in an insulated mode. The first direction intersects with the second direction. According to the invention, the crosstalk problem between the signal lines of the array substrate can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of display technology, array substrates are used more and more widely, and correspondingly, the requirements for array substrates are also getting higher and higher.

[0003] In the related art, the array substrate has a serious problem of signal crosstalk between signal lines, which deteriorates the display effect and seriously limits the further application of the array substrate. Summary of the invention

[0004] The invention provides an array substrate, a display panel and a display device to improve the problem of crosstalk between signal lines.

[0005] According to one aspect of the present invention, an array substrate is provided, wherein the array substrate is provided with a plurality of first signal lines extending along a first direction and a plurality of adapter lines extending along a second direction; each of the adapter lines is connected to one of the first signal lines;

[0006] The array substrate is further provided with a plurality of shielding structures, and the shielding structures are provided between the first signal lines and the switching lines which are insulated and intersected; the first direction intersects with the second direction.

[0007] Optionally, the shielding structure corresponding to the same adapter wire is electrically connected;

[0008] Preferably, the shielding structure corresponding to the same adapter wire is an integrated structure;

[0009] Preferably, along the second direction, the shielding structures located in the same row are an integrated structure.

[0010] Optionally, the array substrate comprises a plurality of repeating units arranged in an array along the first direction and the second direction; each of the repeating units comprises two pixel driving circuits arranged along the second direction; in the repeating unit, two first signal lines are arranged between two pixel driving circuits;

[0011] Preferably, the first signal line is used to provide a data signal to a pixel driving circuit in the repeating unit;

[0012] Preferably, a second signal line is further arranged between the two first signal lines corresponding to the repeating unit, and the second signal line is used to provide a positive power supply signal for the pixel driving circuit; the second signal line and the first signal line are in the same layer;

[0013] Preferably, in at least some of the repeating units, along the second direction, a third signal line is provided at an edge of the first pixel driving circuit away from the first signal line, and the third signal line is used to provide a negative power supply signal for the pixel driving circuit; the third signal line is in the same layer as the first signal line;

[0014] Preferably, in the repeating unit, along the second direction, a fourth signal line is provided at an edge of the second pixel driving circuit away from the first signal line, and the fourth signal line is used to provide an initialization signal for the pixel driving circuit; the fourth signal line is in the same layer as the first signal line.

[0015] Optionally, a constant voltage signal is connected to the shielding structure;

[0016] Preferably, the array substrate is provided with a plurality of fifth signal lines extending along the second direction, and partial structures of some of the fifth signal lines are reused as the shielding structure;

[0017] Preferably, the array substrate comprises a plurality of repeating units arranged in an array along the first direction and the second direction; each of the repeating units comprises two pixel driving circuits arranged along the second direction; along the first direction, the fifth signal line is located at an edge of the repeating unit; the fifth signal line is used to provide an initialization signal for the pixel driving circuit;

[0018] Preferably, in the fifth signal line whose partial structure is multiplexed as the shielding structure, the fifth signal line is electrically connected to the pixel driving circuit through a switching via; along the first direction, the shielding structure corresponding to the fifth signal line is located on the side of the corresponding switching via away from the pixel driving circuit.

[0019] Optionally, the portion of the fifth signal line corresponding to the pixel driving circuit includes a first portion, a second portion and a third portion, the first portion and the third portion extend along the second direction, the second portion extends along the first direction, the first portion and the third portion are not colinear and are connected through the second portion; the third portion is multiplexed as the shielding structure;

[0020] Preferably, along the first direction, the width of the third portion is greater than the width of the first portion.

[0021] Optionally, the array substrate comprises a substrate and a driving circuit layer arranged on the substrate;

[0022] The driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; the adapter line is arranged on the second conductive layer, the shielding structure is arranged on the third conductive layer, and the first signal line is arranged on the fourth conductive layer;

[0023] Preferably, a plurality of pixel driving circuits are arranged in the driving circuit layer; the active layer is used to set the active structure of the transistor in the pixel driving circuit, the first conductive layer is used to set the gate of the transistor, and the third conductive layer is used to set the source and drain of the transistor.

[0024] Optionally, the array substrate is further provided with a plurality of first auxiliary signal lines extending along the first direction; each of the first auxiliary signal lines is connected to one of the first signal lines;

[0025] Preferably, the first auxiliary signal line is in the same layer as the first signal line;

[0026] Preferably, the first auxiliary signal line is used to connect a driving chip;

[0027] Preferably, the array substrate includes a plurality of repeating units arranged in an array along the first direction and the second direction; each of the repeating units includes two pixel driving circuits arranged along the second direction; in the repeating units, two first signal lines are arranged between the two pixel driving circuits; in at least some of the repeating units, along the second direction, a third signal line is provided at an edge of the first pixel driving circuit away from the first signal line, and the third signal line is used to provide a negative power supply signal to the pixel driving circuit; the third signal line is in the same layer as the first signal line; and the first auxiliary signal line is colinear with one of the third signal lines.

[0028] Optionally, the array substrate is further provided with a plurality of second auxiliary signal lines extending along the second direction; the second auxiliary signal lines are in the same layer as the adapter lines;

[0029] Preferably, the second auxiliary signal line is connected with the third signal line to form a mesh structure.

[0030] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate as described above.

[0031] According to another aspect of the present invention, a display device is provided, comprising the display panel as described above.

[0032] The technical solution of the embodiment of the present invention adopts an array substrate provided with a plurality of first signal lines extending along a first direction and a plurality of adapter lines extending along a second direction; each adapter line is connected to a first signal line; the array substrate is also provided with a plurality of shielding structures, the shielding structures are provided between the insulated and intersecting first signal lines and adapter lines; the first direction intersects with the second direction. By providing the shielding structure, the degree of signal coupling between the first signal line and the adapter line is reduced, and the mutual influence between the two signals is small, that is, the shielding structure can shield the signal crosstalk between the first signal line and the adapter line.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of an array substrate provided by an embodiment of the present invention;

[0036] Figure 2 for Figure 1 A cross-section along the A1A2 direction;

[0037] Figure 3 for Figure 1 Schematic diagram of the membrane structure in the first region;

[0038] Figure 4 A cross-sectional view of an array substrate provided by an embodiment of the present invention;

[0039] Figure 5 for Figure 3 A magnified schematic diagram of the repeating unit in FIG.

[0040] Figure 6 A schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present invention;

[0041] Figure 7 for Figure 6 A corresponding timing diagram;

[0042] Figure 8 for Figure 5 Schematic diagram of the structure of the active layer;

[0043] Fig. 9for Figure 5 A schematic structural diagram of the first conductive layer;

[0044] Fig.10 for Figure 5 A schematic structural diagram of the second conductive layer;

[0045] Fig.11 for Figure 5 A schematic diagram of the structure of the third conductive layer;

[0046] Fig.12 for Figure 5 A schematic structural diagram of the fourth conductive layer;

[0047] Fig.13 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] As the array substrate in the related art has the problem of serious crosstalk between signal lines, the inventors have found through careful research that the reason for this technical problem is that in the related art, in order to reduce the frame of the array substrate, the FIAA (fanout in AA, display area fan-out) technology can be used so that the fan-out line corresponding to the first signal line is set in the display area. However, after adopting the FIAA technology, there will inevitably be a certain overlap between the vertical first signal line and the horizontal fan-out line. Since the first signal line and the horizontal fan-out line both transmit the same type of signal (such as both transmit data signals), the signal crosstalk between the two has a greater impact on the display effect. When the distance between two adjacent first signal lines is small, the signal crosstalk problem between the horizontal fan-out line and the first signal line is more serious.

[0051] In view of the above technical problems, the present invention proposes the following solutions:

[0052] Figure 1 A schematic diagram of an array substrate provided by an embodiment of the present invention, Figure 2 for Figure 1 A cross-section along the A1A2 direction, see Figure 1 and Figure 2 The array substrate is provided with a plurality of first signal lines Data extending along a first direction Y and a plurality of adapter lines R11 extending along a second direction X; each adapter line R11 is connected to a first signal line Data; the array substrate is also provided with a plurality of shielding structures 30, and the shielding structures 30 are provided between the insulated and intersecting first signal lines Data and adapter lines R11; the first direction Y intersects with the second direction X.

[0053] Specifically, the array substrate can be used to prepare a display panel, such as forming a display panel after evaporating light-emitting elements on the array substrate and packaging. The first direction Y can be a column direction, and the second direction X can be a row direction. A plurality of pixel driving circuits are provided on the array substrate, and each pixel driving circuit is used to drive at least one light-emitting element. The first signal line Data is used to provide a corresponding driving signal to the pixel driving circuit, for example, the first signal line Data is a data line that provides a data signal to the pixel driving circuit. Of course, in some other embodiments, the first signal line Data can also be other signal lines.

[0054] The array substrate may have a first display area AA1 and a second display area AA2 distributed along the second direction X, and the first display area AA1 corresponds to the arc-shaped frame area. Each first signal line Data located in the first display area AA1 is correspondingly provided with a transfer line R11, so that the first signal line Data in the first display area AA1 implements the FIAA scheme. However, in the related art, the transfer line R11 and the corresponding first signal line Data are located in adjacent conductive layers, and the signal crosstalk between the two is relatively serious. In addition, when the distance between the two first signal lines Data is relatively close, such as when the pixel density is relatively large, or when a Ramless scheme is adopted, or when the adjacent two columns of pixel driving circuits are symmetrically arranged so that the distance between the two first signal lines is relatively close, the crosstalk between the transfer line R11 and the first signal line Data is more serious. In this embodiment, a shielding structure 30 is provided between the insulated and intersecting first signal lines Data and the transfer line R11. In other words, along the thickness direction of the array substrate, the orthographic projection of the insulated intersection of the first signal line Data and the adapter line R11 is located within the orthographic projection of the corresponding shielding structure 30, and the conductive layer where the shielding structure 30 is located is located between the conductive layer where the first signal line Data is located and the conductive layer where the adapter line R11 is located. By setting the shielding structure 30, the signals on the first signal line Data and the adapter line R11 will be coupled to the shielding structure 30, and the crosstalk problem between the first signal line Data and the adapter line R11 will be greatly improved. Based on this, the array substrate can be an array substrate with a high pixel density, an array substrate with a Ramless solution, or an array substrate with a symmetrical pixel driving circuit, etc.

[0055] The technical solution of this embodiment adopts an array substrate provided with a plurality of first signal lines extending in a first direction and a plurality of adapter lines extending in a second direction; each adapter line is connected to a first signal line; the array substrate is also provided with a plurality of shielding structures, the shielding structures are provided between the insulated and intersecting first signal lines and adapter lines; the first direction intersects with the second direction. By providing the shielding structure, the degree of signal coupling between the first signal line and the adapter line is reduced, and the mutual influence between the two signals is small, that is, the shielding structure can shield the signal crosstalk between the first signal line and the adapter line.

[0056] It is understandable that in the above embodiment, the shielding structure 30 can be made of conductive material. The first signal line Data and the adapter line R11 are both made of conductive material, and the shielding structure 30 made of conductive material disposed between the two can provide a better shielding effect.

[0057] For ease of understanding, the overall structure of the array substrate is briefly described below. Of course, the structure of the array substrate is diverse, and this embodiment only introduces one of them. As long as a shielding structure is provided between the first signal line and the adapter line, it is within the protection scope of the present invention. In the present invention, the specific film layer where the first signal line, the adapter line and the shielding structure are located is not limited.

[0058] Figure 3 for Figure 1 Schematic diagram of the membrane structure in the first area, Figure 4 A cross-sectional view of an array substrate provided by an embodiment of the present invention, Figure 5 for Figure 3 A magnified schematic diagram of the repeating unit in Figure 6 A schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present invention, Figure 7 for Figure 6 A corresponding timing diagram, see Figures 3 to 7 . The array substrate includes a substrate Sub and a driving circuit layer disposed on the substrate Sub. The substrate Sub can be a flexible substrate, such as polyimide, etc.; the substrate Sub can also be a rigid substrate, such as glass, etc. A buffer layer can also be disposed between the driving circuit layer and the substrate Sub. A plurality of pixel driving circuits PX are formed in the driving circuit layer. The driving circuit layer can specifically include an active layer Act, a first conductive layer M1, a second conductive layer M2, a third conductive layer SD1, and a fourth conductive layer SD2 stacked in sequence.

[0059] The pixel driving circuit includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first initialization transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second initialization transistor T7 and a capacitor C. The first end of the driving transistor T1 is electrically connected to the first end of the first light emission control transistor T5, the second end of the driving transistor T1 is electrically connected to the first end of the second light emission control transistor T6, and the control end of the driving transistor T1 is electrically connected to the first end of the capacitor C. The first end of the data writing transistor T2 is connected to the data line Data, the second end of the data writing transistor T2 is electrically connected to the first end of the driving transistor T1, and the control end of the data writing transistor T2 is connected to the second scanning signal line S2. The first end of the threshold compensation transistor T3 is electrically connected to the second end of the driving transistor T1, the second end of the threshold compensation transistor T3 is electrically connected to the control end of the driving transistor T1, and the control end of the threshold compensation transistor T3 is connected to the second scanning signal line S2. The first end of the first initialization transistor T4 is connected to the initialization signal line Vref, the second end of the first initialization transistor T4 is electrically connected to the control end of the driving transistor T1, and the control end of the first initialization transistor T4 is connected to the first scanning signal line S1. The second end of the first light-emitting control transistor T5 is connected to the positive power signal line Vdd, and the control end of the first light-emitting control transistor T5 is connected to the enable signal line EM. The second end of the second light-emitting control transistor T5 is connected to the anode of the light-emitting element, and the control end of the second light-emitting control transistor T5 is connected to the enable signal line EM. The first end of the second initialization transistor T7 is connected to the initialization signal line Vref, and the second end is connected to the anode of the light-emitting element, and the control end of the second initialization transistor T7 is connected to the third scanning signal line S3. The second end of the capacitor C is connected to the positive power signal line Vdd. The cathode of the light-emitting element is connected to the negative power signal line Vss.

[0060] The working process of the pixel driving circuit includes an initialization phase t1, a data writing phase t2 and a light emitting phase t3.

[0061] In the initialization stage t1 , the first scanning signal line S1 controls the first initialization transistor T4 , and the initialization signal on the initialization signal line Vref initializes the control terminal voltage of the driving transistor T1 .

[0062] In the data writing stage t2, the second scanning signal line S2 controls the threshold compensation transistor T3 to be turned on, and the third scanning signal line S3 controls the data writing transistor T2 and the second initialization transistor T7 to be turned on. The data signal on the data line Data is written to the control end of the driving transistor T1 after passing through the driving transistor T1 and the threshold compensation transistor T3. When the voltage difference between the control end and one end of the driving transistor T1 is the threshold voltage of the driving transistor T1, the driving transistor T1 is turned off, thereby completing the threshold compensation of the driving transistor T1. At the same time, in this stage, the initialization signal on the initialization signal line Vref initializes the anode voltage of the light-emitting element.

[0063] In the light emitting stage t3, the enable signal line EM controls the first light emitting control transistor T5 and the second light emitting control transistor T6 to be turned on, the driving transistor T1 generates a driving current according to the voltage at its control terminal, and the light emitting element emits light in response to the driving current.

[0064] It should be noted that although the present embodiment is described with the pixel driving circuit as a "7T1C" structure, the specific structure of the pixel driving circuit is not limited thereto, for example, it may also be a "2T1C" pixel driving circuit including two transistors and one capacitor.

[0065] In the above embodiment, optionally, the active structure of each transistor is arranged in the active layer Act, the gate of each transistor is arranged in the first conductive layer M1, the first plate of capacitor C (corresponding to the first end of capacitor C) is arranged in the first conductive layer, the second plate of capacitor C (corresponding to the second end of capacitor C) is arranged in the second conductive layer, and the source and drain of each transistor are arranged in the third conductive layer SD1.

[0066] Optionally, refer to Figure 1 , which is electrically connected to the shielding structure 30 corresponding to the same adapter wire R11.

[0067] Specifically, in the array substrate, the adapter line R11 extends along the second direction X. Since the adapter line R11 is a continuous wire, and the distance between the first signal line Data that is insulated and intersected with it is also close, it means that the distance between the multiple shielding structures corresponding to the same adapter line R11 is close. If the shielding structures 30 with similar distances are independent of each other, parasitic capacitance may be formed between each other, so that there are more parasitic capacitances in the array substrate, and then serious signal interference problems occur. The arrangement of this embodiment enables the shielding structures 30 corresponding to the same adapter line R11 to be electrically connected as a whole, thereby avoiding the formation of parasitic capacitances between the shielding structures 30, that is, the stability of the operation of the array substrate can be improved. More preferably, the shielding structure 30 corresponding to the same adapter line R11 is an integrated structure. During production, the shielding structure 30 and the portion for electrical connection between the shielding structures 30 can be produced by the same process, thereby reducing the production cost. Further preferably, along the second direction X, the shielding structures 30 located in the same row are an integrated structure. During manufacturing, the shielding structures 30 located in the same row along the second direction X and the parts used for electrical connection between the shielding structures 30 can be manufactured through the same process, thereby reducing the manufacturing cost; and the potentials on the shielding structures 30 located in the same row along the second direction X are close, so that the shielding effects can be close.

[0068] Optionally, refer to Figure 3 The array substrate includes a plurality of repeating units 1 arranged in an array along a first direction Y and a second direction X; each repeating unit 1 includes two pixel driving circuits arranged along the second direction X, which are respectively recorded as a first pixel driving circuit PX1 and a second pixel driving circuit PX2 for ease of understanding; the repeating unit 1 is symmetrical about the center line of the repeating unit 1, wherein the center line of the repeating unit extends along the first direction Y; in the repeating unit 1, two first signal lines Data are arranged between the two pixel driving circuits.

[0069] Specifically, this embodiment takes the symmetry of two adjacent columns of pixel driving circuits on the array substrate as an example. In this structure, no first signal line Data is set between two repeating units 1, and two first signal lines Data are set in the middle of the repeating unit 1. Among them, the first signal line Data located on the first side of the center line of the repeating unit 1 is used to drive the pixel driving circuit located on the first side of the center line of the repeating unit 1 ( Figure 3 For example, the first pixel driving circuit PX1) provides a data signal; the first signal line Data located on the second side of the center line of the repeating unit 1 is used to provide a data signal to the pixel driving circuit ( Figure 3For example, the second pixel driving circuit PX2 provides a data signal. It can be seen that in this structure, there are first signal lines Data with a close distance. When the first signal line Data and the adapter line R11 are insulated and intersected, the signal crosstalk will be more serious. By setting a shielding structure 30 between the adapter line R11 and the first signal line Data, the signal crosstalk problem can be greatly improved.

[0070] Optionally, Figure 8 for Figure 5 The schematic diagram of the active layer structure is shown in Figure 2. Fig. 9 for Figure 5 Schematic diagram of the structure of the first conductive layer, Fig.10 for Figure 5 Schematic diagram of the structure of the second conductive layer, Fig.11 for Figure 5 Schematic diagram of the structure of the third conductive layer, Fig.12 for Figure 5 Schematic diagram of the structure of the fourth conductive layer, refer to Figure 3 as well as Figures 5 to 12 A second signal line Vdd1 is further arranged between the two first signal lines Data corresponding to the repeating unit 1, and the second signal line Vdd1 is used to provide a positive power supply signal for the pixel driving circuit; the second signal line Vdd1 is in the same layer as the first signal line Data.

[0071] Specifically, since the distance between the two first signal lines Data corresponding to the same repeating unit 1 is relatively close, the crosstalk between the two first signal lines Data can be improved by setting a second signal line Vdd1 having a constant voltage signal between the two. In this embodiment, the positive power supply signal is a signal input to the second end of the fifth transistor T5, which can be a high level signal. Figure 5 and Fig.10 , the array substrate may also include a plurality of sixth signal lines Vdd2 extending along the second direction X and arranged along the first direction Y, and the sixth signal line Vdd2 is used to provide a positive power signal for the pixel driving circuit. The second signal line Vdd1 and the sixth signal line Vdd2 are connected to form a positive power signal line Vdd with a mesh structure, so that the overall impedance of the positive power signal line Vdd is small, and the signal difference at each position of the positive power signal line Vdd is small, so that the difference in positive power signals received by different pixel driving circuits is small, and thus the brightness difference of each light-emitting element is small. In other words, by setting a positive power signal line Vdd with a mesh structure, the problem of uneven display can be improved. Optionally, the sixth signal line Vdd2 is arranged in the second conductive layer, and can be an integrated structure with the second electrode plate of the capacitor, thereby reducing the manufacturing cost of the array substrate.

[0072] Optionally, refer to Figure 5, in at least part of the repeating unit 1, along the second direction X, a third signal line Vss1 is provided at an edge of the first pixel driving circuit (i.e., the first pixel driving circuit PX1) away from the first signal line Data, and the third signal line Vss1 is used to provide a negative power supply signal for the pixel driving circuit; the third signal line Vss1 is on the same layer as the first signal line Data.

[0073] Specifically, in the area between two adjacent repeating units 1, since the first signal line Data does not need to be set, the interval between two adjacent repeating units 1 can be set smaller. However, for the conductive layer where the first signal line Data is located, there is a serious problem of space waste in the area corresponding to the edge of the repeating unit 1 along the second direction X. In this embodiment, a third signal line Vss1 is set in this area, and the third signal line Vss1 is used to form a negative power signal line Vss to provide a negative power signal, wherein the negative power signal is a signal received by the cathode of the light-emitting element, which can be a low-level signal. It can be understood that the third signal line Vss1 can overlap the cathode layer of the light-emitting element in the non-display area of ​​the array substrate. By setting the third signal line Vss1, the space utilization rate of the array substrate can be improved, and the impedance of the negative power signal line Vss can be reduced, thereby reducing the overall power consumption of the array substrate.

[0074] Optionally, refer to Figure 1 and Figure 3 The array substrate is further provided with a plurality of first auxiliary signal lines R12 extending along the first direction Y; each first auxiliary signal line R12 is connected to a first signal line R11.

[0075] Specifically, the first auxiliary signal line R12 is disposed in the second area A12, and the first auxiliary signal line R12 is used to connect the driving chip to provide a data signal for the corresponding first signal line Data.

[0076] Optionally, the first auxiliary signal line R12 is in the same layer as the first signal line Data.

[0077] Specifically, the arrangement of this embodiment can fully utilize the space of the conductive layer where the first signal line Data is located, thereby improving space utilization.

[0078] Furthermore, in order to make the distribution of signal lines in various parts of the array substrate more uniform and improve the off-screen mura phenomenon, the first auxiliary signal line R11 of the array substrate can be set to correspond to at least part of the third signal line Vss1 in a one-to-one manner; it can be understood that the first auxiliary signal line R11 is insulated from the corresponding third signal line Vss1. In this way, the repeating units in the same column as the first auxiliary signal line R12 are all correspondingly provided with signal lines (the third signal line Vss1 in this embodiment), which can greatly improve the off-screen mura problem. In addition, in order to further improve the off-screen mura, the space of the array substrate is fully utilized, and the FIAA scheme is implemented. In all repeating units 1 of the present application, signal lines are set at the edge of the first pixel driving circuit away from the first signal line, wherein part of the signal lines are the first auxiliary signal lines R12, and the rest of the signal lines are the third signal lines Vss1. It is understandable that in the entire display area of ​​the array substrate, the area where the first auxiliary signal line R12 needs to be set is relatively small, that is, the proportion of the repeating unit 1 corresponding to the third signal line Vss1 is larger than the proportion of the repeating unit 1 corresponding to the first auxiliary signal line R12. It should be noted that the same layer mentioned herein means that the two are simultaneously manufactured and formed in the same process.

[0079] Optionally, refer to Figure 5 In the repeating unit 1, along the second direction X, a fourth signal line Vref1 is provided at an edge of the second pixel driving circuit away from the first signal line Data, and the fourth signal line Vref1 is in the same layer as the first signal line Data.

[0080] Specifically, in this embodiment, by setting the fourth signal line Vref1, the space utilization rate of the conductive layer where the first signal line Data is located can be further improved. And the distribution of the signal lines in the conductive layer is made more uniform, thereby further improving the off-screen mura phenomenon. The fourth signal line Vref1 is used to constitute the initialization signal line Vref corresponding to the pixel driving circuit.

[0081] Optionally, in the above embodiment, the first signal line Data, the second signal line Vdd1, the third signal line Vss1, the first auxiliary signal line R12 and the fourth signal line Vref1 are all disposed in the fourth conductive layer, and a stacked metal structure of TiAlTi may be adopted.

[0082] Optionally, a constant voltage signal is connected to the shielding structure 30. Specifically, if the shielding structure 30 is not connected to a constant potential, it may have the function of radiating signals as an independent conductive block inside the array substrate, that is, it may form an antenna structure, thereby affecting the stability of the signal in the array substrate. By introducing a constant voltage signal to the shielding structure 30, the shielding structure 30 can be prevented from radiating signals outward. It is understandable that the constant voltage signal can be a positive power supply signal, a negative power supply signal, or an initialization signal, etc.

[0083] Optionally, refer to Figure 5 The array substrate is provided with a plurality of fifth signal lines Vref3 extending along the second direction X, and a portion of the structure of some fifth signal lines Vref3 is reused as a shielding structure 30 .

[0084] Specifically, the fifth signal line Vref3 is arranged at an edge of the repeating unit 1 along the first direction Y. For example, it can be an edge close to the border (usually the lower border) used to bind the driver chip. The fifth signal line Vref3 is used to constitute an initialization signal line Vref to provide an initialization signal. Among them, the fifth signal line Vref3 and the fourth signal line Vref1 are connected to form a mesh structure, and the mesh structure constitutes a partial structure of the initialization signal line Vref, so that the overall impedance of the initialization signal line Vref is small and the power consumption is also low. In this embodiment, the position of part of the fifth signal line Vref3 is at a position corresponding to the overlap of the adapter line R11 and the first signal line Data, and the partial structure of the part of the fifth signal line Vref3 can be set between the adapter line R11 and the first signal line Data, and can be reused as a shielding structure 30, so that there is no need to set up an additional shielding structure 30.

[0085] Optionally, refer to Figure 5 The array substrate is further provided with a plurality of seventh signal lines Vref2 extending along the second direction X, and the seventh signal lines Vref2 are in the same layer as the shielding structure 30 .

[0086] Specifically, the seventh signal line Vref2 is disposed at another edge of the repeating unit 1 along the first direction Y, for example, an edge away from the frame for binding the driver chip. The seventh signal line Vref2, the fifth signal line Vref3 and the fourth signal line Vref1 are connected to form a mesh structure of initialization signal lines Vref.

[0087] Optionally, the seventh signal line Vref2 and the fifth signal line Vref3 are arranged in the third conductive layer, and the material thereof may be a TiAlTi laminated structure.

[0088] Optionally, refer to Figure 5, the fifth signal line Vref3 is electrically connected to the pixel driving circuit through the transfer via HO; along the first direction Y, the shielding structure 30 corresponding to the fifth signal line Vref2 is located on a side of the corresponding transfer via HO ​​away from the pixel driving circuit.

[0089] Specifically, in this embodiment, the portion of the fifth signal line Vref2 corresponding to the shielding structure 30 needs to overlap with the adapter line R11, and the fifth signal line Vref2 needs to be connected to the active structure in the active layer through the adapter via HO. If the fifth signal line Vref2 is set as a straight line extending along the first direction, then in order to realize the shielding function of the fifth signal line Vref2, it is necessary to set the adapter line R11 to be consistent with the fifth signal line Vref2. Such a setting will cause the adapter line R11 to overlap with the active structure, and may form a parasitic transistor, affecting the structure of the pixel driving circuit. In the setting of this embodiment, the adapter via HO ​​and the shielding structure 30 are not colinear, so the active structure and the adapter line R11 may not overlap, thereby avoiding the situation where the adapter line R11 intersects with the active structure to form a parasitic transistor.

[0090] Optionally, refer to Fig.11 In the fifth signal line Vref3 whose partial structure is multiplexed as the shielding structure 30, the portion of the fifth signal line Vref3 corresponding to the pixel driving circuit includes a first portion 41, a second portion 42 and a third portion 43, the first portion 41 and the third portion 43 extend along the second direction X, the second portion 42 extends along the first direction Y, the first portion 41 and the third portion 43 are not colinear and are connected through the second portion 42; the third portion is multiplexed as a shielding structure.

[0091] Specifically, the fifth signal line Vref3 corresponds to the portion of the pixel driving circuit, that is, the portion overlapping with the area where the pixel driving circuit is located. The first portion 41, the second portion 42 and the third portion 43 constitute a "Z"-shaped wiring structure. The portion of the fifth signal line Vref3 corresponding to the repeating unit is also symmetrical about the center line axis of the repeating unit, that is, it constitutes a "J"-shaped wiring structure. This arrangement can not only ensure that the shielding structure 30 can partially shield the crosstalk between the adapter line R11 and the first signal line Data, but also enable the fifth signal line Vref3 to be electrically connected to the pixel driving circuit. At the same time, it can also make the arrangement of the pixel driving circuit more compact, so as to improve the pixel density.

[0092] Optionally, along the first direction Y, the width of the third portion 43 is greater than the width of the first portion 41. Specifically, since the third portion 43 needs to be used as the shielding structure 30, a larger width is beneficial to improving the shielding effect. The first portion 41 has a smaller width, which can reduce the area occupied by the entire pixel driving circuit, thereby further improving the pixel density.

[0093] Optionally, the shapes of the fifth signal lines Vref3 in the array substrate are the same. Specifically, the adapter line R11 accounts for a small proportion of the overall array substrate. That is to say, part of the fifth signal line Vref3 corresponds to the adapter line R11, while the remaining fifth signal line Vref3 is not provided with a corresponding adapter line. In this embodiment, all the fifth signal lines Vref3 are arranged in the same shape, that is, each adapter line is composed of a plurality of "J"-shaped structures as a whole, which ensures the consistency of the shape of the signal lines in the array substrate and can further improve the off-screen mura phenomenon.

[0094] refer to Figures 8 to 12 , the first scan signal line S1, the second scan signal line S2, the third scan signal S3 and the enable signal line EM are arranged in the first conductive layer; the adapter line R11 and the sixth signal line Vdd2 are arranged in the second conductive layer; the seventh signal line Vref2 and the fifth signal line Vref3 are arranged in the third conductive layer; the first signal line Data, the second signal line Vdd1, the third signal line Vss1, the first auxiliary signal line R12 and the fourth signal line Vref1 are all arranged in the fourth conductive layer. That is to say, in this embodiment, the number of conductive layers of the array substrate is not increased, but the adapter line R11 is arranged in the second conductive layer, and the shielding structure 30 is arranged in the third conductive layer, so that a shielding structure is added between the adapter line and the first signal line without increasing the conductive layer. Since no conductive layer is added, the mask will not be increased in this embodiment, and the layout space of the array substrate will not be increased, that is, the cost of the array substrate will not be increased.

[0095] Optionally, refer to Figure 1 and Figure 5 The array substrate is further provided with a plurality of second auxiliary signal lines Vss2 extending along the second direction X; the second auxiliary signal lines Vss2 are on the same layer as the adapter lines R11.

[0096] Specifically, the second auxiliary signal line Vss2 and the third signal line Vss1 are connected to form a mesh structure of a negative power signal line Vss, thereby reducing the impedance of the negative power signal line Vss and further reducing power consumption. Optionally, each adapter line R11 is colinear with at least one second auxiliary signal line Vss2.

[0097] An embodiment of the present invention further provides a display panel, which includes the array substrate provided by any embodiment of the present invention. The display panel also includes a light-emitting element disposed on the array substrate. The light-emitting element may be an OLED (Organic Light Emitting Diode), a Micro-LED, a μLED, or a QLED. Since the display panel provided by an embodiment of the present invention includes the array substrate provided by any embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail herein.

[0098] The embodiment of the present invention further provides a display device, such as Fig.13 As shown, Fig.13 A schematic diagram of the structure of a display device provided in an embodiment of the present invention. The display device includes a display panel provided in an embodiment of the present invention. The display device may be a mobile phone, a tablet computer, an MP3, an MP4, a videophone, a personal digital assistant, a smart watch, a smart helmet or other wearable device. Since it includes the display panel provided in an embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0099] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0100] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate is provided with a plurality of first signal lines extending along a first direction and a plurality of adapter lines extending along a second direction; each of the adapter lines is connected to one of the first signal lines; The array substrate is further provided with a plurality of shielding structures, and the shielding structures are provided between the first signal lines and the switching lines which are insulated and intersected; the first direction intersects with the second direction.

2. The array substrate according to claim 1, characterized in that: being electrically connected to the shielding structure corresponding to the same adapter wire; Preferably, the shielding structure corresponding to the same adapter wire is an integrated structure; Preferably, along the second direction, the shielding structures located in the same row are an integrated structure.

3. The array substrate according to claim 1, characterized in that: The array substrate comprises a plurality of repeating units arranged in an array along the first direction and the second direction; each of the repeating units comprises two pixel driving circuits arranged along the second direction; in the repeating unit, two first signal lines are arranged between two pixel driving circuits; Preferably, the first signal line is used to provide a data signal to a pixel driving circuit in the repeating unit; Preferably, a second signal line is further arranged between the two first signal lines corresponding to the repeating unit, and the second signal line is used to provide a positive power supply signal for the pixel driving circuit; the second signal line and the first signal line are in the same layer; Preferably, in at least some of the repeating units, along the second direction, a third signal line is provided at an edge of the first pixel driving circuit away from the first signal line, and the third signal line is used to provide a negative power supply signal for the pixel driving circuit; the third signal line is in the same layer as the first signal line; Preferably, in the repeating unit, along the second direction, a fourth signal line is provided at an edge of the second pixel driving circuit away from the first signal line, and the fourth signal line is used to provide an initialization signal for the pixel driving circuit; the fourth signal line is in the same layer as the first signal line.

4. The array substrate according to claim 1, characterized in that: A constant voltage signal is connected to the shielding structure; Preferably, the array substrate is provided with a plurality of fifth signal lines extending along the second direction, and partial structures of some of the fifth signal lines are reused as the shielding structure; Preferably, the array substrate comprises a plurality of repeating units arranged in an array along the first direction and the second direction; each of the repeating units comprises two pixel driving circuits arranged along the second direction; along the first direction, the fifth signal line is located at an edge of the repeating unit; the fifth signal line is used to provide an initialization signal for the pixel driving circuit; Preferably, the fifth signal line is electrically connected to the pixel driving circuit through a transfer via; Along the first direction, the shielding structure corresponding to the fifth signal line is located on a side of the corresponding transfer via hole away from the pixel driving circuit.

5. The array substrate according to claim 4, characterized in that: In the fifth signal line whose partial structure is multiplexed into the shielding structure, the portion of the fifth signal line corresponding to the pixel driving circuit includes a first portion, a second portion and a third portion, the first portion and the third portion extend along the second direction, the second portion extends along the first direction, the first portion and the third portion are not colinear and are connected through the second portion; the third portion is multiplexed into the shielding structure; Preferably, along the first direction, the width of the third portion is greater than the width of the first portion.

6. The array substrate according to claim 1, characterized in that: The array substrate comprises a substrate and a driving circuit layer arranged on the substrate; The driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; the adapter line is arranged on the second conductive layer, the shielding structure is arranged on the third conductive layer, and the first signal line is arranged on the fourth conductive layer; Preferably, a plurality of pixel driving circuits are arranged in the driving circuit layer; the active layer is used to set the active structure of the transistor in the pixel driving circuit, the first conductive layer is used to set the gate of the transistor, and the third conductive layer is used to set the source and drain of the transistor.

7. The array substrate according to claim 1, characterized in that: The array substrate is further provided with a plurality of first auxiliary signal lines extending along the first direction; each of the first auxiliary signal lines is connected to one of the first signal lines; Preferably, the first auxiliary signal line is in the same layer as the first signal line; Preferably, the first auxiliary signal line is used to connect a driving chip; Preferably, the array substrate includes a plurality of repeating units arranged in an array along the first direction and the second direction; each of the repeating units includes two pixel driving circuits arranged along the second direction; in the repeating units, two first signal lines are arranged between the two pixel driving circuits; in at least some of the repeating units, along the second direction, a third signal line is provided at an edge of the first pixel driving circuit away from the first signal line, and the third signal line is used to provide a negative power supply signal to the pixel driving circuit; the third signal line is in the same layer as the first signal line; and the first auxiliary signal line is colinear with one of the third signal lines.

8. The array substrate according to claim 3, characterized in that: The array substrate is further provided with a plurality of second auxiliary signal lines extending along the second direction; the second auxiliary signal lines are in the same layer as the adapter lines; Preferably, the second auxiliary signal line is connected with the third signal line to form a mesh structure.

9. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9.

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