Binary significant bit reflection calculation method and device

Abstract

The invention discloses a binary significant bit reflection calculation method and device, and the method is used for calculating an input value A and (A-1) XOR, and comprises the steps: sequentially carrying out the calculation from the lowest bit to the highest bit of an output value X; the second lowest bit to the highest bit of the output value X are sequentially calculated according to the following formula: Xi = (A1 +... + Ai-1) ', i is greater than or equal to 2, Xi represents the i bit of the output value X from the second lowest bit to the highest bit, and Ai-1 represents the i-1 bit of the input value A from the lowest bit to the second highest bit; and arranging the numerical values of all bits of the obtained output value X according to a sequence, and calculating to obtain a calculation result X of XOR of the input value A and (A-1). By adopting the technical scheme, a special calculation method is provided for effective bit reflection calculation, and the calculation is simpler, more convenient and more efficient.

Description

Technical Field

[0001] The present invention relates to the field of computer logic calculation technology, and in particular to a binary effective bit reflection calculation method and device. Background Art

[0002] Mathematical logic calculation plays an important role in many fields, such as computer science and engineering, artificial intelligence and machine learning, electronic engineering, and communication systems. Therefore, providing simple and convenient mathematical logic calculation methods and devices can provide support for research and development in the above fields.

[0003] In the prior art, some simple mathematical logic operations have special calculation methods, dedicated accelerators and corresponding circuit structures, but some more complex mathematical logic operations do not. For these mathematical logic operations without special calculation methods, the ALU (Arithmetic Logic Unit) in the computer central processing unit (CPU) is usually used. No matter how complex the operation is, it can be implemented using the ALU. For example, effective bit reflection calculation, that is, A⊕(A-1).

[0004] But the problem is that the more complex the mathematical logic operation, the higher the cost of the ALU, the larger the space it takes up in the processor, and the more power it consumes. Although the simplest computer can calculate the most complex formulas, it usually takes a lot of time and takes several steps to complete; a powerful processor will be designed with an extremely complex ALU that can complete the calculation in one step, but this is based on the premise of constructing a very complex ALU in the processor. Summary of the invention

[0005] Purpose of the invention: The present invention provides a binary effective bit reflection calculation method and device, aiming to provide a special calculation method and a special accelerator for the effective bit reflection calculation.

[0006] Technical solution: The present invention provides a binary effective bit reflection calculation method for calculating the exclusive OR of an input value A and (A-1), comprising: receiving an input value A; calculating from the lowest bit to the highest bit of an output value X; calculating from the second lowest bit to the highest bit of the output value X in sequence according to the following formula: X i =(A1+……+A i-1 )', where i≥2, X i Indicates the output value X from the second lowest bit to the highest bit, A i-1 It represents the i-1th bit of the input value A from the lowest bit to the second highest bit; the values ​​of each bit of the output value X are arranged in order, and the calculation result X of the input value A and (A-1) is calculated.

[0007] Specifically, the lowest bit X1 of the output value X=1.

[0008] The present invention also provides a binary effective bit reflection device for calculating the XOR of an input value A and (A-1), comprising: a plurality of single-digit calculation units, wherein: the single-digit calculation unit comprises a NOT gate and an OR gate; the plurality of single-digit calculation units are arranged in sequence, and in the single-digit calculation unit of the i-th order, the input of the NOT gate comprises C i-1 , the output of the NOT gate includes X i , the input of the OR gate includes A i and C i-1 , the output of the OR gate includes C i , where A i Indicates the i-th bit of the input value A from the lowest bit to the highest bit, X i Indicates the i-th bit of the output value X from the lowest bit to the highest bit, C i-1 Indicates the carry input of the i-1th position in the calculation, C i Indicates the carry output of the i-th bit in the calculation; the NOT gate outputs of each single-digit calculation unit are arranged in order from the lowest bit to the highest bit to obtain the calculation result X of the input value A and (A-1) XOR.

[0009] Specifically, C0=0.

[0010] Specifically, the number of unit-digit calculation units is consistent with the number of digits of the input value A.

[0011] Specifically, the arrangement order of the plurality of unit-digit calculation units is consistent with the arrangement order of the input value A from the lowest bit to the highest bit.

[0012] Specifically, the NOT gate and OR gate of the i+1th bit unit calculation unit receive the C output of the adjacent last low bit unit calculation unit. i .

[0013] Specifically, the NOT gate and the OR gate in the single-digit calculation unit apply corresponding gate circuit structures.

[0014] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: a special calculation method and a special accelerator are provided for effective bit reflection calculation, and the calculation is simpler and more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of a single-digit calculation unit of a binary effective bit reflection device provided by the present invention;

[0016] Figure 2 This is a schematic diagram of the overall structure of the binary valid bit reflection device provided by the present invention. DETAILED DESCRIPTION

[0017] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0018] In a specific implementation, the effective bit reflector is a dedicated accelerator for binary calculation A⊕(A-1), that is, the result of calculating the XOR of A and (A-1). Its function is to output the rightmost bit of the input value A that is 1 and the data on its right as 1, and the remaining bits as 0. If the input is all 0, the output is all 1, and if the input is all 1, the output is the integer 1. For example, when the input value A is an 8-bit binary number 0101 1000, the calculation of A⊕(A-1) is 0000 1111, that is, 0101 1000=>0000 1111.

[0019] In the specific implementation, when calculating A⊕(A-1), (A-0000 0001) is calculated first, and then the XOR with A is calculated. In order to find a more simplified calculation method that can be realized through simple logic gate operations, the following further research and exploration were carried out.

[0020] In a specific implementation, taking 8-bit binary as an example (the calculation method and effective bit reflection device provided by the present invention have no limit on the number of bits of the input value, and 8 bits are only used as an example), the output value X=A⊕(A-00000001), A i Indicates the i-th bit of the input value A from the lowest bit to the highest bit (i.e. from right to left), X i represents the i-th bit of the output value X from the lowest bit to the highest bit (i.e. from right to left), where B=11111111, S=A-00000001=A+11111111 (ignoring overflow)=A+B, S i Indicates that when the 8-bit number S is added from the lowest bit to the highest bit, C i-1 Indicates the carry input of the previous level, S i The carry output generated is C i , let C i =0, we get:

[0021]

[0022] C i =A i ·B i +A i ·C i-1 +B i ·C i-1 =A i +C i-1

[0023]

[0024] After simplifying the above logic, we find that each Si The corresponding input bit A i After inversion and carry C i-1 Differential or obtained, output bit X i By A i With S i Different or get, further simplification found by the carry input C i-1 By negating it, we can get a simpler logical calculation method, as follows:

[0025]

[0026] When there are multiple inputs, the calculation method for the i-th bit of the output value is to add the 1st bit of the input value to the i-1th bit (binary addition calculation) and then invert it. From this, A can be calculated i ...A3A2A1=>X i …X3X2X1.

[0027] In summary, the binary significant bit reflection calculation method provided by the present invention can be obtained.

[0028] In the embodiment of the present invention, the calculation is performed in sequence from the lowest bit to the highest bit of the output value X; the calculation is performed in sequence from the second lowest bit to the highest bit of the output value X according to the following formula:

[0029] X i =(A1+……+A i-1 )',

[0030] Where i≥2, X i Indicates the output value X from the second lowest bit to the highest bit, A i-1 Represents the i-1th bit of the input value A from the lowest bit to the second highest bit.

[0031] In the embodiment of the present invention, the values ​​of each bit of the obtained output value X are arranged in order, and the calculation result X of the XOR of the input value A and (A-1) is calculated.

[0032] In the embodiment of the present invention, the least significant bit X1 of the output value X=1.

[0033] The superscript prime of the letter symbol involved in the present invention, such as ', indicates that the binary number represented by the corresponding letter symbol is inverted, for example, 0'=1.

[0034] In a specific implementation, (A1+...+A i-1 )' means that the 1st bit of the input value A is accumulated to the i-1th bit (binary addition calculation) and then inverted. When i=2, the formula should be expressed as (A1)', when i=3, the formula should be expressed as (A1+A2)', and so on.

[0035] In a specific implementation, taking a 4-bit input value A as an example, after calculating to obtain X1, X2, X3 and X4, the values ​​of each bit of the output value X are arranged in order from low to high, and X=X4 X3 X2 X1 is obtained. The values ​​of other bits are similar.

[0036] See also Figure 1 and Figure 2 , Figure 1 A schematic diagram of the structure of a single-digit calculation unit of a binary effective bit reflection device provided by the present invention, Figure 2 This is a schematic diagram of the overall structure of the binary valid bit reflection device provided by the present invention.

[0037] Based on the binary significant digit reflection calculation method provided by the present invention, the present invention provides a corresponding binary significant digit reflection device, that is, a dedicated accelerator.

[0038] In the embodiment of the present invention, the unit number calculation unit includes a NOT gate and an OR gate; the plurality of unit number calculation units are arranged in sequence, and in the i-th unit number calculation unit, the input of the NOT gate includes C i-1 , the output of the NOT gate includes X i , the input of the OR gate includes A i and C i-1 , the output of the OR gate includes C i , where A i Indicates the i-th bit of the input value A from the lowest bit to the highest bit, X i Indicates the i-th bit of the output value X from the lowest bit to the highest bit, C i-1 Indicates the carry input of the i-1th position in the calculation, C i Indicates the carry output of the i-th bit in the calculation; the NOT gate outputs of each single-digit calculation unit are arranged in order from the lowest bit to the highest bit to obtain the calculation result X of the input value A and (A-1) XOR.

[0039] In the embodiment of the present invention, the input C0 of the NOT gate and the OR gate of the least significant bit (the first bit) of the unit number calculation unit is 0.

[0040] In the embodiment of the present invention, the number of the unit-digit calculation units is consistent with the number of digits of the input value A.

[0041] In the embodiment of the present invention, the arrangement order of the plurality of single-digit calculation units is consistent with the arrangement order of the input value A from the lowest bit to the highest bit.

[0042] In the embodiment of the present invention, the NOT gate and the OR gate of the i+1th bit unit number calculation unit receive the C output by the adjacent last low bit unit number calculation unit. i .

[0043] In the embodiment of the present invention, the NOT gate and the OR gate in the single-digit calculation unit apply corresponding gate circuit structures.

[0044] In a specific implementation, taking the input value A=0101 1000 as an example, C0=0, the lowest bit (the first bit) ( Figure 2 The NOT gate outputs 1, that is, X2 is 1, the inputs of the OR gate of the first unit digit calculation unit are A1=0 and C0=0, and the output of the OR gate is C1=0; C1 serves as the input of the NOT gate and the OR gate of the second lowest unit digit calculation unit, where the NOT gate outputs 1, that is, X2 is 1, the inputs of the OR gate are A2=0 and C1=0, and the output of the OR gate is C2=0. Subsequent calculations can be performed by analogy accordingly to obtain X1, X2...X8, and finally arranged in order from the lowest bit to the highest bit to obtain X=0000 1111.

[0045] In a specific implementation, based on the binary significant digit reflection calculation method and the binary significant digit reflection device provided by the present invention, the XOR calculation of the input value A and (A-1) can be performed more simply and efficiently.

Claims

1. A binary effective bit reflection calculation method, characterized in that: Used to calculate the XOR of input value A and (A-1), including: Receive input value A; Calculate from the lowest bit to the highest bit of the output value X; The output value X is calculated from the second lowest bit to the highest bit in sequence according to the following formula: X i =(A1+……+A i-1 )', where i≥2, X i Indicates the output value X from the second lowest bit to the highest bit, A i-1 Represents the i-1th bit of the input value A from the lowest bit to the second highest bit; Arrange the values ​​of each bit of the obtained output value X in order, and calculate the calculation result X of the input value A and (A-1) XOR.

2. The binary significant bit reflection calculation method according to claim 1, characterized in that: The lowest bit X1 of the output value X is 1.

3. A binary effective bit reflection device, characterized in that: Used to calculate the XOR of input value A and (A-1), including: a plurality of single-digit calculation units, wherein: The single-digit calculation unit includes a NOT gate and an OR gate; Multiple single-digit calculation units are arranged in order. In the single-digit calculation unit of the i-th order, the input of the NOT gate includes C i-1 , the output of the NOT gate includes X i , the input of the OR gate includes A i and C i-1 , the output of the OR gate includes C i , where A i Indicates the i-th bit of the input value A from the lowest bit to the highest bit, X i Indicates the i-th bit of the output value X from the lowest bit to the highest bit, C i-1 Indicates the carry input of the i-1th position in the calculation, C i Indicates the carry output of the i-th bit in the calculation; the NOT gate outputs of each single-digit calculation unit are arranged in order from the lowest bit to the highest bit to obtain the calculation result X of the input value A and (A-1) XOR.

4. The binary effective bit reflection device according to claim 3, characterized in that: C0＝0。 5. The binary effective bit reflection device according to claim 3, characterized in that: The number of single-digit calculation units is consistent with the number of digits of the input value A.

6. The binary effective bit reflection device according to claim 3, characterized in that: The arrangement order of the plurality of single-digit calculation units is consistent with the arrangement order of the input value A from the least significant bit to the most significant bit.

7. The binary effective bit reflection device according to claim 3, characterized in that: The NOT gate and OR gate of the i+1th bit unit calculation unit receive the C output of the adjacent last low bit unit calculation unit. i .

8. The binary effective bit reflection device according to claim 3, characterized in that: The NOT gate and OR gate in the single-digit calculation unit apply the corresponding gate circuit structure.

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