SiC groove terminal structure manufacturing method

By using high-energy ion implantation in the SiC trench MOSFET to form multiple P+ regions, forming a gradient trench terminal ring in the terminal region and defining a gate trench pattern in the cellular region, forming a side wall to form a P-type protection area at the bottom of the trench, the problem of electric field concentration in the deep pplus transition area and small JTE terminal structure process window is solved, and the terminal length shortens and performance improvement is achieved.

CN119653807AActive Publication Date: 2025-03-18BEIJING XINGAN TECH CO LTD
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Patent Information

Application Number
CN202411952722.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-27
Publication Date
2025-03-18
Estimated Expiration
2044-12-27

AI Technical Summary

Technical Problem

In SiC trench MOSFETs, the electric field is concentrated in the deep pplus transition zone during the reverse withstand voltage, resulting in performance loss. The commonly used JTE terminal structure has a small process window, high injection sensitivity, and is greatly affected by the interface charge.

Method used

A SiC trench terminal structure production method is adopted to form a plurality of P+ regions by implanting high energy ion in the N-epitaxy layer, divided into a terminal region and a cell region, and a gradient trench terminal ring is formed in the terminal region and a gate trench pattern is defined in the cell region, and a side wall is formed to form a P-type protection region at the bottom of the trench.

Benefits of technology

This method reduces the electric field strength of the deep P+ transition zone at the terminal edge, shortens the terminal length, does not add additional mask plates and process steps, and is compatible with the single-trench + deep pplus solution, improving the performance and reliability of the terminal.

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Abstract

The invention discloses a manufacturing method of a SiC groove terminal structure, and belongs to the technical field of semiconductor manufacturing. Comprising the following steps: forming a plurality of P + regions in an N-epitaxial layer to divide the N-epitaxial layer into a terminal region and a plurality of cellular regions, forming a first Pwell region in the terminal region, and respectively forming a JFET injection region, a second Pwell region and an N + region in the cellular regions; defining a gradual change groove terminal ring in the terminal area and defining a grid electrode groove pattern on the cellular area through photoresist; forming a plurality of terminal region grooves of which the depths are gradually increased in the direction of the cellular region in the terminal region through the pattern, and forming a grid electrode groove in the cellular region; and forming side walls on the terminal region trench and the gate trench, and forming a P-type protection region at the bottom. And removing the side wall and the hard mask layer, and further forming a grid electrode, a source electrode and a drain electrode. According to the method, a mask plate required by the process is not added, a single groove and deep pplus scheme is compatible, and the problem of electric field concentration of a deep pplus transition region during reverse voltage withstanding is solved.
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