Display device and mobile electronic device including the same

Abstract

A display device and a mobile electronic device including the same are provided. According to one or more embodiments, a display device may include a display panel including a display area in which a light emitting element is positioned and a non-display area, the non-display area being located outside the display area in plan view and including an impermeable area and an anti-cracking area, the impermeable area being located outside a package area, the anti-cracking area being located outside the package area, and the anti-cracking area being located outside the package area. The anti-cracking area is located on the outer side of the anti-seepage area, and at least one corner of the display panel is in a double-line shape.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0125878 filed in the Korean Intellectual Property Office on September 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device and a mobile electronic device including the display device. Background Art

[0004] Wearable devices in which a focus is formed at a distance close to the user's eyes have been developed in the form of glasses or helmets. For example, the wearable device may be a head mounted display (HMD) device or augmented reality (AR) glasses. The wearable device provides an AR screen or a virtual reality (VR) screen to the user.

[0005] Wearable devices such as HMD devices or AR glasses may appropriately use a display specification of at least 2000 PPI (pixels per inch) so that users can use it for a long time without dizziness. For this reason, organic light emitting diode on silicon (OLEDoS) technology is emerging as a high-resolution small organic light emitting display device. OLEDoS is a technology in which an organic light emitting diode (OLED) is positioned on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is positioned.

[0006] Generally, a method of manufacturing a display device includes manufacturing a plurality of display panels (a plurality of units) on one mother substrate, a sawing process of cutting the manufactured display panels from the mother substrate, and a grinding process of polishing a corner of each display panel into a rounded shape after the sawing process. The conventional method of manufacturing a display device may cause a problem in which the display panel is damaged during the sawing process and / or the grinding process, or moisture and oxygen penetrate into the display panel due to the damage. Summary of the invention

[0007] Aspects of the present disclosure provide a display device and a mobile electronic device including the display device, which can protect a display panel from cracks that may occur during a sawing process and a grinding process and can reduce or prevent moisture and oxygen from penetrating into the display panel.

[0008] According to one or more embodiments of the present disclosure, a display device may include a display panel including a display area and a non-display area, a light-emitting element is positioned in the display area, the non-display area is located outside the display area in a plan view and includes an anti-seepage area and an anti-cracking area, the anti-seepage area is located outside the packaging area, the anti-cracking area is located outside the anti-seepage area and is in a double-line shape at at least one corner of the display panel.

[0009] The display device may also include a driving circuit located at one end of the display panel, wherein the display panel is defined as including a first corner and a second corner adjacent to the driving circuit, and a third corner and a fourth corner not adjacent to the driving circuit, and wherein the anti-crack area is in a double-line shape at the third corner and the fourth corner of the display panel.

[0010] The crack prevention area may be in a single line shape at the first corner and the second corner of the display panel.

[0011] The crack prevention area may be in a right triangle shape at a third corner or a fourth corner of the display panel.

[0012] At the third corner or the fourth corner of the display panel, the anti-crack area may include a first portion forming a portion of a first side surface of the display panel, a second portion extending from the first portion in a vertical direction to form a portion of a second side surface of the display panel, and a third portion connecting the first portion to the second portion in a diagonal direction.

[0013] At the third corner or the fourth corner of the display panel, the anti-seepage area may be located inside the third portion of the crack prevention area to be parallel to the third portion.

[0014] At the third corner or the fourth corner of the display panel, the dummy structure may be located in the crack prevention area having a right triangle shape.

[0015] The display panel may include a semiconductor backplane including a semiconductor substrate, a light emitting element backplane having a plurality of metal layers, and a light emitting element layer located above the light emitting element backplane.

[0016] The stacked structure of the barrier region may include a plurality of barrier metal layers at the same layer as the plurality of metal layers of the light emitting element back panel.

[0017] The stack structure of the crack prevention area may include a plurality of crack prevention metal layers at the same layer as the plurality of metal layers of the light emitting element back plate.

[0018] According to one or more embodiments of the present disclosure, a mobile electronic device may include a display device, the display device including a display panel including a display area and a non-display area, a light-emitting element is positioned in the display area, the non-display area is located outside the display area and includes an anti-seepage area and an anti-crack area, the anti-seepage area is located outside the packaging area, and the anti-crack area is located outside the anti-seepage area in a double-line shape at at least one corner of the display panel.

[0019] The mobile electronic device may also include a driving circuit located at one end of the display panel, wherein the display panel includes a first corner and a second corner adjacent to the driving circuit, and a third corner and a fourth corner adjacent to the non-driving circuit, and wherein the anti-crack area is in a double-line shape at the third corner and the fourth corner of the display panel.

[0020] The crack prevention area may be in a single line shape at the first corner and the second corner of the display panel.

[0021] The crack prevention area may be in a right triangle shape at a third corner or a fourth corner of the display panel.

[0022] At the third corner or the fourth corner of the display panel, the anti-crack area may include a first portion forming a portion of a first side surface of the display panel, a second portion extending from the first portion in a vertical direction to form a portion of a second side surface of the display panel, and a third portion connecting the first portion to the second portion in a diagonal direction.

[0023] At the third corner or the fourth corner of the display panel, the anti-seepage area may be located inside the third portion of the crack prevention area to be parallel to the third portion.

[0024] At the third corner or the fourth corner of the display panel, the dummy structure may be located in the crack prevention area having a right triangle shape.

[0025] The display panel may include a semiconductor backplane including a semiconductor substrate, a light emitting element backplane having a plurality of metal layers, and a light emitting element layer located above the light emitting element backplane.

[0026] The stacked structure of the barrier region may include a plurality of barrier metal layers at the same layer as the plurality of metal layers of the light emitting element back panel.

[0027] The stack structure of the crack prevention area may include a plurality of crack prevention metal layers at the same layer as the plurality of metal layers of the light emitting element back plate.

[0028] According to the display device and the mobile electronic device including the display device, according to the embodiments, it is possible to protect the display panel from cracks that may occur during the sawing process and the grinding process, and reduce or prevent the penetration of moisture and oxygen into the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0030] Figure 1 is a perspective view showing a head mounted display device according to one or more embodiments;

[0031] Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head mounted display device;

[0032] Figure 3 is a perspective view showing a head mounted display device according to one or more embodiments;

[0033] Figure 4 is an exploded perspective view showing a display device according to one or more embodiments;

[0034] Figure 5 It is shown Figure 4 An example layout diagram of a display panel shown in FIG.

[0035] Figure 6 is a block diagram showing a display device according to one or more embodiments;

[0036] Figure 7 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments;

[0037] Figure 8 is a layout diagram showing pixels of a display area according to one or more embodiments;

[0038] Fig. 9 is shown along Figure 8 A cross-sectional view of an example of a display device taken along line AA';

[0039] Fig.10 is a diagram showing an example of a mother substrate for manufacturing a display panel according to one or more embodiments;

[0040] Fig.11 is an enlarged plan view of a third corner of a display panel according to one or more embodiments;

[0041] Fig.12 is an enlarged plan view of a fourth corner of a display panel according to one or more embodiments; and

[0042] Fig.13 is a partial cross-sectional view of a display panel, illustrating a stacked structure of a crack prevention area and an anti-seepage area according to one or more embodiments. DETAILED DESCRIPTION

[0043] By referring to the detailed description and drawings of the embodiments, various aspects of some embodiments of the present disclosure and the methods for implementing them can be more easily understood. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand various aspects of the present disclosure may be omitted. Unless otherwise stated, the same reference numerals, symbols or combinations thereof refer to the same elements throughout the drawings and written descriptions, and therefore their repeated descriptions may be omitted.

[0044] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited only to the embodiments shown herein. The use of "can", "may" or "maynot" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and replacements within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interlocks and drives are possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0045] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0046] Various embodiments are described herein with reference to schematic cross-sectional illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are contemplated. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as being limited to the shapes of the elements, layers, or regions shown, but rather include deviations in shape resulting from, for example, manufacturing.

[0047] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0048] Spatially relative terms such as "beneath", "below", "lower", "lowerside", "under", "above", "upper", "upper side", etc. may be used herein for convenience of explanation to describe the relationship between one element or feature and another (some) element or feature as shown in the figures. It should be understood that in addition to the orientations depicted in the figures, spatially relative terms are intended to also include different orientations of the device in use or in operation. For example, if the device in the figures is turned over, the elements described as being "below", "beneath" or "under" other elements or features will then be oriented to be "above" other elements or features. Therefore, the example terms "below" and "under" can include both the orientations of above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when the first portion is described as being disposed “on” the second portion, this indicates that the first portion is disposed at the upper side or lower side of the second portion, without being limited to the upper side thereof based on the gravity direction.

[0049] Furthermore, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-sectional view obtained by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapped" means that a first object may be located above or below a second object, or to the side of the second object, and vice versa. Additionally, the term "overlap" may include stacking, facing or facing, extending above, covering or partially covering, or any other suitable term that a person of ordinary skill in the art would appreciate and understand. The expression "non-overlapping" may include expressions such as "separated from" or "placed beside" or "offset from" and any other suitable equivalents that a person of ordinary skill in the art would appreciate and understand.

[0050] It should be understood that when an element, layer, region, or component is referred to as being "formed" "on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it can be directly formed on, directly on, directly connected to, or coupled to, another element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or coupled to, another element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. In addition, this may generally mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or coupled to, another layer, region, or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, and / or the like. In describing embodiments, unless explicitly described as directly connected, expressions of connection indicate electrical connection, and "directly connected / directly coupled" or "directly on" means that one component is directly connected or coupled to another component, or is located on another component without intermediate components.

[0051] In addition, in this specification, when a part of a layer, film, region, plate or the like is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate or the like is formed "under" another part, this includes not only the situation that the part is "directly" "under" another part, but also the situation that there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts such as "between", "immediately adjacent" or "adjacent" and "directly adjacent" can be interpreted similarly. It should be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0052] For the purposes of this disclosure, expressions following a list of elements such as "at least one of" or "any of" or "one or more of" modify the entire list of elements, rather than modifying individual elements in the list. For example, "at least one of X, Y, and Z," "at least one of X, Y, or Z," "at least one selected from the cluster consisting of X, Y, and Z," and "at least one selected from the cluster consisting of X, Y, or Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expressions "at least one of A and B" and "at least one of A or B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases following a list of elements modify the entire list of elements and do not modify the individual elements of the list.

[0053] It should be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or parts, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are only used to distinguish an element, member, component, area, region, layer, part or part from another element, member, component, area, region, layer, part or part. Therefore, the first element, component, area, layer or part discussed below can be referred to as the second element, component, area, layer or part, without departing from the spirit and scope of the present disclosure. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish different categories or sets of elements. For the sake of brevity, the terms "first", "second", etc. can respectively represent "first category (or first set)", "second category (or second set)", etc.

[0054] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0055] The terms used herein are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. Unless otherwise clearly indicated in the context, the singular forms "a" and "an" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It should also be understood that when the terms "comprises", "comprising", "have", "having", "includes" and "including" are used in this specification, the existence of the stated features, wholes, steps, operations, elements and / or parts is specified, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or clusters thereof is not excluded.

[0056] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the errors associated with the measurement and the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within the acceptable deviation range of the particular value determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0057] In some embodiments, known structures and devices may be described in conjunction with one or more functional blocks (e.g., block diagrams), units and / or modules in the accompanying drawings to avoid unnecessary blurring of various embodiments. It will be appreciated by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, single components, microprocessors, hard-wired circuits, storage elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and can be optionally driven by firmware and / or software. In addition, each block, unit and / or module may be implemented by dedicated hardware, or by a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs functions different from those of dedicated hardware. In addition, in some embodiments, without departing from the scope of the present disclosure, blocks, units and / or modules may be physically separated into two or more interactive single blocks, units and / or modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0059] Figure 1 is a perspective view showing a head mounted display device according to one or more embodiments. Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head mounted display device.

[0060] Reference Figure 1 and Figure 2 According to one or more embodiments, the head-mounted display device 1 includes a first display device 10_1, a second display device 10_2, a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted strap 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector.

[0061] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is connected to the reference Figures 4 to 13 The display devices 10 described are substantially the same. Therefore, the description of the first display device 10_1 and the second display device 10_2 will be referred to with reference to Figures 4 to 13 Description instead.

[0062] The first optical member 151 may be positioned between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be positioned between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0063] The middle frame 160 may be positioned between the first display device 10_1 and the control circuit board 170, and may be positioned between the second display device 10_2 and the control circuit board 170. The middle frame 160 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0064] The control circuit board 170 may be positioned between the middle frame 160 and the display device housing 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source input from the outside into digital video data DATA (see Figure 6 ), and transmits the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0065] The control circuit board 170 may transmit digital video data DATA corresponding to a left-eye image suitable for the left eye of the user to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image suitable for the right eye of the user to the second display device 10_2. Alternatively, the control circuit board 170 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0066] The display device housing 110 is used to store the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 is positioned to cover one open surface of the display device housing 110. The housing cover 120 may include a first eyepiece 131 on which the user's left eye is positioned and a second eyepiece 132 on which the user's right eye is positioned. Although in Figure 1 and Figure 21 and 132 are shown to be separately positioned, but the present disclosure is not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be integrated into one piece.

[0067] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may observe the image of the first display device 10_1 magnified into a virtual image by the first optical member 151 through the first eyepiece 131, and may observe the image of the second display device 10_2 magnified into a virtual image by the second optical member 152 through the second eyepiece 132.

[0068] The head-mounted strap 140 is used to fix the display device housing 110 to the user's head, so that the state in which the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are respectively positioned at the user's left eye and the user's right eye can be maintained. When the display device housing 110 is implemented as a light and small device, the head-mounted display device 1 may include a glasses frame, such as Figure 3 As shown in , the headband 140 is replaced.

[0069] In addition, the head mounted display device 1 may further include a battery for supplying power, an external memory slot capable of storing an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0070] Figure 3 is a perspective view showing a head mounted display device according to one or more embodiments.

[0071] Reference Figure 3 The head mounted display device 1_1 according to one or more embodiments may be a glasses type display device in which the display device housing 120_1 is implemented as a relatively light and relatively small device. The head mounted display device 1_1 according to one or more embodiments may include a display device 10_3, a left lens 311, a right lens 312, a support frame 350, temples 341 and 342, an optical member 320, an optical path changing member 330, and a display device housing 120_1.

[0072] Figure 3 The display device 10_3 shown in FIG. Figures 4 to 13 The display device 10 described is substantially the same as that of FIG. 1 . Therefore, the description of the display device 10_3 will be referred to as Figures 4 to 13 Description instead.

[0073] The display device housing 120_1 may include a display device 10_3, an optical member 320, and an optical path changing member 330. An image displayed on the display device 10_3 may be enlarged by the optical member 320, may have an optical path changed by the optical path changing member 330, and may be provided to the right eye of the user through the right lens 312. Therefore, the user may observe an augmented reality image in which a virtual image displayed on the display device 10_3 observed by the right eye and a real image seen through the right lens 312 are combined.

[0074] although Figure 3 3 shows that the display device housing 120_1 is positioned at the right end of the support frame 350, but the present disclosure is not limited thereto. For example, the display device housing 120_1 may be positioned at the left end of the support frame 350, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device housing 120_1 may be positioned at both the left and right ends of the support frame 350, and the user may observe the image displayed on the display device 10_3 through both the left eye and the right eye.

[0075] Figure 4 is an exploded perspective view showing a display device according to one or more embodiments. Figure 5 It is shown Figure 4 Layout diagram of an example of a display panel shown in . Figure 6 is a block diagram illustrating a display device according to one or more embodiments.

[0076] Reference Figure 4 and Figure 5 , the display device 10 according to one or more embodiments is a device for displaying a moving image or a still image. The display device 10 according to one or more embodiments may be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), or the like. For example, the display device 10 may be applied as a display of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 may be applied to a smart watch, a watch phone, a head mounted display (HMD) for realizing virtual reality and augmented reality, or the like.

[0077] The display device 10 according to one or more embodiments includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a timing control circuit 440 , and a power supply circuit 450 .

[0078] The display panel 410 may have a planar shape similar to a quadrilateral shape. For example, the display panel 410 may have a planar shape similar to a quadrilateral shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 410, the corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be right angles or rounded corners having a curvature (e.g., a predetermined curvature). The planar shape of the display panel 410 is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 410, but the present disclosure is not limited thereto.

[0079] like Figure 5 As shown in , the display panel 410 includes a display area DAA for displaying an image and a non-display area NDA for not displaying an image.

[0080] like Figure 6 As shown in FIG. 1 , the display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0081] The plurality of pixels PX include a light emitting element LE for emitting light (see Figure 7 ). A plurality of pixels PX may be arranged in a matrix in the first direction DR1 and the second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 while being arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 while being arranged in the first direction DR1.

[0082] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0083] Each of the plurality of pixels includes a plurality of sub-pixels SP1, SP2 and SP3 (see Fig. 9 ). The plurality of sub-pixels SP1, SP2 and SP3 may include: Figure 7 The plurality of pixel transistors shown in the figure can be formed by a semiconductor process and can be positioned on a semiconductor substrate SSUB (see Fig. 9 ). For example, a plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0084] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and may emit light from the light emitting element LE according to the data voltage.

[0085] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0086] The scan driving area SDA may be an area where the scan driver 510 and the emission driver 520 are located. Figure 5 , the scan driver 510 is shown to be positioned on the left side of the display area DAA, and the emission driver 520 is positioned on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 510 and the emission driver 520 may be positioned on both the left and right sides of the display area DAA.

[0087] The scan driver 510 includes a plurality of scan transistors, and the emission driver 520 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see Fig. 9 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed by CMOS.

[0088] The scan driver 510 may include a write scan signal driver 511, a control scan signal driver 512, and a bias scan signal driver 513. Each of the write scan signal driver 511, the control scan signal driver 512, and the bias scan signal driver 513 may receive a scan timing control signal SCS from the timing control circuit 440. The write scan signal driver 511 may generate write scan signals in response to the scan timing control signal SCS of the timing control circuit 440, and may sequentially output them to the write scan lines GWL. The control scan signal driver 512 may generate control scan signals in response to the scan timing control signal SCS, and may sequentially output them to the control scan lines GCL. The bias scan signal driver 513 may generate bias scan signals in response to the scan timing control signal SCS, and may sequentially output them to the bias scan lines EBL.

[0089] The emission driver 520 includes a first emission control driver 521 and a second emission control driver 522. Each of the first emission control driver 521 and the second emission control driver 522 may receive an emission timing control signal ECS from the timing control circuit 440. The first emission control driver 521 may generate a first emission control signal in response to the emission timing control signal ECS, and may sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 522 may generate a second emission control signal in response to the emission timing control signal ECS, and may sequentially output the second emission control signal to the second emission control line EL2.

[0090] The data driving area DDA may be an area where the data driver 530 is located. The data driver 530 may include a plurality of data transistors, and the plurality of data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Fig. 9 For example, the plurality of data transistors may be formed of CMOS.

[0091] The data driver 530 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 440. The data driver 530 converts the digital video data DATA into an analog data voltage in response to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 510, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0092] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by the cover layer CVL (see Fig. 9 ) and polarizer POL (see Fig. 9 )cover.

[0093] The heat dissipation layer 420 may overlap the display panel 410 in the third direction DR3 which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be positioned on one surface, for example, on the rear surface of the display panel 410. The heat dissipation layer 420 serves to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include a metal layer having high thermal conductivity such as silver (Ag), copper (Cu), or aluminum (Al), or a layer including graphite.

[0094] The circuit board 430 may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 44 shows that the circuit board 430 is unfolded, but the circuit board 430 may be bent. In this case, one end of the circuit board 430 may be positioned on the rear surface of the display panel 410. One end of the circuit board 430 may be opposite to the other end of the circuit board 430 connected to the plurality of pads PD of the pad area PDA of the display panel 410 by using a conductive adhesive member.

[0095] The timing control circuit 440 may receive digital video data DATA and a timing signal from the outside. The timing control circuit 440 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 410 in response to the timing signal. The timing control circuit 440 may output the scan timing control signal SCS to the scan driver 510, and may output the emission timing control signal ECS to the emission driver 520. The timing control circuit 440 may output the digital video data DATA and the data timing control signal DCS to the data driver 530.

[0096] The power supply circuit 450 may generate a plurality of panel driving voltages in response to a power supply voltage from the outside. For example, the power supply circuit 450 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 410. Figure 7 A first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT are described.

[0097] Each of the timing control circuit 440 and the power supply circuit 450 may be formed as an integrated circuit (IC) and may be attached to one surface of the circuit board 430. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 440 may be supplied to the display panel 410 through the circuit board 430. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 450 may be supplied to the display panel 410 through the circuit board 430.

[0098] Figure 7 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments.

[0099] Reference Figure 7, the first sub-pixel SP1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first sub-pixel SP1 may be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be lower than the third drive voltage VINT. The second drive voltage VDD may be higher than the third drive voltage VINT.

[0100] The first sub-pixel SP1 includes a light emitting element LE and a pixel driving circuit PC connected to the light emitting element LE. The pixel driving circuit PC includes a plurality of transistors T1 to T6, a first capacitor CP1, and a second capacitor CP2.

[0101] The light emitting element LE emits light in response to the driving current flowing through the channel of the first transistor T1. The emission amount of the light emitting element LE may be proportional to the driving current. The light emitting element LE may be positioned between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode (or a pixel electrode), and the second electrode of the light emitting element LE may be a cathode (or a common electrode). The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer positioned between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode, in which case the light emitting element LE may be a micro light emitting diode.

[0102] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (hereinafter referred to as a "driving current") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0103] The second transistor T2 may be positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL may be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0104] The third transistor T3 may be positioned between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. For this reason, since the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0105] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Therefore, the driving current Ids of the first transistor T1 may be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0106] The fifth transistor T5 may be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0107] The sixth transistor T6 may be positioned between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0108] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0109] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0110] The first node N1 is a junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0111] Each of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, one or more of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, and the remaining transistors may be N-type MOSFETs.

[0112] Despite Figure 7 FIG. 4 shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2, but it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 7 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 7 Those shown in .

[0113] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be combined with Figure 7 The equivalent circuit diagram of the first sub-pixel SP1 described above is substantially the same. Therefore, descriptions of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 are omitted in this specification.

[0114] Figure 8 is a diagram showing a layout of pixels of a display area according to one or more embodiments.

[0115] Reference Figure 8 , each of the plurality of pixels PX includes a first emission area EA1 as an emission area of ​​a first sub-pixel SP1, a second emission area EA2 as an emission area of ​​a second sub-pixel SP2, and a third emission area EA3 as an emission area of ​​a third sub-pixel SP3.

[0116] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape such as a rectangle, a square, or a rhombus in a plan view. For example, the first emission area EA1 may have a rectangular shape with a short side in the first direction DR1 and a long side in the second direction DR2 in a plan view. In addition, each of the second emission area EA2 and the third emission area EA3 may have a rectangular shape with a long side in the first direction DR1 and a short side in the second direction DR2 in a plan view.

[0117] The length of the first emission region EA1 in the first direction DR1 may be smaller than the length of the second emission region EA2 in the first direction DR1, and may be smaller than the length of the third emission region EA3 in the first direction DR1. The length of the second emission region EA2 in the first direction DR1 and the length of the third emission region EA3 in the first direction DR1 may be substantially the same.

[0118] The length of the first emission region EA1 in the second direction DR2 may be greater than the sum of the lengths of the second emission region EA2 and the third emission region EA3 in the second direction DR2. The length of the second emission region EA2 in the second direction DR2 may be greater than the length of the third emission region EA3 in the second direction DR2.

[0119] Despite Figure 8 , each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 is shown to have a rectangular shape in a plan view, but the present disclosure is not limited thereto. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape, a circular shape, or an elliptical shape in addition to a quadrilateral shape in a plan view.

[0120] In each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be different.

[0121] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the light of the first color may be light of a blue wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a red wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 370 nm to about 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 600 nm to about 750 nm.

[0122] exist Figure 8 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission areas.

[0123] In addition, the layout of the emission regions of the plurality of pixels PX is not limited to Figure 8 For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged in the first direction DR1, in which the emission regions are arranged in a diamond shape, or in a plurality of pixels PX. Structure (for example, RGBG matrix structure, Matrix structure, structure or RGBG structure, and is a registered trademark of Samsung Display Co., Ltd. of South Korea), or a hexagonal structure in which emission areas having a hexagonal shape in a plan view are arranged side by side.

[0124] Fig. 9 is shown along Figure 8 A cross-sectional view of an example of a display device taken along line AA′.

[0125] Reference Fig. 9 The display panel 410 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, a cover layer CVL and a polarizing plate POL.

[0126] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. Figure 4 The first transistor T1 to the sixth transistor T6 are described.

[0127] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be positioned on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity may be a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, when the first type of impurity may be an n-type impurity, the second type of impurity may be a p-type impurity.

[0128] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH positioned between the source region SA and the drain region DA.

[0129] A lower insulating film BINS may be disposed between the gate electrode GE and the well area WA. A side insulating film SINS may be disposed on a side surface of the gate electrode GE. The side insulating film SINS may be disposed on the lower insulating film BINS.

[0130] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be positioned on one side of the gate electrode GE, and the drain region DA may be positioned on the other side of the gate electrode GE.

[0131] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 positioned between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 positioned between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the plurality of pixel transistors PTR may be increased, thereby reducing or preventing the possibility of punch-through and hot carrier phenomena that may be caused by a short channel.

[0132] A first semiconductor insulating layer SINS1 may be positioned on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0133] A second semiconductor insulating layer SINS2 may be positioned on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0134] A plurality of contact terminals CTE may be positioned on the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be connected to the gate electrode GE, the source area SA, and the drain area DA of the pixel transistor PTR, respectively, through holes penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0135] A third semiconductor insulating layer SINS3 may be positioned on the side surface of each of the plurality of contact terminals CTE. A top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0136] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as polyimide). In this case, the pixel transistor may be positioned on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0137] The light emitting element back plate EBP includes first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of via holes VA1 to VA10, and a step layer STPL. In addition, the light emitting element back plate EBP includes a plurality of interlayer insulating layers INS1 to INS10.

[0138] The first metal layer ML1 to the eighth metal layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing Figure 7 The circuit of the first sub-pixel SP1 shown in FIG. That is, the first to sixth transistors T1 to T6 are formed only on the semiconductor backplane SBP, and the connection between the first to sixth transistors T1 to T6 and the first capacitor CP1 and the second capacitor CP2 is realized through the first to eighth metal layers ML1 to ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE is also realized through the first to eighth metal layers ML1 to ML8.

[0139] The first interlayer insulating layer INS1 may be positioned on the semiconductor backplane SBP. Each of the plurality of first vias VA1 may penetrate the first interlayer insulating layer INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the plurality of first metal layers ML1 may be positioned on the first interlayer insulating layer INS1 and may be connected to the first vias VA1.

[0140] The second interlayer insulating layer INS2 may be positioned on the first interlayer insulating layer INS1 and the plurality of first metal layers ML1. Each of the plurality of second via holes VA2 may penetrate the second interlayer insulating layer INS2 and may be connected to the exposed first metal layer ML1. Each of the plurality of second metal layers ML2 may be positioned on the second interlayer insulating layer INS2 and may be connected to the second via holes VA2.

[0141] The third interlayer insulating layer INS3 may be positioned on the second interlayer insulating layer INS2 and the plurality of second metal layers ML2. Each of the plurality of third via holes VA3 may penetrate the third interlayer insulating layer INS3 and may be connected to the exposed second metal layer ML2. Each of the plurality of third metal layers ML3 may be positioned on the third interlayer insulating layer INS3 and may be connected to the third via holes VA3.

[0142] The fourth interlayer insulating layer INS4 may be positioned on the third interlayer insulating layer INS3 and the plurality of third metal layers ML3. Each of the plurality of fourth vias VA4 may penetrate the fourth interlayer insulating layer INS4 and may be connected to the exposed third metal layer ML3. Each of the plurality of fourth metal layers ML4 may be positioned on the fourth interlayer insulating layer INS4 and may be connected to the fourth via VA4.

[0143] The fifth interlayer insulating layer INS5 may be positioned on the fourth interlayer insulating layer INS4 and the plurality of fourth metal layers ML4. Each of the plurality of fifth vias VA5 may penetrate the fifth interlayer insulating layer INS5 and may be connected to the exposed fourth metal layer ML4. Each of the plurality of fifth metal layers ML5 may be positioned on the fifth interlayer insulating layer INS5 and may be connected to the fifth via VA5.

[0144] The sixth interlayer insulating layer INS6 may be positioned on the fifth interlayer insulating layer INS5 and the plurality of fifth metal layers ML5. Each of the plurality of sixth vias VA6 may penetrate the sixth interlayer insulating layer INS6 and may be connected to the exposed fifth metal layer ML5. Each of the plurality of sixth metal layers ML6 may be positioned on the sixth interlayer insulating layer INS6 and may be connected to the sixth via VA6.

[0145] The seventh interlayer insulating layer INS7 may be positioned on the sixth interlayer insulating layer INS6 and the plurality of sixth metal layers ML6. Each of the plurality of seventh vias VA7 may penetrate the seventh interlayer insulating layer INS7 and may be connected to the exposed sixth metal layer ML6. Each of the plurality of seventh metal layers ML7 may be positioned on the seventh interlayer insulating layer INS7 and may be connected to the seventh via VA7.

[0146] The eighth interlayer insulating layer INS8 may be positioned on the seventh interlayer insulating layer INS7 and the plurality of seventh metal layers ML7. Each of the plurality of eighth vias VA8 may penetrate the eighth interlayer insulating layer INS8 and may be connected to the exposed seventh metal layer ML7. Each of the plurality of eighth metal layers ML8 may be positioned on the eighth interlayer insulating layer INS8 and may be connected to the eighth via VA8.

[0147] The first metal layer ML1 to the eighth metal layer ML8 and the first via hole VA1 to the eighth via hole VA8 may be formed of substantially the same material. The first metal layer ML1 to the eighth metal layer ML8 and the first via hole VA1 to the eighth via hole VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The first via hole VA1 to the eighth via hole VA8 may be made of substantially the same material. The first interlayer insulating layer INS1 to the eighth interlayer insulating layer INS8 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0148] The thickness of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be respectively greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 may be about 1000 Å. The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be about 1000 mm. And the thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6 may be about

[0149] The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, the thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be approximately The thickness of each of the seventh via hole VA7 and the eighth via hole VA8 may be about

[0151] The ninth interlayer insulating layer INS9 may be positioned on the eighth interlayer insulating layer INS8 and the plurality of eighth metal layers ML8. The ninth interlayer insulating layer INS9 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0152] Each of the plurality of ninth via holes VA9 may penetrate the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth metal layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the ninth via hole VA9 may be about 100 mm.

[0153] Each of the plurality of first reflective electrodes RL1 may be positioned on the ninth interlayer insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0154] Each of the second reflective electrodes RL2 may be positioned on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the second reflective electrode RL2 may be made of titanium nitride (TiN).

[0155] In the first sub-pixel SP1, the step layer STPL may be positioned on the second reflective electrode RL2. The step layer STPL may not be positioned in each of the second sub-pixel SP2 and the third sub-pixel SP3. In order to appropriately reflect the light of the first color emitted from the first light emitting layer IL1 of the first sub-pixel SP1, the thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first light emitting layer IL1 to the fourth reflective electrode RL4. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) is formed by a base inorganic layer, but the present disclosure is not limited thereto. The thickness of the step layer STPL may be about

[0157] In the first sub-pixel SP1, the third reflective electrode RL3 may be positioned on the second reflective electrode RL2 and the step layer STPL. In the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 may be positioned on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0158] In one or more embodiments, at least one of the first reflective electrode RL1 , the second reflective electrode RL2 , and the third reflective electrode RL3 may be omitted.

[0159] A plurality of fourth reflective electrodes RL4 may be positioned on the plurality of third reflective electrodes RL3, respectively. The fourth reflective electrode RL4 may reflect light from the first light-emitting layer IL1, the second light-emitting layer IL2, and the third light-emitting layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to appropriately reflect light. The fourth reflective electrode RL4 may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy (an alloy of silver (Ag), palladium (Pd), and copper (Cu)), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the present disclosure is not limited thereto. Each of the plurality of fourth reflective electrodes RL4 may have a thickness of approximately Thickness.

[0160] The tenth interlayer insulating layer INS10 may be positioned on the ninth interlayer insulating layer INS9 and the plurality of fourth reflective electrodes RL4. The tenth interlayer insulating layer INS10 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0161] Each of the plurality of tenth via holes VA10 may penetrate the tenth interlayer insulating layer INS10 and may be connected to the fourth reflective electrode RL4. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. Due to the presence of the step layer STPL, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 (for example, in the thickness direction DR3) may be less than the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be about And the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3 may be about 100 mm.

[0162] The light emitting element layer EML may be positioned on the light emitting element backplane EBP and may include a plurality of light emitting elements LE and a pixel defining layer PDL, each of which has a first electrode AND, a light emitting layer IL (eg, a first light emitting layer IL1, a second light emitting layer IL2 or a third light emitting layer IL3) and a second electrode CAT.

[0163] The first electrode AND of each of the plurality of light emitting elements LE may be positioned on the tenth interlayer insulating layer INS10 and may be connected to the tenth via VA10. The first electrode AND of each of the plurality of light emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the plurality of light emitting elements LE may be made of titanium nitride (TiN).

[0164] The pixel defining layer PDL may be positioned on a portion of the first electrode AND of each of the plurality of light emitting elements LE. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the plurality of light emitting elements LE. The pixel defining layer PDL may be used to divide the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0165] The first emission area EA1 may be defined as a region where the first electrode AND, the first light emitting layer IL1, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the second light emitting layer IL2, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the third light emitting layer IL3, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0166] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be positioned on an edge of the first electrode AND of each of the plurality of light emitting elements LE, the second pixel defining layer PDL2 may be positioned on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be positioned on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x ) is formed of a base inorganic layer, but the present disclosure is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of about Thickness.

[0167] The first emission area EA1 includes a first light emitting layer IL1 that emits a first light, the second emission area EA2 includes a second light emitting layer IL2 that emits a second light, and the third emission area EA3 includes a third light emitting layer IL3 that emits a third light. The first light emitting layer IL1 may be disposed on a portion of the first electrode AND that is exposed in the first emission area EA1 and not covered by the first pixel defining layer PDL1. The first light emitting layer IL1 may be disposed on the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3.

[0168] The second light emitting layer IL2 may be disposed on a portion of the first electrode AND that is exposed in the second emission area EA2 and not covered by the first pixel defining layer PDL1. The second light emitting layer IL2 may be disposed on the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3.

[0169] The third light emitting layer IL3 may be disposed on a portion of the first electrode AND that is exposed in the third emission area EA3 and not covered by the first pixel defining layer PDL1. The third light emitting layer IL3 may be disposed on the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3.

[0170] The first light emitting layer IL1 , the second light emitting layer IL2 , and the third light emitting layer IL3 may be disposed to be spaced apart from each other.

[0171] The second electrode CAT may be positioned on the first light emitting layer IL1, the second light emitting layer IL2, and the third light emitting layer IL3. The second electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or may be formed of a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of the semi-transmissive conductive material, the light emission efficiency of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be improved due to the microcavity effect.

[0172] The encapsulation layer TFE may be positioned on the light emitting element layer EML. The encapsulation layer TFE may include at least one inorganic layer to reduce or prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0173] The first encapsulation inorganic layer TFE1 may be positioned on the second electrode CAT, the encapsulation organic layer TFE2 may be positioned on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be positioned on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be formed by alternately stacking silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layer. The encapsulating organic layer TFE2 may be a monomer. Alternatively, the encapsulating organic layer TFE2 may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or the like.

[0174] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the cover layer CVL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0175] The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it may be attached to the adhesive layer ADL. In this case, the adhesive layer ADL may be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it may be used as a packaging substrate. When the cover layer CVL is a polymer resin, it may be directly applied to the adhesive layer ADL.

[0176] In one or more embodiments, the polarizing plate POL may be positioned on one surface of the cover layer CVL. The polarizing plate POL may be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizing plate POL may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the present disclosure is not limited thereto.

[0177] Fig.10 is a diagram illustrating an example of a mother substrate for manufacturing a display panel according to one or more embodiments.

[0178] Reference Fig.10 , the mother substrate 1000 may be a semiconductor wafer for OLEDoS. In the present disclosure, the semiconductor wafer may be referred to as a "semiconductor substrate", "substrate" or "semiconductor wafer substrate".

[0179] The mother substrate 1000 may include a plurality of net dies 1001. One net die 1001 may correspond to one display panel 410. For example, the mother substrate 1000 as a semiconductor wafer may include about 76 net dies 1001. This means that about 76 display panels 410 may be manufactured by one mother substrate 1000.

[0180] The plurality of display panels 410 manufactured on the mother substrate 1000 may be individually separated through a sawing process and a grinding process, and a corner of each display panel 410 is polished into a rounded shape in the grinding process after the sawing process.

[0181] The display panel 410 may include a display area DAA at which the light emitting element is positioned, and a non-display area NDA positioned outside the display area DAA.

[0182] A driving circuit 1010 may be located in the non-display area NDA of the display panel 410. The driving circuit 1010 may include a combination of Figure 5The data driver 530 described above. For example, the driving circuit 1010 may be positioned at one end of the display panel 410. Therefore, the display panel 410 may be defined to include a first corner C1 and a second corner C2 adjacent to the driving circuit 1010, and a third corner C3 and a fourth corner C4 not adjacent to the driving circuit 1010. In the example shown, the driving circuit 1010 is positioned at the bottom of the display panel 410. Therefore, in the example shown, the first corner C1 and the second corner C2 may be positioned at the bottom of the display panel 410, and the third corner C3 and the fourth corner C4 may be positioned at the top of the display panel 410.

[0183] Generally, the third corner C3 and the fourth corner C4 where the driving circuit 1010 is not located are relatively closer to the display area DAA than the first corner C1 and the second corner C2. Therefore, during the sawing process and the grinding process, the portion of the display area DAA adjacent to the third corner C3 and / or the fourth corner C4 is more likely to be damaged. In one or more embodiments of the present disclosure, an anti-seepage area MOB is located at the outermost periphery of the non-display area NDA (see Fig.13 ), and a crack prevention area CS is positioned outside the anti-seepage area MOB (see Fig.13 ), thereby reducing or preventing the possibility of damage to the display panel 410 or penetration of moisture and oxygen that may occur during the sawing process and the grinding process. For example, in one or more embodiments of the present disclosure, since the crack prevention area CS is positioned in a double-line shape at the third corner C3 and the fourth corner C4 located relatively closer to the display area DAA, it is possible to reduce or prevent damage to the display panel 410 and improve reliability.

[0184] In the following, we will combine Figures 11 to 13 The display device 10 in which the crack prevention area CS is positioned in a double line shape at the third corner C3 and the fourth corner C4 according to one or more embodiments is described in detail.

[0185] Fig.11 is an enlarged plan view of a third corner C3 of the display panel 410 according to one or more embodiments. Fig.12 is an enlarged plan view of a fourth corner C4 of the display panel 410 according to one or more embodiments.

[0186] In the following, combined Fig.11 and Fig.12 The description relates to the shapes and positions of the crack prevention area CS and the anti-seepage area MOB when viewed from the front of the display panel 410. In this case, viewing the display panel 410 from the front may mean viewing the display panel 410 in a direction perpendicular to a plane defining the front of the display panel 410.

[0187] exist Fig.11 and Fig.12 In the figure, reference numeral 1110 denotes an imaginary line at which the anti-seepage zone MOB is located.

[0188] exist Fig.11 and Fig.12 , reference numeral 1120 denotes an imaginary line at which the crack prevention area CS is located.

[0189] Reference Fig.11 and Fig.12 The anti-seepage area MOB and the crack prevention area CS positioned outside the anti-seepage area MOB may be positioned at the outermost periphery of the display panel 410. The crack prevention area CS may be substantially a region positioned at the outermost periphery of the display panel 410.

[0190] According to one or more embodiments, the anti-seepage area MOB and the crack prevention area CS may be positioned to surround the periphery of the display panel 410. At the third corner C3 and the fourth corner C4, the crack prevention area CS may be positioned in a double line shape. In this case, the fact that the crack prevention area CS is positioned in a double line shape may mean that, when viewed from the front of the display panel 410, the crack prevention area CS is positioned to be separated at corresponding intervals at the third corner C3 and the fourth corner C4.

[0191] In one or more embodiments, at the first corner C1 and the second corner C2, the crack prevention area CS may be positioned in a single line shape, and the anti-seepage area MOB may be positioned in a single line shape inside the crack prevention area CS.

[0192] According to one or more embodiments, at the third corner C3 and the fourth corner C4 , the anti-seepage area MOB is positioned inside the crack prevention area CS while surrounding the periphery of the display panel 410 in a single line shape.

[0193] According to one or more embodiments, the crack prevention area CS may be positioned in a right triangle shape at the third corner C3 and the fourth corner C4. For example, at the third corner C3 and the fourth corner C4, the crack prevention area CS may include a first portion 1121 forming a portion of a first side surface of the display panel 410, a second portion 1122 extending from the first portion 1121 in a vertical direction to form a portion of a second side surface of the display panel 410, and a third portion 1123 positioned to connect the first portion 1121 to the second portion 1122 in a diagonal direction. At the third corner C3 and the fourth corner C4, the third portion 1123 of the crack prevention area CS may substantially form a hypotenuse of the crack prevention area CS positioned in a right triangle shape.

[0194] According to one or more embodiments, at the third corner C3 and the fourth corner C4, the anti-seepage area MOB may be positioned inside the third portion 1123 of the crack prevention area CS (eg, between the first portion 1121 , the second portion 1122 , and the third portion 1123 ) to be parallel to the third portion 1123 .

[0195] According to one or more embodiments, since the crack prevention area CS is positioned in a right triangle shape at the third corner C3 and the fourth corner C4, the possibility of a defect in which the anti-seepage area MOB is removed during a grinding process of polishing the corners of the display panel 410 can be reduced or prevented.

[0196] exist Fig.11 and 12 , the dotted line 1101 represents the polishing line 1101 used for the grinding process. That is, each corner of the display panel 410 can be polished into a rounded shape along the polishing line 1101, and the outermost portion of the display panel 410 positioned outside the polishing line 1101 can be removed in the polishing process. As shown, the crack prevention area CS is positioned in a double line shape (e.g., a right triangle shape) at the third corner C3 and the fourth corner C4, so that a portion of the crack prevention area CS positioned outside the polishing line 1101 can be removed, but the anti-seepage area MOB may not be removed. That is, since the anti-seepage area MOB is not only positioned inside the polishing line 1101, but also positioned inside the third portion 1123 of the crack prevention area CS, even after the grinding process, the anti-seepage area MOB may not be removed or damaged at the third corner C3 and the fourth corner C4. In one or more embodiments of the present disclosure, it is possible to protect the display panel 410 from cracks that may occur during the sawing process and the grinding process, and reduce or prevent moisture and oxygen from penetrating into the display panel 410 .

[0197] Meanwhile, as shown, a dummy structure DM may be positioned inside the crack prevention area CS positioned in a right triangle shape at the third corner C3 and the fourth corner C4. In one or more embodiments, the dummy structure DM may include a plurality of metal layers ML1 to ML8 (see FIG. 1 ) connected to the display panel 410. Fig. 9 ) is positioned on the same layer as the dummy metal layer.

[0198] Fig.13 4 is a partial cross-sectional view of a display panel 410 , illustrating a stacked structure of a crack prevention region CS and an anti-seepage region MOB according to one or more embodiments.

[0199] Fig.13 The anti-crack area CS and the anti-seepage area MOB shown in the figure can be Fig.11 and Fig.12 A portion of the crack prevention zone CS and the anti-seepage zone MOB is shown in FIG. Fig.13 The first sub-pixel SP1 shown in FIG. Fig. 9 The first sub-pixel SP1 shown in FIG. 1 is substantially the same.

[0200] Reference Fig.13 The display panel 410 may include a semiconductor backplane SBP including a semiconductor substrate SSUB, a semiconductor backplane SBP including a plurality of metal layers ML1 to ML8 (see Fig. 9 ) and a light emitting element backplane EBP and a light emitting element layer EML positioned on the light emitting element backplane EBP.

[0201] According to one or more embodiments, the stacked structure of the barrier region MOB may include a plurality of metal layers ML1 to ML8 (see Fig. 9 ) are located in the same layer as the plurality of impermeable metal layers 1320. For example, the plurality of impermeable metal layers 1320 may be located in the display area DAA with the plurality of metal layers ML1 to ML8 (see Fig. 9 ) are positioned in the same layer and in the barrier area MOB. A plurality of barrier metal layers 1320 may be positioned to surround the periphery of the display panel 410.

[0202] According to one or more embodiments, the stack structure of the crack prevention area CS may include a plurality of metal layers ML1 to ML8 (see Fig. 9 ) are located at the same layer of a plurality of crack prevention metal layers 1310. For example, the plurality of crack prevention metal layers 1310 may be located at the same layer as the plurality of metal layers ML1 to ML8 (see Fig. 9 ) are positioned in the same layer and in the crack prevention area CS. The plurality of crack prevention metal layers 1310 may be positioned to surround the outermost periphery of the display panel 410. For example, since the plurality of crack prevention metal layers 1310 are positioned in a double line shape at the third corner C3 and the fourth corner C4 of the display panel 410, the possibility of removing the anti-seepage area MOB during the grinding process can be reduced or prevented.

[0203] Fig.13 Reference numeral 1301 may correspond to a pad metal layer 1301 positioned on a plurality of barrier metal layers 1320 in the barrier region MOB. In one or more embodiments, the pad metal layer 1301 may be a metal layer positioned at the same layer as a pad electrode of the display panel 410.

[0204] According to the display device and the mobile electronic device including the display device according to the embodiments, the display panel may be protected from cracks that may occur during sawing and grinding processes, and the possibility of moisture and oxygen penetrating into the display panel may be reduced or prevented.

[0205] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the preferred embodiment without departing substantially from the aspects of the present disclosure. Therefore, the disclosed embodiments are used only in a generic and descriptive sense and not for purposes of limitation.

Claims

1. A display device, comprising: A display panel, the display panel having a display area and a non-display area, wherein a light-emitting element is positioned in the display area, the non-display area is located outside the display area in a plan view and includes an anti-seepage area and an anti-crack area, the anti-seepage area is located outside the packaging area, the anti-crack area is located outside the anti-seepage area and is in a double-line shape at at least one corner of the display panel.

2. The display device according to claim 1, further comprising: a driving circuit, wherein the driving circuit is located at one end of the display panel, The display panel is defined as comprising a first corner and a second corner adjacent to the drive circuit, and a third corner and a fourth corner not adjacent to the drive circuit, and Wherein, the anti-crack area is in the double-line shape at the third corner and the fourth corner of the display panel.

3. The display device according to claim 2, wherein: The crack prevention area is in a single line shape at the first corner and the second corner of the display panel.

4. The display device according to claim 2, wherein: The crack prevention area is in a right triangle shape at the third corner or the fourth corner of the display panel.

5. The display device according to claim 4, wherein: At the third corner or the fourth corner of the display panel, the anti-crack zone includes a first portion forming a portion of a first side surface of the display panel, a second portion extending from the first portion in a vertical direction to form a portion of a second side surface of the display panel, and a third portion connecting the first portion to the second portion in a diagonal direction.

6. The display device according to claim 5, wherein: At the third corner or the fourth corner of the display panel, the anti-seepage area is located inside the third portion of the crack prevention area to be parallel to the third portion.

7. The display device according to claim 4, wherein: At the third corner or the fourth corner of the display panel, a dummy structure is located in the crack prevention area in the shape of the right triangle.

8. The display device according to claim 7, wherein: The display panel includes a semiconductor backplane including a semiconductor substrate, a light emitting element backplane having a plurality of metal layers, and a light emitting element layer located above the light emitting element backplane.

9. The display device according to claim 8, wherein: The stacked structure of the barrier region includes a plurality of barrier metal layers on the same layer as the plurality of metal layers of the light emitting element backplane.

10. The display device according to claim 8, wherein: The stacked structure of the crack prevention area includes a plurality of crack prevention metal layers on the same layer as the plurality of metal layers of the light emitting element back panel.

11. A mobile electronic device, comprising: A display device, the display device includes a display panel, the display panel includes a display area and a non-display area, a light-emitting element is positioned in the display area, the non-display area is located outside the display area and includes an anti-seepage area and an anti-crack area, the anti-seepage area is located outside the packaging area, and the anti-crack area is located outside the anti-seepage area in a double-line shape at at least one corner of the display panel.

12. The mobile electronic device according to claim 11, further comprising: a driving circuit, wherein the driving circuit is located at one end of the display panel, The display panel includes a first corner and a second corner adjacent to the drive circuit, and a third corner and a fourth corner not adjacent to the drive circuit, and Wherein, the anti-crack area is in the double-line shape at the third corner and the fourth corner of the display panel.

13. The mobile electronic device according to claim 12, wherein: The crack prevention area is in a single line shape at the first corner and the second corner of the display panel.

14. The mobile electronic device according to claim 12, wherein: The crack prevention area is in a right triangle shape at the third corner or the fourth corner of the display panel.

15. The mobile electronic device according to claim 14, wherein: At the third corner or the fourth corner of the display panel, the anti-crack zone includes a first portion forming a portion of a first side surface of the display panel, a second portion extending from the first portion in a vertical direction to form a portion of a second side surface of the display panel, and a third portion connecting the first portion to the second portion in a diagonal direction.

16. The mobile electronic device according to claim 15, wherein: At the third corner or the fourth corner of the display panel, the anti-seepage area is located inside the third portion of the crack prevention area to be parallel to the third portion.

17. The mobile electronic device according to claim 14, wherein: At the third corner or the fourth corner of the display panel, a dummy structure is located in the crack prevention area in the shape of the right triangle.

18. The mobile electronic device according to claim 17, wherein: The display panel includes a semiconductor backplane including a semiconductor substrate, a light emitting element backplane having a plurality of metal layers, and a light emitting element layer located above the light emitting element backplane.

19. The mobile electronic device according to claim 18, wherein: The stacked structure of the barrier region includes a plurality of barrier metal layers on the same layer as the plurality of metal layers of the light emitting element backplane.

20. The mobile electronic device according to claim 18, wherein: The stacked structure of the crack prevention area includes a plurality of crack prevention metal layers on the same layer as the plurality of metal layers of the light emitting element back panel.

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