Electro-optical device and electronic apparatus

Abstract

An electro-optical device and an electronic apparatus are provided. The present invention suppresses a reduction in display quality caused by charge remaining on a drain node of a transistor that drives an OLED, and achieves low power consumption. A pixel circuit provided corresponding to a scan line and a data line has a transistor (121) and an OLED (130), the transistor (121) supplies a current corresponding to a voltage between a gate node and a source node to the OLED (130) during a light emission period (E), the data line (14) is set to a potential Vini during an initialization period (A), the gate node of the transistor (121) is set to a threshold-equivalent potential during a compensation period (B), and the gate node of the transistor (121) is set to a threshold-equivalent potential during a compensation period (E). During the write period (C), the gate node of the transistor (121) is set from a threshold-equivalent potential to a potential corresponding to the brightness of the OLED (130), and during the drain set period (D), the drain node of the transistor (121) is set to a potential not less than the potential Vini but less than the potential VBk.

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device. Background Art

[0002] In recent years, various electro-optical devices using light-emitting elements such as organic light emitting diodes (OLEDs) have been proposed. In the electro-optical device, a pixel circuit is provided corresponding to the intersection of a scanning line and a data line and corresponding to the pixel of an image to be displayed, and the pixel circuit includes the light-emitting element, a transistor for supplying current to drive the light-emitting element, and the like.

[0003] When the electro-optical device is miniaturized, parasitic capacitance is generated in various parts of the electro-optical device. If parasitic capacitance is generated at the drain node of the transistor driving the light-emitting element, the charge remaining in the parasitic capacitance flows to the light-emitting element, resulting in a decrease in display quality. Therefore, the following technology is proposed: before supplying current to the light-emitting element to cause it to emit light, a reset potential is supplied to the drain node of the transistor via a data line (for example, refer to Patent Document 1).

[0004] Patent Document 1: Japanese Patent Application Publication No. 2023-50791

[0005] However, when a reset potential is supplied to the drain node of a transistor via a data line as in the technique described in Patent Document 1, the potential amplitude of the data line increases, and power consumption cannot be reduced due to charge and discharge of a capacitance parasitic on the data line. Summary of the invention

[0006] Therefore, an object of the present invention is to provide a technology that suppresses degradation of display quality due to charges remaining at a drain node of a transistor that drives a light-emitting element and achieves low power consumption.

[0007] In order to solve the above-mentioned problems, an electro-optical device involved in one embodiment of the present invention includes a pixel circuit arranged corresponding to a scanning line and a data line, the pixel circuit having a first transistor and a light-emitting element, the first transistor supplies a current corresponding to the voltage between a gate node of the first transistor and a source node of the first transistor to the light-emitting element during a light-emitting period, and, during an initialization period before the light-emitting period, the data line is set to a first potential, during a compensation period after the initialization period and before the light-emitting period, the gate node of the first transistor is set to a second potential corresponding to the threshold voltage of the first transistor, during a first period after the compensation period and before the light-emitting period, the gate node of the first transistor is set from the second potential to a third potential corresponding to the brightness of the light-emitting element, and during a second period after the first period and before the light-emitting period, the drain node of the first transistor is set to a fourth potential that is greater than the first potential and less than the third potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a perspective view of the electro-optical device according to the first embodiment.

[0009] Figure 2 This is a block diagram showing the electrical structure of the electro-optical device according to the first embodiment.

[0010] Figure 3 This is a diagram showing a pixel circuit of the electro-optical device according to the first embodiment.

[0011] Figure 4 This is a timing chart showing the operation of the electro-optical device according to the first embodiment.

[0012] Figure 5 It is a diagram showing the operation of the electro-optical device according to the first embodiment.

[0013] Figure 6 It is a diagram showing the operation of the electro-optical device according to the first embodiment.

[0014] Figure 7 It is a diagram showing the operation of the electro-optical device according to the first embodiment.

[0015] Figure 8 It is a diagram showing the operation of the electro-optical device according to the first embodiment.

[0016] Fig. 9 It is a diagram showing the operation of the electro-optical device according to the first embodiment.

[0017] Fig.10 It is a diagram showing the potential range during the writing period in the first embodiment.

[0018] Fig.111 is a diagram showing potential changes in various parts of the electro-optical device according to the first embodiment.

[0019] Fig.12 It is a block diagram showing the electrical structure of the electro-optical device according to the second embodiment.

[0020] Fig.13 It is a timing chart showing the operation of the electro-optical device according to the second embodiment.

[0021] Fig.14 It is a block diagram showing the electrical structure of an electro-optical device according to the third embodiment.

[0022] Fig.15 It is a diagram showing a pixel circuit of an electro-optical device according to a fourth embodiment.

[0023] Fig.16 It is a timing chart showing the operation of the electro-optical device according to the fourth embodiment.

[0024] Fig.17 It is a diagram showing a pixel circuit of an electro-optical device according to a fifth embodiment.

[0025] Fig.18 It is a diagram showing a pixel circuit of an electro-optical device according to a sixth embodiment.

[0026] Fig.19 It is a timing chart showing the operation of the electro-optical devices according to the fifth embodiment and the sixth embodiment.

[0027] Fig. 20 It is a timing chart showing the operation of the electro-optical device according to the modification.

[0028] Fig.21 This is a perspective view showing a head mounted display using an electro-optical device.

[0029] Fig. 22 2 is a diagram showing the optical structure of a head mounted display.

[0030] Fig.23 It is a timing chart showing the operation of the electro-optical device of the comparative example.

[0031] Fig.24 It is a diagram showing the operation of the electro-optical device of the comparative example.

[0032] Description of symbols

[0033] 10: electro-optical device; 12: scanning line; 14: data line; 14c: data signal output line; 30: control circuit; 50: data signal output circuit: 60: auxiliary circuit; 62: transistor; 70: capacitor element; 72, 150: parasitic capacitance; 80: initialization circuit; 82, 84, 85, 86, 87: transistor; 110: pixel circuit; 120: scanning line driving circuit; 121~124, 126: transistor; 130: OLED; 161, 162: capacitor element; 170: discharge control line. DETAILED DESCRIPTION

[0034] Hereinafter, the electro-optical device of the embodiment will be described with reference to the accompanying drawings. In addition, in each figure, the size and scale of each part are appropriately different from the actual size and scale. In addition, the embodiment described below is a preferred specific example, and therefore various technically preferred limitations are added, but as long as there is no record of the subject matter of the present disclosure being particularly limited in the following description, the scope of the present disclosure is not limited to these modes.

[0035] First embodiment

[0036] Figure 1 1 is a perspective view showing an electro-optical device 10 according to a first embodiment. The electro-optical device 10 is, for example, a micro display panel for displaying images in a head-mounted display or the like. The electro-optical device 10 includes a pixel circuit including an OLED, a drive circuit for driving the pixel circuit, and the like. The pixel circuit, the drive circuit, and the like are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may also be other semiconductor substrates.

[0037] The electro-optical device 10 is housed in a frame-shaped housing 192 opened in the display area 100. The electro-optical device 10 is connected to one end of an FPC substrate 194. In addition, FPC is an abbreviation for Flexible Printed Circuits. A plurality of terminals 196 connected to a host device (not shown) are provided at the other end of the FPC substrate 194. When the plurality of terminals 196 are connected to the host device, image data, synchronization signals, etc. are supplied from the host device to the electro-optical device 10 via the FPC substrate 194.

[0038] In the figure, the X direction indicates the extending direction of the scanning line in the electro-optical device 10, and the Y direction indicates the extending direction of the data line. The two-dimensional plane defined by the X direction and the Y direction is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X direction and the Y direction and is the emitting direction of the light emitted from the OLED.

[0039] Figure 21 is a block diagram showing the electrical structure of the electro-optical device of the first embodiment. As shown in the figure, the electro-optical device 10 includes a control circuit 30, a data signal output circuit 50, an auxiliary circuit 60, n capacitor elements 70, an initialization circuit 80, a display area 100 and a scanning line driving circuit 120.

[0040] In the display area 100, m rows of scanning lines 12 are arranged along the X direction in the figure, and n columns of data lines 14 are arranged along the Y direction and electrically insulated from the scanning lines 12. Note that m and n are integers of 2 or more.

[0041] In the display area 100, the pixel circuits 110 are arranged corresponding to the intersections of the scan lines 12 of the m rows and the data lines 14 of the n columns. Therefore, the pixel circuits 110 are arranged in a matrix with m rows and n columns. In order to distinguish the rows in the matrix arrangement, sometimes the 1st, 2nd, 3rd, ..., (m-1), and mth rows are referred to from the top in the figure. Similarly, in order to distinguish the columns of the matrix, sometimes the 1st, 2nd, 3rd, ..., (n-1), and nth columns are referred to from the left in the figure.

[0042] In order to generally describe the scanning line 12, an integer i of 1 to m is used. In order to generally describe the data line 14, an integer j of 1 to n is used.

[0043] The control circuit 30 controls each unit based on the video data Vid and the synchronization signal Sync supplied from the upper host device. The video data Vid specifies the grayscale level of a pixel in an image to be displayed using, for example, 8 bits.

[0044] The synchronization signal Sync includes a vertical synchronization signal for instructing the start of vertical scanning of the video data Vid, a horizontal synchronization signal for instructing the start of horizontal scanning, and a dot clock signal indicating the timing of one pixel of the video data.

[0045] In the embodiment, pixels of an image to be displayed correspond one-to-one to the pixel circuits 110 in the display area 100 .

[0046] The characteristics of brightness expressed by grayscale in the image data Vid supplied from the host device are not necessarily consistent with the characteristics of brightness of the OLED included in the pixel circuit 110. Therefore, in order to make the OLED emit light at a brightness corresponding to the grayscale specified by the image data Vid, the control circuit 30 upconverts 8 bits of the image data Vid into 10 bits in the embodiment, for example, and outputs it as the image data Vdata. Therefore, the grayscale is also specified for the 10-bit image data Vdata. That is, the image data Vdata specifies the grayscale obtained by converting the grayscale specified by the image data Vid.

[0047] In the up-conversion, for example, a lookup table storing in advance the correspondence between 8 bits of input video data Vid and 10 bits of output video data Vdata is used. The control circuit 30 generates various control signals to control each unit, which will be described in detail later.

[0048] The scan line drive circuit 120 is a circuit for outputting various signals and driving the pixel circuits 110 arranged in m rows and n columns for each row according to the control of the control circuit 30. For example, the scan line drive circuit 120 supplies scan signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) to the scan lines 12 of the 1st, 2nd, 3rd, ..., (m-1), and mth rows in sequence. Generally speaking, the scan line drive circuit 120 supplies a scan signal / Gwr(i) to the scan line 12 of the i-th row. In addition to the scan signals / Gwr(1) to / Gwr(m), the scan line drive circuit 120 also outputs various control signals, which will be described in detail later.

[0049] The data signal output circuit 50 is a circuit that outputs a voltage signal corresponding to brightness to the pixel circuit 110 located in the row selected by the scan line driving circuit 120. Specifically, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 500.

[0050] The selection circuit group 52 includes selection circuits 520 corresponding to n columns one by one, the first latch circuit group 54 includes first latch circuits L1 corresponding to n columns one by one, and the second latch circuit group 56 includes second latch circuits L2 corresponding to n columns one by one. In addition, the n DA conversion circuits 500 correspond to n columns one by one.

[0051] That is, a group of a selection circuit 520, a first latch circuit L1, a second latch circuit L2, and a DA conversion circuit 500 is provided corresponding to each column. Here, the selection circuit 520 of the j-th column instructs the first latch circuit L1 of the j-th column to select the image data of the j-th column among the image data Vdata output from the control circuit 30, and the first latch circuit L1 of the j-th column latches the image data Vdata according to the instruction. The second latch circuit L2 of the j-th column outputs the image data Vdata latched by the first latch circuit L1 of the j-th column to the DA conversion circuit 500 of the j-th column in accordance with the control of the control circuit 30 during the write period (C) described later.

[0052] The DA conversion circuit 500 of the jth column converts the 10-bit image data Vdata output from the second latch circuit L2 of the jth column into an analog signal, and outputs it to the data signal output line 14c of the jth column. In other words, the data signal output line 14c is provided in a one-to-one correspondence with the data line 14, and the output end of the DA conversion circuit 500 of the jth column is connected to the data signal output line 14c of the jth column.

[0053] The auxiliary circuit 60 is a collection of transistors 62 provided in one-to-one correspondence with the data signal output line 14c. The source node of the transistor 62 corresponding to the j-th column is connected to the power supply line of the potential Vref, and the drain node of the transistor 62 is connected to the data signal output line 14c of the j-th column. In addition, the control signal / Gref output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 62 in each column.

[0054] The n capacitor elements 70 are provided in a one-to-one correspondence with the data signal output line 14c and the data line 14. Specifically, one end of the capacitor element 70 in the j-th column is connected to the data signal output line 14c in the j-th column, and the other end of the capacitor element 70 in the j-th column is connected to the data line 14 in the j-th column. In addition, the image data Vdata corresponds to the grayscale level specified by the image data Vid, and the DA conversion circuit 500 converts the image data Vdata into an analog signal, which is supplied to the data line 14 as a data signal via the capacitor element 70. Therefore, the potential of the data signal supplied to the data line 14 corresponds to the grayscale level specified by the image data Vid and the image data Vdata.

[0055] The initialization circuit 80 is a collection of groups of transistors 82 , 84 , and 86 provided in a one-to-one correspondence with the data lines 14 .

[0056] The source node of the transistor 82 corresponding to the j-th column is connected to the power supply line of the potential Vel, and the drain node of the transistor 82 is connected to the data line 14 of the j-th column. In addition, the control signal / Drst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 82 in each column. The potential Vel is used as a high potential of the power supply voltage.

[0057] The source node of the transistor 84 corresponding to the jth column is connected to the supply line of the potential Vini, and the drain node of the transistor 84 is connected to the data line 14 of the jth column. The control signal / Gini outputted from the control circuit 30 is commonly supplied to the gate nodes of the transistors 84 in each column.

[0058] The source node of the transistor 86 corresponding to the j-th column is connected to the power supply line of the potential Vorst, and the drain node of the transistor 86 is connected to the data line 14 of the j-th column. In addition, the control signal / Grst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 86 in each column. In addition, the potential Vorst is, for example, the potential Gnd or a lower potential close to the potential Gnd. Specifically, the potential Vorst is a potential at which current does not flow through the OLED when the anode of the OLED is powered. In addition, the potential Gnd is a ground potential and a reference potential of zero voltage.

[0059] In addition, in this embodiment, the control signals / Drst and / Grst are always at the H level, so the transistors 82 and 86 of each column are always in the off state. Therefore, in this embodiment, the transistors 82 and 86 have no electrical meaning. However, they are retained for comparison with the comparative example described later.

[0060] Each column of data line 14 has a parasitic capacitance component. In the figure, this capacitance component is marked as parasitic capacitance 72. From an electrical point of view, this parasitic capacitance 72 is represented as a capacitance element having one end connected to data line 14 and the other end connected to a constant potential power supply line such as potential Gnd.

[0061] In the figure, the potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are marked as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n) respectively. Generally, the potential of the data line 14 in the jth column is marked as Vd(j).

[0062] Figure 3 is a circuit diagram showing the pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to each other. Therefore, the pixel circuit 110 will be described using the pixel circuit 110 located in the i row and j column as a representative.

[0063] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-type transistors 121 to 124, and a capacitor 140. The transistors 121 to 124 are, for example, MOS type. MOS is the abbreviation of Metal-Oxide-Semiconductor field-effect transistor.

[0064] In addition to the scanning signal / Gwr(i) corresponding to the i-th row, the scanning line driving circuit 120 supplies control signals / Gel(i) and / Gcmp(i) to the pixel circuits 110 in the i-th row.

[0065] The control signal / Gel(i) is a signal obtained by generalizing the control signals / Gel(1), / Gel(2), ..., / Gel(m-1), and / Gel(m) which are sequentially supplied corresponding to the 1st, 2nd, ..., (m-1), and mth rows. Similarly, the control signal / Gcmp(i) is a signal obtained by generalizing the control signals / Gcmp(1), / Gcmp(2), ..., / Gcmp(m-1), and / Gcmp(m) which are sequentially supplied corresponding to the 1st, 2nd, ..., (m-1), and mth rows.

[0066] The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 has light-transmitting properties.

[0067] In the OLED 130 , when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby generating white light.

[0068] In the case of color display, the generated white light resonates in an optical resonator composed of a reflective layer and a semi-reflective and semi-transmissive layer, which are omitted from the illustration, and is emitted at a resonant wavelength set corresponding to any color of R (red), G (green), and B (blue). A color filter corresponding to the color is set on the emission side of the light emitted from the optical resonator. Therefore, the emitted light from the OLED 130 is sequentially colored by the optical resonator and the color filter and is visually recognized by the observer. In addition, the illustration of the optical resonator is omitted. In addition, in the case where the electro-optical device 10 only displays a monochrome image of light and dark, the above-mentioned optical resonator and color filter are omitted.

[0069] In the transistor 121 of the pixel circuit 110 in the i row and j column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116 supplied with the potential Vel, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124.

[0070] A parasitic capacitance component is present at the drain node d of the transistor 121. In the figure, this capacitance component is indicated as a parasitic capacitance 150. From an electrical point of view, this parasitic capacitance 150 is represented as a capacitance element having one end connected to the drain node d and the other end connected to a supply line of a constant potential, such as the potential Gnd.

[0071] In the capacitor 140, one end is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitor 140 holds the voltage between the gate node g and the source node s of the transistor 121.

[0072] In addition, the other end of the capacitor element 140 only needs to maintain a substantially constant potential, and therefore may be connected to a power supply line having a potential other than the power supply line 116 having the potential Vel.

[0073] In the embodiment, a so-called MOS capacitor formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer (lower electrode) of the transistor and a gate electrode layer (upper electrode) is used as the capacitor 140. In addition, as the capacitor 140, a parasitic capacitor of a gate node g of the transistor 121 or a so-called metal capacitor formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate can be used.

[0074] In the transistor 122 of the pixel circuit 110 in the i row and j column, the gate node is connected to the scan line 12 of the i row, and the source node is connected to the data line 14 of the j column. In the transistor 123 of the pixel circuit 110 in the i row and j column, the control signal / Gcmp(i) is supplied to the gate node, and the drain node is connected to the data line 14 of the j column. In the transistor 124 of the pixel circuit 110 in the i row and j column, the control signal / Gel(i) is supplied to the gate node, and the drain node is connected to the pixel electrode 131 which is the anode of the OLED 130.

[0075] In the transistors 122 , 123 , and 124 , when the direction of current flow is reversed, the source node and the drain node are switched, but in this description, the source node and the drain node are assumed to be as described above.

[0076] A potential Vct is supplied to the common electrode 133 functioning as a cathode of the OLED 130. The potential Vct is, for example, the potential Gnd or a lower potential close to the potential Gnd. In such a pixel circuit 110, a series connection of transistors 123 and 124 is provided in a path from the data line 14 to the pixel electrode 131, and a transistor 124 is provided between the drain node d of the transistor 121 and the pixel electrode 131.

[0077] In this description, "electrical connection" or simply "connection" refers to direct or indirect connection or connection between two or more elements, and also includes the situation where, for example, two or more elements in a semiconductor substrate are not directly connected but are connected through different wiring layers and contact holes.

[0078] In addition, although the pixel circuit 110 in the i-th row and the j-th column is described here, the pixel circuits 110 in other rows and other columns have the same structure.

[0079] The control circuit 30 controls the driving of the pixel circuit 110 via the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scan line driving circuit 120. Therefore, sometimes the control circuit 30, the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scan line driving circuit 120 are included and referred to as a broad control circuit that controls the pixel circuit 110.

[0080] Next, the operation of the electro-optical device 10 will be described.

[0081] Figure 4 1 is a timing chart for explaining the operation of the electro-optical device 10 according to the first embodiment. Figure 4 1 is a timing chart showing the operation of one frame in the electro-optical device 10 and the operation of two consecutive horizontal scanning periods in the one frame.

[0082] In this description, it is referred to as 1 frame. 1 frame refers to the period required to display 1 frame of the image specified by the video data Vid. When the time length of 1 frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds corresponding to 1 cycle of the vertical synchronization signal.

[0083] In the electro-optical device 10, in each frame (V), m rows of scanning lines 12 are selected row by row in the order of the 1st, 2nd, 3rd, ..., mth row and horizontally scanned. The period required for horizontal scanning of one row is the horizontal scanning period (H).

[0084] In this embodiment, the horizontal scanning period (H) is divided into an initialization period (A), a compensation period (B), a writing period (C), and a drain setting period (D) in chronological order. In addition, as an operation of the pixel circuit 110, in addition to the initialization period (A), the compensation period (B), the writing period (C), and the drain setting period (D), a light emitting period (E) is added.

[0085] The initialization period (A) is a period for supplying the potential Vini for turning on the transistor 121 to the gate node g via the data line 14 .

[0086] The compensation period (B) is a period for causing the gate node g of the transistor 121 to converge to a potential corresponding to the threshold voltage of the transistor 121 .

[0087] The write period (C) is a period during which the gate node g of the transistor 121 maintains (writes) a potential corresponding to the grayscale level. Specifically, it is a period during which the gate node g of the transistor 121 changes from a potential corresponding to the threshold voltage to a voltage amount corresponding to the current flowing to the OLED 130.

[0088] The drain set period (D) is a period during which the potential Vini is set at the drain node d of the transistor 121. The potential Vini set at the drain node d is held by the parasitic capacitor 150.

[0089] The light emission period (E) is a period for causing a current corresponding to the potential of the gate node g held in the writing period (C) to flow through the OLED 130 to cause it to emit light.

[0090] In this description, the "on state" of a transistor means that the source node and the drain node in the transistor are electrically closed to form a low impedance state. In addition, the "off state" of a transistor means that the source node and the drain node are electrically opened to form a high impedance state.

[0091] In this embodiment, the operation of each frame is the same. In addition, in one frame (V), the operation of each row during the horizontal scanning period (H) is the same. Furthermore, the operation of the pixel circuits 110 of the first to nth columns of one row scanned during one horizontal scanning period (H) is the same.

[0092] Therefore, the following description will be made by taking the operation of the pixel circuit 110 in the i-th row and the j-th column as an example regarding the horizontal scanning period (H) of the i-th row in each frame.

[0093] In one frame (V), during the initialization period (A) of each horizontal scanning period (H), the control signal / Gini is at L level and the control signal / Gref is at L level. Therefore, the transistors 84 and 62 of each column are turned on.

[0094] In addition, during the initialization period (A) of the horizontal scanning period (H) of the i-th row, the scanning signal / Gwr(i) is at the L level, the control signal / Gcmp(i) is at the H level, and the control signal / Gel(i) is at the H level. Therefore, during this initialization period (A), in the pixel circuit 110 of the i-th row and the j-th column, the transistor 122 is in the on state, the transistor 123 is in the off state, and the transistor 124 is in the off state.

[0095] Therefore, during initialization (A), if Figure 5 As shown, in the pixel circuit 110 of the i-th row and the j-th column, the potential Vini is supplied to one end of the capacitor 140 and the gate node g of the transistor 121 via the transistor 84 , the data line 14 of the j-th column, and the transistor 122 in sequence.

[0096] In this initialization period (A), since the transistor 62 is turned on in each column, the data signal output line 14c, that is, one end of the capacitor 70, becomes the potential Vref.

[0097] As described above, in the initialization period (A), the data line 14 of the j-th column, that is, the other end of the capacitor 70 is at the potential Vini.

[0098] Therefore, in each column, the voltage across the capacitor 70 becomes |Vref-Vini|, and one end of the parasitic capacitor 72 is maintained at the potential Vini.

[0099] In addition, the potentials Vini and Vorst are

[0100] Vini>Vorst

[0101] relationship.

[0102] During the compensation period (B) of each horizontal scanning period (H), the control signal / Gini changes to the H level and the control signal / Gref maintains the L level. Therefore, the transistor 84 of each column changes to the OFF state and the transistor 62 of each column maintains the ON state.

[0103] During the compensation period (B) of the horizontal scanning period (H) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the L level, and the control signal / Gel(i) maintains the H level. Therefore, in the pixel circuit 110 of the i-th row and the j-th column, the transistor 122 maintains the on state, the transistor 123 changes to the on state, and the transistor 124 maintains the off state.

[0104] At the beginning of the compensation period (B), in the pixel circuit 110 of the i-th row, the gate node g of the transistor 121 reaches the potential Vini. When the gate node g reaches the potential Vini, if the transistor 123 is turned on, the transistor 121 is in a diode connection state, that is, the gate node g is connected to the drain node d.

[0105] Therefore, during the compensation period (B), if Figure 6 As shown, the voltage between the gate node g and the source node s of the transistor 121 is close to the threshold voltage Vth (voltage close to the threshold voltage Vth) of the transistor 121. That is, the potentials of the gate node g, the drain node d and the data line 14 of the transistor 121 are close to the threshold equivalent potential (Vel-Vth).

[0106] During the compensation period (B), the transistor 62 in each column is kept on, so that one end of the capacitor 70 maintains the potential Vref. During the compensation period (B), the data line 14 as the other end of the capacitor 70 approaches the threshold equivalent potential (Vel-Vth).

[0107] Therefore, in each column, the voltage across the capacitor 70 becomes |Vel-Vth-Vref|, and one end of the parasitic capacitor 72 is maintained at a threshold-equivalent potential (Vel-Vth).

[0108] In the writing period (C) of each horizontal scanning period (H), the control signal / Gini maintains the H level and the control signal / Gref changes to the H level. Therefore, the transistor 84 of each column maintains the OFF state and the transistor 62 of each column changes to the OFF state.

[0109] During the writing period (C) of the horizontal scanning period (H) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the H level, and the control signal / Gel(i) maintains the H level. Therefore, in the pixel circuit 110 of the i-th row and the j-th column, the transistor 122 maintains the on state, the transistor 123 changes to the off state, and the transistor 124 maintains the off state.

[0110] During this writing period (C), the transistor 62 of each column changes to an off state. In addition, the 10-bit image data Vdata of the i-th row and corresponding to the column is supplied to the DA conversion circuit 500 of each column. Therefore, the DA conversion circuit 500 of the j-th column outputs a signal of a potential corresponding to the grayscale level of the i-th row and the j-th column to the data signal output line 14c.

[0111] Therefore, during this writing period (C), if Figure 7 As shown, one end of the j-th capacitor 70 rises from the potential Vref to the potential of the grayscale corresponding to the i-th row and the j-th column. This potential rise reaches the gate node g of the transistor 121 via the capacitor 70, the data line 14, and the transistor 122 in sequence.

[0112] The potential change amount of the gate node g during the write period (C) is the value obtained by multiplying the potential rise amount of the data signal output line 14c, i.e., one end of the capacitor 70, by the ratio of the capacitance value of the capacitor 70 to the "composite capacitance value". The "composite capacitance value" mentioned here refers to the capacitance value of the composite capacitance of the capacitor 70, the parasitic capacitance 72, and the capacitor 140. In addition, the capacitance value of the capacitor 140 can be ignored when it is sufficiently small compared with other capacitance values.

[0113] Reference Fig.10 Next, the potential changes of the data signal output line 14c and the data line 14 during the writing period (C) will be described.

[0114] The potential corresponding to the grayscale outputted to the data signal output line 14c by the DA conversion circuit 500 is in the range from the potential Bk corresponding to the black level of the lowest grayscale to the potential Wt corresponding to the white level of the highest grayscale. The potential in this range is compressed into a range from the potential Vbk (≈Vel) to the potential Vwt slightly lower than the potential Vbk by the charge distribution of the capacitor element 70 and the parasitic capacitor 72, and reaches the data line 14 and the gate node g.

[0115] When the scanning signal / Gwr(i) becomes H level, the writing period (C) ends. In the pixel circuit 110 of the i row and j column, the transistor 122 is turned off, but the voltage difference between the potential of the gate node g and the potential Vel of the source node s is held in the capacitor 140 .

[0116] In this embodiment, after the writing period (C) is completed, it becomes the drain setting period (D). During the drain setting period (D) of each horizontal scanning period (H), the control signal / Gini changes to the L level, and the control signal / Gref maintains the H level. Therefore, the transistor 84 of each column changes to the on state, and the transistor 62 of each column maintains the off state.

[0117] During the drain set period (D) of the horizontal scanning period (H) of the i-th row, the scanning signal / Gwr(i) changes to the H level, the control signal / Gcmp(i) changes to the L level, and the control signal / Gel(i) maintains the H level. Therefore, in the pixel circuit 110 of the i-th row and the j-th column, the transistor 122 changes to the off state, the transistor 123 changes to the on state, and the transistor 124 maintains the off state.

[0118] Therefore, during the drain set period (D), if Figure 8 As shown, in the pixel circuit 110 of the i-th row and the j-th column, the potential Vini is supplied to the drain node d of the transistor 121 via the transistor 84 , the data line 14 of the j-th column, and the transistor 123 in sequence.

[0119] Therefore, during the drain set period (D), the drain node d, that is, one end of the parasitic capacitor 150, is set to the potential Vini. As described above, the potential Vini is a potential that turns on the transistor 121 when supplied to the gate node g, and is lower than the potential Vel and higher than the potential Vorst.

[0120] In this embodiment, after the drain setting period (D) ends, the light emitting period (E) begins.

[0121] During the light emission period (E) of the i-th row, the control signal / Gel(i) is inverted to the L level, and thus the transistor 124 is turned on.

[0122] Therefore, during the light emission period (E), if Fig. 9 As shown, a current Iel corresponding to the potential of the gate node g held by the capacitor 140 flows to the OLED 130 in the pixel circuit 110 of the i row and j column through the transistor 121. Therefore, the OLED 130 emits light with a brightness corresponding to the current Iel.

[0123] Fig.23 This is a timing chart for explaining the operation of a comparative example for explaining the superiority of the electro-optical device 10 according to the first embodiment.

[0124] The structure of the electro-optical device of the comparative example is Figure 2 and Figure 3 The structure shown in FIG. 1 is the same as that shown in FIG. 1 , but the control signals supplied from the control circuit 30 and the scanning line driving circuit 120 are different from those in the first embodiment. Fig.23 The waveform shown.

[0125] In the comparative example, the initialization period (A) is divided into three initialization periods (A1), (A2) and (A3). Among them, the initialization period (A1) is a period for setting the transistor 121 to the off state. The initialization period (A2) is a period for resetting the potential in the anode of the OLED 130, and the initialization period (A3) is a period for applying the potential Vini for turning on the transistor 121 at the beginning of the compensation period (B) to the gate node g via the data line 14.

[0126] In the comparative example, during the initialization period (A1) of each horizontal scanning period (H), the control signal / Drst is at an L level, the control signal / Gini is at an H level, the control signal / Grst is at an H level, and the control signal / Gref is at an L level. Therefore, the transistor 82 is turned on, the transistor 84 is turned off, the transistor 86 is turned off, and the transistor 62 is turned on.

[0127] In the comparative example, during the initialization period (A1) of the horizontal scanning period (H) for selecting the i-th row, the scanning signal / Gwr(i) is at the L level, the control signal / Gcmp(i) is at the H level, and the control signal / Gel(i) is at the H level. Therefore, in the pixel circuit 110, the transistor 122 is turned on, and the transistors 123 and 124 are turned off.

[0128] Therefore, in the comparative example, in the pixel circuit 110 of the i-th row during the initialization period (A1), the potential Vel is sequentially supplied to the gate node g of the transistor 121 via the data line 14 and the transistor 122. When the potential Vel is supplied to the gate node g, the voltage between the gate node and the source node becomes zero, so the transistor 121 is forcibly turned off. In addition, one end of the capacitor 70 is fixed to the potential Vref.

[0129] In the comparative example, during the initialization period (A2) of each horizontal scanning period (H), the control signal / Drst changes to the H level, the control signal / Gini maintains the H level, the control signal / Grst changes to the L level, and the control signal / Gref maintains the L level. Therefore, the transistor 82 changes to the off state, the transistor 84 maintains the off state, the transistor 86 changes to the on state, and the transistor 62 maintains the on state.

[0130] In the comparative example, during the initialization period (A2) of the horizontal scanning period (H) for selecting the i-th row, the scanning signal / Gwr(i) changes to the H level, the control signal / Gcmp(i) changes to the L level, and the control signal / Gel(i) changes to the L level. Therefore, in the pixel circuit 110, the transistor 122 changes to the off state, and the transistors 123 and 124 change to the on state.

[0131] Therefore, in the comparative example, in the pixel circuit 110 of the i-th row during the initialization period (A2), the potential Vorst is sequentially supplied to the anode of the OLED 130, that is, the pixel electrode 131, via the data line 14, the transistors 123 and 124. When the potential Vorst is supplied to the pixel electrode 131, the OLED 130 is forcibly extinguished. In addition, since the potential Vorst passes through the drain node d of the transistor 121, the charge remaining in the parasitic capacitor 150 is reset. In addition, one end of the capacitor element 70 is fixed to the potential Vref.

[0132] In the comparative example, the initialization period (A3), compensation period (B) and writing period (C) of the horizontal scanning period (H) of the i-th row are selected to be the same as the initialization period (A), compensation period (B) and writing period (C) in the first embodiment.

[0133] That is, in the comparative example, during the initialization period (A3) in the horizontal scanning period (H) for selecting the i-th row, the potential Vini is supplied to the gate node g of the transistor 121 in the pixel circuit 110 of the i-th row, during the compensation period (B), the gate node g is close to the threshold equivalent potential (Vel-Vth), and during the writing period (C), the potential corresponding to the grayscale level is maintained at the gate node g of the transistor 121.

[0134] In the comparative example, during the drain set period (D) of each horizontal scanning period (H), the control signal / Drst is at an H level, the control signal / Gini is at an H level, the control signal / Grst is at an H level, and the control signal / Gref is at an H level. Therefore, the transistor 82 is turned off, the transistor 84 is turned off, the transistor 86 is turned off, and the transistor 62 is turned off.

[0135] In the comparative example, during the drain set period (D) of the horizontal scanning period (H) for selecting the i-th row, the scanning signal / Gwr(i) is at the H level, the control signal / Gcmp(i) is at the L level, and the control signal / Gel(i) is at the H level. Therefore, in the pixel circuit 110, the transistor 122 is in the OFF state, the transistor 123 is in the ON state, and the transistor 124 is in the OFF state.

[0136] In addition, during the drain set period (D), the control signal / Gref(i) continues to be at the H level from the writing period (C). Therefore, the transistor 62 is in the off state.

[0137] Therefore, in the comparative example, in the pixel circuit 110 of the i-th row during the drain setting period (D), as shown in FIG. Fig.24 As shown, during the writing period (C), the potential held in the data line 14 and the parasitic capacitance 72 , that is, the potential corresponding to the grayscale level is supplied to the drain node d of the transistor 121 via the transistor 123 .

[0138] Fig.11 It is a diagram showing potential changes of various parts in the pixel circuit 110 of the electro-optical device 10 according to the first embodiment in comparison with the above-mentioned comparative example.

[0139] Here, the potential of the data line 14 is marked as Vdt, and the potential at the drain node d of the transistor 121 is marked as Vdr_d. In addition, this is an example of a case where the OLED 130 in the pixel circuit 110 is set to the black level of the lowest grayscale. In addition, the potential change in the first embodiment is represented by the solid line p, and the potential change in the comparative example is represented by the dotted line q.

[0140] In this case, in the first embodiment, the potential Vdt of the data line 14 becomes the potential Vini during the initialization period (A), approaches the threshold equivalent potential (Vel-Vth) during the compensation period (B), and becomes the potential Vbk equivalent to the black level during the writing period (C). In addition, as described above, the potential Vbk is roughly equal to the potential Vel. In the first embodiment, the potential Vdt of the data line 14 becomes the potential Vini during the drain setting period (D). The light-emitting period (E) is also the initialization period (A) in the next horizontal scanning period, so in the first embodiment, the potential Vdt of the data line 14 becomes the potential Vini.

[0141] In the comparative example, the potential Vdt of the data line 14 becomes the potential Vini during the initialization period (A3) which is the end of the initialization period (A), approaches the threshold equivalent potential (Vel-Vth) during the compensation period (B), and becomes the potential Vbk during the writing period (C). So far, it is the same as the first embodiment. In the comparative example, the potential Vdt of the data line 14 is maintained at the potential Vbk (≈Vel) corresponding to the grayscale level during the writing period (C) and the drain setting period (D). In addition, in the comparative example, the light-emitting period (E) is the initialization period (A1) in the next horizontal scanning period, so the potential Vdt of the data line 14 is the potential Vel and hardly changes.

[0142] In the first embodiment, since the transistor 123 is in the on state during the compensation period (B), the potential Vdr_d of the drain node d of the transistor 121 is equal to the potential Vdt and is close to the threshold equivalent potential (Vel-Vth).

[0143] In the first embodiment, when the transistor 123 is turned off at the end of the compensation period (B), the gate node g is substantially at the threshold potential (Vel-Vth), so the transistor 121 is turned on. Therefore, the potential Vdr_d at the drain node d of the transistor 121 rises to the potential Vel.

[0144] During the writing period (C), the gate node g rises from the threshold equivalent potential (Vel-Vth) to the potential Vbk (≈Vel) corresponding to the black level. This potential rise is propagated to the drain node d via the capacitance parasitic between the gate node and the source node in the transistor 121. Therefore, during the writing period (C), the potential Vdr_d of the drain node d of the transistor 121 further rises from the potential Vel.

[0145] In the first embodiment, the potential Vdr_d of the drain node d becomes the potential Vini due to the on state of the transistor 123 during the drain set period (D). At the end of the drain set period (D) or the beginning of the light emission period (E), the transistor 123 changes from the on state to the off state, thereby the potential Vdr_d of the drain node d rises from the potential Vini. That is, the control signal / Gcmp(i) of the i-th row changes from the L level to the H level, and this potential rise is propagated to the drain node d via the capacitance parasitic between the gate node and the source node in the transistor 123, so the potential Vdr_d rises from the potential Vini.

[0146] In the comparative example, the potential Vdr_d of the drain node d of the transistor 121 approaches the threshold equivalent potential (Vel-Vth) during the compensation period (B), rises to the potential Vel at the end of the compensation period (B), and further rises from the potential Vbk (≈Vel) equivalent to the black level during the writing period (C). This is the same as the first embodiment. In the comparative example, during the drain set period (D), the transistor 123 is turned on while the transistor 84 is turned off, so the potential Vdr_d of the drain node d is equal to the potential Vbk (≈Vel) of the potential Vdt of the data line 14.

[0147] At the end of the drain set period (D) or the beginning of the light emission period (E), the transistor 123 changes from the on state to the off state, whereby the potential Vdr_d of the drain node d rises from the potential Vbk (≈Vel).

[0148] When the OLED 130 in the pixel circuit 110 is set to the black level of the lowest grayscale, in the comparative example, during the drain set period (D), the potential Vdr_d of the drain node d of the transistor 121 is substantially the potential Vel, and the potential Vel is held by the parasitic capacitor 150. That is, a charge remains in the parasitic capacitor 150. In this state, when the light emission period (E) is reached and the transistor 124 changes to the on state, the charge remaining in the parasitic capacitor 150 flows into the OLED 130, and the OLED 130 emits light slightly. Therefore, in the comparative example, although the black level of the lowest grayscale is intended to be expressed, the OLED 130 emits light slightly, and the realization of high contrast is hindered.

[0149] In contrast, in the first embodiment, when the OLED 130 is set to the black level of the lowest grayscale, the potential Vdr_d of the drain node d of the transistor 121 is a potential Vini lower than the potential Vel during the drain set period (D). Therefore, in the first embodiment, the charge remaining in the parasitic capacitor 150 is less than that in the comparative example, so even if the charge remaining in the parasitic capacitor 150 flows into the OLED 130 during the light emission period (E), the degree of light emission of the OLED 130 is less than that in the comparative example.

[0150] Therefore, in the first embodiment, a higher contrast ratio than that of the comparative example can be achieved.

[0151] In the comparative example, when the display is set to black level, the potential Vdt of the data line 14 becomes the potential Vbk (≈Vel) during the drain setting period (D), becomes the potential Vel during the initialization period (A1) of the next horizontal scanning period (H), becomes the potential Vorst during the initialization period (A2), and becomes the potential Vini during the initialization period (A3). That is, in the comparative example, the potential Vdt of the data line 14 decreases from the potential Vel to the potential Vorst during the initialization period from the drain setting period (D) to the next horizontal scanning period, and then increases to the potential Vini.

[0152] In contrast, in the first embodiment, the potential Vdt of the data line 14 is the potential Vini during the drain setting period (D), and is also the potential Vini during the initialization period (A) of the next horizontal scanning period (H). That is, in the first embodiment, the potential Vdt of the data line 14 is constant at the potential Vini during the initialization period from the drain setting period (D) to the next horizontal scanning period.

[0153] Therefore, in the first embodiment, the power consumed by the parasitic capacitance 72 due to the potential amplitude of the data line 14 is suppressed compared with the comparative example.

[0154] In addition, in the technology described in the above-mentioned patent document 1, the potential Vorst is supplied to the drain node d of the transistor 121 during the period corresponding to the drain set period (D), while in the first embodiment, the potential Vini higher than the potential Vorst is supplied. Therefore, in the case of a black level display, the amount of decrease in the potential Vdt of the data line 14 from the writing period (C) to the drain set period (D) is smaller than in the technology described in the patent document 1 in the first embodiment.

[0155] In the technology described in patent document 1, when the display is set to black level, the potential Vdt of the data line 14 becomes the potential Vorst during the drain setting period (D), becomes the potential Vel during the initialization period (A1) of the next horizontal scan period (H), becomes the potential Vorst during the initialization period (A2), and becomes the potential Vini during the initialization period (A3).

[0156] On the other hand, in the first embodiment, the potential Vdt of the data line 14 is kept constant at the potential Vini during the initialization period from the drain set period (D) to the next horizontal scanning period as described above.

[0157] Therefore, in the first embodiment, the power consumed by the parasitic capacitance 72 due to the potential amplitude of the data line 14 is suppressed not only compared with the comparative example but also compared with the technology described in Patent Document 1.

[0158] In the first embodiment described above, when the potential Vini is supplied to the gate node g, the transistor 121 needs to be turned on. Therefore, the potential Vini needs to be lower than the threshold equivalent potential (Vel-Vth) of the transistor 121 .

[0159] However, if the potential Vini is set to be relatively low, then in order to compensate for the deviation of the threshold characteristics of all transistors 121, it is necessary to set the compensation period (B) to be relatively long, which hinders the shortening of the horizontal scanning period accompanying the high resolution. In addition, if the potential Vini is set to be relatively low, the potential amplitude of the data line 14 becomes larger, and the power consumed by the parasitic capacitance 72 increases, so it is difficult to reduce power consumption. In addition, at the end of the compensation period (B), in order to make the gate node g of the transistor 121 close to the ideal threshold equivalent potential (Vel-Vth), the setting of the potential Vini supplied to the gate node g of the transistor 121 at the beginning of the compensation period (B) becomes important. In this way, when determining the potential Vini, various constraints need to be met.

[0160] If the potential Vini that needs to satisfy various constraints is set at the drain node during the drain setting period (D), it may be impossible to sufficiently suppress the micro-luminescence generated by the charge remaining in the parasitic capacitor 150 flowing into the OLED 130 at the beginning of the light emission period (E). Therefore, a second embodiment of using a potential other than the potential Vini as the potential set at the drain node during the drain setting period (D) is described.

[0161] Second embodiment

[0162] Fig.12 1 is a block diagram showing the electrical structure of the electro-optical device 10 according to the second embodiment. Figure 2 The first embodiment shown is different in that, in the initialization circuit 80 , transistors 85 are provided in a one-to-one correspondence with the data lines 14 .

[0163] The source node of the transistor 85 corresponding to the j-th column is connected to the power supply line of the potential Vini2, and the drain node of the transistor 85 is connected to the data line 14 of the j-th column. In addition, the gate nodes of the transistors 85 in each column are commonly supplied with the control signal / Gini2 output from the control circuit 30. The potential Vini2 is higher than the potential Vini and lower than the potential Vbk.

[0164] Fig.13 This is a timing chart for explaining the operation of the electro-optical device 10 according to the second embodiment.

[0165] Fig.13 The timing diagram shown is similar to Figure 4The difference is that the control signal / Gini maintains the H level from the end of the write period (C) to the end of the drain set period (D), and the control signal / Gini2 is added. The control signal / Gini2 becomes the L level during the drain set period (D) of each horizontal scanning period (H) in 1 frame (V), and becomes the H level in other periods.

[0166] In the second embodiment, in the drain set period (D), the transistor 85 is turned on in each column instead of the transistor 84 being turned off.

[0167] Therefore, during the drain set period (D), although not particularly shown, the potential Vini2 is supplied to the drain node d of the transistor 121 in the pixel circuit 110 of the i row and j column in sequence via the transistor 85 , the data line 14 of the j column, and the transistor 123 .

[0168] Therefore, in the second embodiment, in the drain set period (D), the potential set at the drain node uses the potential Vini2 which is independent of the potential Vini, so that the degree of freedom in setting the potentials Vini and Vini2 can be increased.

[0169] In the first embodiment or the second embodiment, the potential Vref plays the role of fixing the potential of one end of the capacitor 70 when the potential of the data line 14, that is, the potential of the other end of the capacitor 70 varies during the initialization period (A) and the compensation period (B).

[0170] Therefore, a third embodiment will be described in which the potential Vref is used as a potential other than the potential Vini as a potential set at the drain node during the drain set period (D).

[0171] Third embodiment

[0172] Fig.14 1 is a block diagram showing the electrical structure of the electro-optical device 10 according to the third embodiment. Figure 2 The first embodiment shown is different in that, in the initialization circuit 80 , transistors 87 are provided in a one-to-one correspondence with the data lines 14 .

[0173] The source node of the transistor 87 corresponding to the jth column is connected to the supply line of the potential Vref, and the drain node of the transistor 87 is connected to the data line 14 of the jth column. The control signal / Gref2 outputted from the control circuit 30 is commonly supplied to the gate nodes of the transistors 87 in each column.

[0174] In the third embodiment, the control signal / Gref2 becomes Fig.13In the third embodiment, the control signal / Gini is not the same as the control signal / Gini2. Figure 4 Same waveform, but with Fig.13 Same waveform.

[0175] In the third embodiment, in the drain set period (D), the transistor 87 is turned on in each column instead of the transistor 84 being turned off.

[0176] Therefore, during the drain set period (D), although not particularly shown, the potential Vref is sequentially supplied to the drain node d of the transistor 121 via the transistor 87 , the j-th column data line 14 , and the transistor 123 in the pixel circuit 110 of the i-th row and the j-th column.

[0177] Therefore, in the third embodiment, during the drain set period (D), the potential set at the drain node does not use the potential Vini but uses the potential Vref, thereby increasing the degree of freedom in setting the potential Vini. In addition, in the third embodiment, compared with the second embodiment, it is not necessary to generate an independent potential Vini2, so the circuit structure for generating the potential can be simplified.

[0178] In the third embodiment, the potential Vref is set to be equal to or higher than the potential Vini and lower than the potential Vbk.

[0179] In the first to third embodiments, the initialization circuit 80 supplies the potential set at the drain node during the drain set period (D), but another element other than the initialization circuit 80, specifically, another element in the pixel circuit 110, may supply the potential.

[0180] Therefore, a fourth embodiment will be described in which the pixel circuit 110 itself supplies a potential set at the drain node during the drain set period (D).

[0181] Furthermore, the fourth embodiment is different from the first embodiment in the structure of the pixel circuit.

[0182] Fourth embodiment

[0183] Fig.15 FIG. 1 is a diagram showing a pixel circuit 110 of an electro-optical device 10 according to a fourth embodiment. Figure 3 The first embodiment shown is different in that a transistor 126 is provided for electrically connecting the drain node d of the transistor 121 to the power supply line of the potential Vini2 during the drain set period (D).

[0184] The control signal / Gini2(i) outputted from the control circuit 30 is commonly supplied to the gate nodes of the transistors 126 in the pixel circuits 110 in the i-th row. That is, the control signal / Gini2(i) is supplied for each row.

[0185] Fig.16 1 is a timing chart showing the operation of the electro-optical device 10 according to the fourth embodiment, particularly the waveforms of the control signal / Gini2(i-1) of the (i-1)th row and the control signal / Gini2(i) of the i-th row.

[0186] As shown in the figure, during the drain setting period (D) of the horizontal scanning period (H) of the i-th row, the control signal / Gini2(i) becomes L level and the control signal / Gcmp(i) becomes H level. In the fourth embodiment, the control signal / Gini2(i) maintains H level from the end of the writing period (C) to the end of the drain setting period (D). Fig.13 The second embodiment shown is the same.

[0187] In the fourth embodiment, during the drain setting period (D) of the horizontal scanning period (H) of the i-th row, the transistor 123 is turned off and the transistor 126 is turned on. Therefore, during the drain setting period (D), although not particularly shown, in the pixel circuit 110 of the i-th row and the j-th column, the potential Vini2 is supplied to the drain node d of the transistor 121 via the transistor 126.

[0188] Therefore, in the fourth embodiment, during the drain set period (D), the potential set at the drain node is not supplied via the data line 14 unlike the first to third embodiments, thereby being able to suppress power consumed by charging and discharging the data line 14 (parasitic capacitance 72).

[0189] In addition, in the fourth embodiment, the drain setting period (D) in the horizontal scanning period (H) of the i-th row can be performed independently of other rows.

[0190] Furthermore, in the fourth embodiment, the drain setting period (D) of the horizontal scanning period (H) of the i-th row can be performed in parallel with the writing period (C). In the fourth embodiment, if the drain setting period (D) and the writing period (C) are performed in parallel, the compensation period (B) can be ensured to be longer accordingly, or the horizontal scanning period (H) can be shortened to achieve higher resolution.

[0191] In addition, for example, Fig.16As shown by the dotted line Dw, the scanning signal / Gwr(i) can also be configured to change from the L level to the H level during the drain setting period (D) of the horizontal scanning period (H) of the i-th row. In this structure, the writing period (C) and the drain setting period (D) are performed in parallel until the middle of the drain setting period (D).

[0192] In such a structure, when the transistor 122 changes from the on state to the off state, the transistor 126 is in the on state. Therefore, the influence when the transistor 122 changes to the off state can be suppressed. In addition, this influence specifically refers to the following phenomenon: due to the feed-through of the transistor 122, the potential of the drain node of the transistor 122 (the gate node g of the transistor 121) rises, and the potential rise causes the potential of the drain node d to change via the parasitic capacitance between the gate node and the drain node of the transistor 121.

[0193] In the fourth embodiment, the potential set at the drain node d during the drain set period (D) is supplied via the transistor 126 provided separately in the pixel circuit 110, but the present invention is not limited to this structure. In short, any structure may be used as long as the charge remaining in the parasitic capacitor 150 is reduced before the light emission period (E).

[0194] Therefore, a fifth embodiment and a sixth embodiment are described in which the charge remaining in the parasitic capacitance 150 is reduced before the light emission period (E) by using elements other than the transistor 126 .

[0195] Fifth embodiment

[0196] Fig.17 FIG. 1 is a diagram showing a pixel circuit 110 of an electro-optical device 10 according to a fifth embodiment. Figure 3 The difference of the first embodiment shown is that a capacitor 161 is provided between the drain node d of the transistor 121 and the discharge control line 170. In detail, in the capacitor 161, one electrode is connected to the drain node d of the transistor 121, and the other electrode is connected to the discharge control line 170. In the fifth embodiment, the capacitor 161 is a metal capacitor of a MIM (Metal Insulator Metal) structure in which an insulating layer is sandwiched between different conductive layers in a semiconductor substrate. In addition, the discharge control line 170 of the pixel circuit 110 of the i-th row is commonly supplied with a control signal / Ds(i) output from the control circuit 30. That is, the control signal / Ds(i) is supplied for each row.

[0197] Sixth Embodiment

[0198] Fig.18FIG. 1 is a diagram showing a pixel circuit 110 of an electro-optical device 10 according to a sixth embodiment. Fig.17 The fifth embodiment shown is different in that the capacitor 161 is replaced by a capacitor 162. Specifically, the capacitor 162 is a MOS capacitor in which the source node and the drain node of one electrode are connected to the drain node d of the transistor 121, and the other electrode is connected to the gate node. That is, the capacitor 162 is formed by sandwiching the gate insulating layer of the transistor by the semiconductor layer (lower electrode) of the transistor and the gate electrode layer (upper electrode).

[0199] In the sixth embodiment, similarly to the fifth embodiment, the control signal / Ds(i) outputted from the control circuit 30 is commonly supplied to the discharge control lines 170 of the pixel circuits 110 in the i-th row.

[0200] Fig.19 It is a timing chart showing the operation of the electro-optical device 10 according to the fifth or sixth embodiment, particularly the waveforms of the control signal / Ds(i-1) of the (i-1)th row and the control signal D / s(i) of the i-th row.

[0201] As shown in the figure, the control signal D / s(i) of the i-th row becomes an H level at the beginning of the horizontal scanning period (H) of the i-th row, and at the beginning of the drain setting period (D), the control signal D / s(i) is reduced from the H level to the L level, thereby reducing the charge remaining in the parasitic capacitor 150 due to the potential of the drain node d.

[0202] Modifications and Applications

[0203] In the above-mentioned first to sixth embodiments (hereinafter referred to as "embodiments etc."), various modifications or applications are possible as follows.

[0204] In the embodiments, etc., Fig. 20 As shown in (1), the period from the initialization period (A) to the drain setting period (D) converges within one horizontal scanning period (H), but the drain setting period (D) does not necessarily have to converge within the one horizontal scanning period (H). Specifically, the initialization period (A), the compensation period (B), and the writing period (C) need to converge within one horizontal scanning period (H), but the drain setting period (D), as shown in Fig. 20 As shown in (2), it only needs to be after the horizontal scanning period and before the light-emitting period (E).

[0205] If the drain setting period (D) is placed after a horizontal scanning period in this way, the period required to converge with the horizontal scanning period (H), especially the compensation period (B), can be ensured to be longer, or the horizontal scanning period (H) can be shortened for high resolution.

[0206] In the embodiments, the reason for performing the drain set period (D) after the write period (C) is described. If the write period (C) ends during the horizontal scan period (H) of the i-th row, the transistor 122 changes from the on state to the off state, and in detail, the potential of the scan signal / Gwr(i) rises from the L level to the H level. This potential rise is propagated through the parasitic capacitance between the gate node and the drain node of the transistor 122, so that the potential of the drain node of the transistor 122, that is, the gate node g of the transistor 121, rises. The potential rise of the gate node g of the transistor 121 is propagated through the parasitic capacitance between the gate node and the drain node of the transistor 121, so that the potential of the drain node d of the transistor 121 rises.

[0207] Therefore, it is efficient to execute the drain set period (D) after the potential of the drain node d rises at the end of the write period (C).

[0208] In the embodiment and the like, the transistors 82 and 86 are provided for comparison and explanation with the comparative example, but as described above, they are not necessary in the embodiment and the like and therefore may not be provided.

[0209] In the embodiments, the OLED 130 is described as an example of a light-emitting element, but other light-emitting elements may be used. For example, an LED may be used as a light-emitting element, or a liquid crystal element may be used in combination with an illumination mechanism. That is, as a light-emitting element, any electro-optical element that can achieve an optical state corresponding to the voltage of the data line 14 may be used.

[0210] In the embodiments and the like, a 10-bit conversion example is shown as the DA conversion circuit 500 , but the present invention is not limited to this.

[0211] The channel types of transistors 64, (82), 84, 85, (86), 87, 121 to 126, etc. are not limited to the embodiments, etc. In addition, the channels of these transistors, etc. may be changed as appropriate, or may be replaced with transmission gates as appropriate.

[0212] Electronic devices

[0213] Next, an electronic device to which the electro-optical device 10 of the embodiment is applied will be described. The electro-optical device 10 is suitable for use in a display with small pixels and high definition. Therefore, a head mounted display will be described as an example of the electronic device.

[0214] Fig.21 is a diagram showing the appearance of a head mounted display, Fig. 22 is a diagram showing its optical structure.

[0215] First, if Fig.21As shown in FIG. 1 , the head mounted display 300 has temples 310, a nose bridge 320, and lenses 301L and 301R in appearance, similar to ordinary glasses. Fig. 22 As shown, the head mounted display 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the nose bridge 320 and on the back side (lower side in the figure) of the lenses 301L and 301R.

[0216] The image display surface of the electro-optical device 10L is Fig. 22 The image display surface of the electro-optical device 10R is arranged on the right side opposite to the electro-optical device 10L. Thus, the image display of the electro-optical device 10R is emitted in the direction of 3 o'clock in the figure via the optical lens 302R. The half-mirror 303R reflects the image display of the electro-optical device 10R in the direction of 6 o'clock, and on the other hand, allows light incident from the direction of 12 o'clock to pass through.

[0217] In this configuration, the wearer of the head mounted display 300 can observe the display images of the electro-optical devices 10L and 10R in a see-through state superimposed on the external scene.

[0218] In the head mounted display 300 , if the electro-optical device 10L displays a left-eye image and the electro-optical device 10R displays a right-eye image in binocular images with parallax, the wearer can perceive the displayed images as if they have depth and three-dimensionality.

[0219] In addition, electronic devices including the electro-optical device 10 can be applied to electronic viewfinders in video cameras, digital cameras with interchangeable lenses, smart watches, display units of wearable devices, light valves of projection projectors, etc., in addition to the head-mounted display 300.

[0220] Notes

[0221] According to the above-exemplified aspects, for example, the following aspects can be understood.

[0222] An electro-optical device involved in one method (method 1) includes a pixel circuit arranged corresponding to a scanning line and a data line, the pixel circuit having a first transistor and a light-emitting element, the first transistor supplies a current corresponding to a voltage between a gate node of the first transistor and a source node of the first transistor to the light-emitting element during a light-emitting period, and, during an initialization period before the light-emitting period, the data line is set to a first potential, during a compensation period after the initialization period and before the light-emitting period, the gate node of the first transistor is set to a second potential corresponding to a threshold voltage of the first transistor, during a first period after the compensation period and before the light-emitting period, the gate node of the first transistor is set from the second potential to a third potential corresponding to the brightness of the light-emitting element, and during a second period after the first period and before the light-emitting period, the drain node of the first transistor is set to a fourth potential that is greater than the first potential and less than the third potential.

[0223] According to the electro-optical device of aspect 1, the charge remaining in the parasitic capacitance of the drain node of the first transistor is prevented from flowing into the light-emitting element during the light-emitting period. Therefore, micro-luminescence caused by the inflow of charge is suppressed, and high contrast is easily achieved.

[0224] In addition, transistor 121 is an example of a first transistor. In the first embodiment, the potential Vini is an example of a first potential and a fourth potential. The threshold equivalent potential (Vel-Vth) at the end of the compensation period (B) is an example of a second potential. The write period (C) is an example of a first period. The potential Vbk supplied to the gate node g of the transistor 121 during the write period (C) is an example of a third potential. The drain set period (D) is an example of a second period. Preferably, during the initialization period, the gate node of the first transistor is the first potential.

[0225] In the electro-optical device according to a specific aspect 2 of aspect 1, the fourth potential is the same as the first potential. According to the electro-optical device according to aspect 2, since the fourth potential also serves as the first potential, the circuit for generating the potential can be simplified.

[0226] In the electro-optical device according to a specific embodiment 3 of the embodiment 1, the fourth potential is higher than the first potential. When the gate node of the first transistor is at the first potential during the initialization period and at the second potential corresponding to the threshold voltage during the compensation period, the first potential is accompanied by various constraints. According to the electro-optical device of embodiment 3, the fourth potential uses a potential independent of the first potential, so the degree of freedom in setting the fourth potential is improved.

[0227] The potential Vini2 in the second embodiment or the potential Vref in the third embodiment is an example of the fourth potential.

[0228] In the electro-optical device according to a specific aspect 4 of the aspect 1, during the second period, the drain node of the first transistor is set to the fourth potential via the data line.

[0229] The electro-optical device according to a specific aspect 5 of the aspect 1 includes a second transistor that electrically connects the power supply line of the fourth potential to the drain node of the first transistor during the second period.

[0230] In the electro-optical device of a specific aspect 6 of the aspect 1, a capacitor is provided, one electrode of the capacitor is connected to the drain node of the first transistor, and the other electrode of the capacitor is connected to a discharge control line.

[0231] In the electro-optical device according to a specific aspect 7 of aspect 6, the capacitor element is a metal capacitor. In addition, the capacitor element 161 is an example of a metal capacitor.

[0232] In the electro-optical device according to a specific aspect 8 of aspect 6, the capacitor element is a MOS capacitor. The capacitor element 162 is an example of a MOS capacitor.

[0233] An electronic device according to aspect 9 includes the electro-optical device according to any one of aspects 1 to 8.

Claims

1. An electro-optical device, wherein: The electro-optical device includes pixel circuits arranged corresponding to the scan lines and the data lines. The pixel circuit comprises a first transistor and a light emitting element. The first transistor supplies a current corresponding to a voltage between a gate node of the first transistor and a source node of the first transistor to the light emitting element during a light emitting period, and During the initialization period before the light emitting period, the data line is set to a first potential. During a compensation period after the initialization period and before the light emitting period, the gate node of the first transistor is set to a second potential corresponding to the threshold voltage of the first transistor, In a first period after the compensation period and before the light emitting period, the gate node of the first transistor is set from the second potential to a third potential corresponding to the brightness of the light emitting element, In a second period after the first period and before the light emitting period, the drain node of the first transistor is set to a fourth potential that is higher than the first potential and lower than the third potential.

2. The electro-optical device according to claim 1, wherein: The fourth potential is the same as the first potential.

3. The electro-optical device according to claim 1, wherein: The fourth potential is higher than the first potential.

4. The electro-optical device according to claim 1, wherein: During the second period, the drain node of the first transistor is set to the fourth potential via the data line.

5. The electro-optical device according to claim 1, wherein: The electro-optical device includes a second transistor that electrically connects the fourth potential power supply line to a drain node of the first transistor during the second period.

6. The electro-optical device according to claim 1, wherein: The electro-optical device includes a capacitor element having one electrode connected to the drain node of the first transistor and the other electrode connected to a discharge control line.

7. The electro-optical device according to claim 6, wherein: The capacitor element is a metal capacitor.

8. The electro-optical device according to claim 6, wherein: The capacitor element is a MOS capacitor. 9 . An electronic device comprising the electro-optical device according to claim 1 .

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