Semiconductor memory device

By designing active patterns, device isolation patterns, bit lines, word lines, multiple electrode plates, common electrode patterns and ferroelectric patterns in semiconductor memory devices, the problem of insufficient integration and current driving capabilities in the prior art is solved, and higher integration and improved electrical characteristics are achieved, and manufacturing costs are reduced.

CN119697996APending Publication Date: 2025-03-25SAMSUNG ELECTRONICS CO LTD
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Patent Information

Application Number
CN202410513181.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2023-09-25
Filing Date
2024-04-26
Publication Date
2025-03-25

AI Technical Summary

Technical Problem

While improving the integration and reducing resistance, existing semiconductor memory devices are difficult to effectively improve the current driving capability, and have high process complexity and high manufacturing cost.

Method used

A semiconductor memory device is designed, adopting structures such as active patterns, device isolation patterns, bit lines, word lines, multiple electrode plates, common electrode patterns and ferroelectric patterns. Through the combination of these structures, higher integration and improved electrical characteristics are achieved.

Benefits of technology

With this design, higher integration and improved electrical characteristics of semiconductor memory devices are achieved, reducing manufacturing costs and improving current driving capabilities.

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Abstract

There is provided a semiconductor memory device including: a device isolation pattern in a semiconductor substrate and defining an active pattern extending in a first direction; a bit line crossing the active pattern on the semiconductor substrate and extending in a second direction forming an acute angle with the first direction; a word line extending across the active pattern in a third direction crossing the second direction and extending into the semiconductor substrate; electrode plates vertically stacked on the bit lines; a common electrode pattern extending through the electrode plate to the active pattern on one side of the bit line; and a ferroelectric pattern between the common electrode pattern and the electrode plate. The bit line is in contact with an upper surface of the active pattern and an upper surface of the device isolation pattern.
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