IGZO-FET device with suspended nanowire structure and preparation method thereof

By using a combination of suspended nanowire structure and IGZO channel layer in IGZO thin film transistors, the problem of short channel effect is solved, and the effect of high integration density and driving current is achieved, which is suitable for high-performance displays and integrated circuits.

CN119698021AActive Publication Date: 2025-03-25NANJING UNIV
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Patent Information

Application Number
CN202510194397.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-02-21
Publication Date
2025-03-25
Estimated Expiration
2045-02-21

AI Technical Summary

Technical Problem

The existing IGZO thin film transistors are prone to severe short-channel effects when the channel length is reduced, resulting in increased leakage current and deterioration of switching characteristics. The device scaling and integration density are limited, making it difficult to meet the needs of high-resolution displays or high-performance integrated circuits.

Method used

Using a suspended nanowire structure, by alternately depositing silicon oxide and silicon nitride stacks on the substrate, vertically parallel nanowires are grown, and IGZO channel layer and other electrode layers are deposited on their surface to form a CAA or GAA IGZO-FET device.

Benefits of technology

It effectively avoids the short channel effect, improves the device's integration density and driving current, enhances gate control capabilities and electrical stability, and is suitable for high-definition displays and high-density integrated circuits.

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Abstract

The invention relates to the technical field of microelectronic manufacturing. The invention discloses an IGZO-FET (Indium Gallium Zinc Oxide-Field Effect Transistor) device with a suspended nanowire structure, which is characterized in that a gate dielectric layer, an IGZO channel layer, a source electrode layer, a drain electrode layer, a suspended electrode and a suspended nanowire linked with the suspended electrode are sequentially deposited on the surface of the suspended nanowire structure from inside to outside to form a gate electrode of the CAA IGZO-FET device; the suspended electrode is provided with an opening area used for applying grid voltage to a grid electrode formed by connecting the suspended electrode with the suspended nanowire; or the buffer layer, the IGZO channel layer, the source electrode layer, the drain electrode layer, the gate dielectric layer and the gate electrode layer are sequentially deposited on the surface of the suspended nanowire structure from inside to outside to form the GAA IGZO-FET device. The high driving current and the low sub-threshold swing are obtained, the integration density of the high-performance IGZO transistor is effectively improved, and the high-performance IGZO transistor is suitable for high-definition display and high-density integrated circuits.
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