Gate structure of semiconductor device
By introducing a highly doped conductive polysilicon layer into the gate structure of the semiconductor device, the problems of uneven gate depletion and parasitic capacitance in the prior art are solved, and more efficient drain current and more stable high-frequency performance are achieved.
CN119698024APending Publication Date: 2025-03-25TEXAS INSTRUMENTS INC
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Patent Information
- Application Number
- CN202411508738.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-22
- Filing Date
- 2024-10-28
- Publication Date
- 2025-03-25
AI Technical Summary
Technical Problem
In high-frequency applications, existing semiconductor devices have problems with uneven gate exhaustion and parasitic capacitance, which affects the stability and efficiency of drain current.
Method used
A highly doped conductive polysilicon layer is introduced into the gate structure of the semiconductor device, forming ohmic contacts through a self-alignment process with the gate layer, improving gate decoupling and parasitic capacitance while maintaining a high energy barrier height Schottky junction.
Benefits of technology
A more uniform gate depletion is achieved, parasitic capacitance is reduced, drain current stability and efficiency are improved, and high energy barrier performance is maintained in high-frequency applications.
✦ Generated by Eureka AI based on patent content.
Abstract
The present disclosure generally relates to conductive layers in gate structures of semiconductor devices. The conductive layer may be a silicon layer. An example is a semiconductor device (100, 200). The semiconductor device (100, 200) includes a channel layer (106), a barrier layer (108), a gate layer (120), and a silicon layer (122, 222). The channel layer (106) is over the semiconductor substrate (102). The barrier layer (108) is over the channel layer (106). The gate layer (120) is over the barrier layer (108). The silicon layer (122, 222) is over and in contact with the gate layer (120).
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