Preparation method of semiconductor device and semiconductor device

By etching and back-etching the pseudo gate of the second type transistor in the semiconductor integrated circuit manufacturing process, the morphology is optimized and the top is non-arched, which solves the metal loss problem caused by the difference in thickness of the PMOS and NMOS gates, and achieves the complete filling of the gate metal and the improvement of yield.

CN119698057AActive Publication Date: 2025-03-25SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
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Patent Information

Application Number
CN202311218591.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2023-09-20
Publication Date
2025-03-25
Estimated Expiration
2043-09-20

AI Technical Summary

Technical Problem

In the semiconductor integrated circuit manufacturing process, there is a difference in the thickness of the gate hard mask SiO2 of PMOS and NMOS, which leads to easy gate metal loss in subsequent processes, resulting in yield loss and reliability risks.

Method used

By performing an etch and back etching process on the semiconductor structure, the dummy gate morphology of the second type transistor is optimized so that its top is non-arched, and the dummy gate is removed and the conductive dielectric is filled to form the gate after grinding.

Benefits of technology

Complete filling of gate metal is achieved, the yield rate of semiconductor devices is improved, and yield loss and reliability risks are reduced.

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Abstract

The invention discloses a preparation method of a semiconductor device and the semiconductor device, which are applied to the technical field of semiconductor devices, and comprises the following steps: obtaining a semiconductor structure; etching the photoresist to expose the side wall with a preset height; etching the semiconductor structure with the exposed side wall according to a preset etching time until a part of hard mask is left at the top of the dummy gate of the second type transistor; and executing a back-etching process based on the etched semiconductor structure, and grinding the surface of the semiconductor structure after the back-etching process is completed, so that the top of the dummy gate of the second-type transistor is of a non-arched structure. By reducing the etching time, the arch degree of the top of the second-type transistor grid is effectively reduced; in cooperation with a subsequent grinding process, the top of the dummy gate of the second type transistor can be of a non-arched structure, it is guaranteed that the hole after the dummy gate is removed has enough size, gate metal is completely filled, and it is guaranteed that the semiconductor device has a high yield.
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