Verification data processing method and equipment of memory and storage medium
By introducing a verification chip into the memory and encoding the data using the target data verification algorithm, the problem of insufficient verification capabilities of low-cost memory types is solved, and the dual optimization of memory stability and cost is achieved.
CN119718763APending Publication Date: 2025-03-28HANGZHOU ALICLOUD FEITIAN INFORMATION TECH CO LTD
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Patent Information
- Application Number
- CN202311283208.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-28
- Publication Date
- 2025-03-28
AI Technical Summary
Technical Problem
Low-cost memory types have poor verification capabilities, which can easily lead to memory downtime.
Method used
By introducing a verification chip in the memory, the data is encoded using the target data verification algorithm to generate a verification unit and an information data unit to realize the checksum correction when reading data.
Benefits of technology
While reducing memory costs, the stability of the memory is improved, and bounded error checksum correction is realized when there is less verification data.
✦ Generated by Eureka AI based on patent content.
Abstract
The embodiment of the invention provides a verification data processing method and equipment of a memory and a storage medium. When data in a target cache line is written into a plurality of data chips in a memory, the data in the target cache line can be coded according to a corresponding channel (data queue, DQ) region when the data is written into the data chips by adopting a coding mode corresponding to a target data verification algorithm, so that the data in the target cache line can be coded. And obtaining the first number of verification units and a plurality of information data units corresponding to the plurality of data chips. Wherein the target cache line is integrally coded, so that the data volume of the verification data can be effectively reduced. In the data reading stage, the information data units in the single channel area in any target data chip can be verified and / or corrected according to the first number of verification units, verification and / or correction of bounded errors in the isolation boundary are / is achieved under the condition that verification data is less, the cost of the memory is reduced, and meanwhile the memory performance is improved. The stability of the memory is ensured.
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