Method and computing device for predicting potential risk factors in semiconductor layout
By integrating machine learning and image interpretation modules in computing devices, and using IG technology to generate attribute map images, the problem of difficult identification of potential defect-induced elements in semiconductor devices is solved, and advance prediction of potential risk factors and improvement of semiconductor devices are achieved.
CN119720914APending Publication Date: 2025-03-28SAMSUNG ELECTRONICS CO LTD
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Patent Information
- Application Number
- CN202411239261.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-03
- Filing Date
- 2024-09-05
- Publication Date
- 2025-03-28
AI Technical Summary
Technical Problem
In the design and production of semiconductor devices, it is difficult to identify and define potential defect-induced elements in advance, resulting in a decrease in the yield rate of the equipment.
Method used
By integrating machine learning modules and image interpretation modules in computing devices, the attribute map images are generated using integral gradient (IG) technology to visualize and predict potential defect-induced factors.
Benefits of technology
This method can predict potential risk factors in advance, improve the yield rate of semiconductor equipment, reduce the number of trial and errors of design engineers, and improve the performance of equipment.
✦ Generated by Eureka AI based on patent content.
Abstract
A computing device is provided that predicts potential defect inducing factors within a semiconductor layout. The computing device includes a machine learning module that computes predicted measurement data corresponding to at least one first semiconductor layout image among a plurality of semiconductor layout images after training based on the plurality of semiconductor layout images and corresponding actual measurement data, and an image interpretation module that interprets the predicted measurement data corresponding to at least one first semiconductor layout image from among the plurality of semiconductor layout images after training based on the plurality of semiconductor layout images and corresponding actual measurement data, and an attribute map detection unit that generates an attribute map image of the predicted measurement data on the basis of an image regression model using an integral gradient (IG) method, pre-analyzes the attribute map image, and detects elements within the attribute map image having attribute values with high sensitivity to the predicted measurement data as potential defect inducing factors.
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