Bit error judgment method for CANFD frame, controller and communication system

Abstract

The invention relates to a bit error judgment method for a CANFD frame, a controller and a communication system, data to be sent and bit time sequence parameters are stored in a configuration register and then transmitted to a bit stream processor and a bit time sequence unit through a sending cache, a sampling point and a sending point are generated in the bit time sequence unit according to the bit time sequence parameters, and a bit error judgment result is obtained. The method comprises the following steps: generating a sending bit in a bit stream processor according to data to be sent and a sending point to construct a CANFD frame, outputting the frame through a sending port, sequentially transmitting the generated sending bit to an error management unit, collecting at a receiving port, generating a sampling bit, analyzing the sampling bit, and transmitting an analysis result to the error management unit, in the unit, for the data bits in the high-speed data bit time period, the data bits of the data to be sent are directly obtained from the configuration register and are sequentially compared with the analysis result, and if differences exist, bit errors are judged. By adopting the method, the difficulty and inaccuracy of SSP calculation in the prior art can be effectively avoided.

Description

Technical Field

[0001] The present application relates to the field of CANFD communication technology, and in particular to a bit error judgment method, a controller and a communication system for a CANFD frame. Background Art

[0002] The CANFD communication system is a network standard commonly used in vehicles and other control systems. It allows data to be transmitted at different communication rates. In the CANFD system, the transmitter needs to detect whether the received level is consistent with the sent level while sending data to determine whether there is a bit error.

[0003] However, in the prior art, for data bits in a high-speed data bit period, calculating the position of the second sampling point (SSP) is difficult and uncertain, especially in high-speed communication. Summary of the invention

[0004] Based on this, it is necessary to provide a bit error judgment method, controller and communication system for CANFD frames that can improve the accuracy of bit error judgment in response to the above technical problems.

[0005] A method for determining a bit error of a CANFD frame, the method being applied to a CANFD controller, the method comprising: Acquire the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register; The data to be sent and the bit timing parameters are transmitted from the configuration register to the bit stream processor and the bit timing unit in the CANFD core through the transmission buffer respectively; In the bit timing unit in the CANFD core, a sampling point and a sending point are generated according to the bit timing parameters, and the sampling point and the sending point are transmitted to the bit stream processor; In the bit stream processor, a transmission bit is generated according to the data to be transmitted and the transmission point, so as to construct a CANFD frame, and the CANFD frame is output through a transmission port, and the generated transmission bits are sequentially transmitted to an error management unit; The CANFD frame is collected at the receiving port, transmitted to the bit timing unit, a sampling bit is generated according to the sampling point, and then the bit stream processor parses the CANFD frame according to the sampling bit, and transmits the parsing result to the error management unit in sequence; In the error management unit, for the data bits in the high-speed data bit period, the data to be sent is directly obtained from the configuration register, and each data bit in the data to be sent is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

[0006] In one embodiment, the bit timing parameters are configured via the configuration register; According to the bit timing parameters, the bit timing of the synchronization segment, the Seg1 segment and the Seg2 segment in each data bit in the data to be sent is configured; At the same time, the bit timing of the received samples is configured according to the bit timing parameters, and the boundary between the Seg1 segment and the Seg2 segment is used as the sampling point.

[0007] In one embodiment, in the bit timing unit, the collected CANFD frame is used to generate a sampling bit according to a sampling point, including: For the data bits in the high-speed data bit period, the level value of each received data bit at the sampling point is used as the sampling bit of the data bit.

[0008] In one embodiment, when performing bit error determination in the error management unit: For data bits in a normal bit period, bit errors are determined by comparing the transmitted bit with the sampled bit at the sampling point.

[0009] In one embodiment, the error management unit further determines whether the received data has a format error, an ACK error, a padding error, or a CRC error.

[0010] In one embodiment, in the bitstream processor: The ID value obtained by parsing the received data is transmitted to the filtering unit; In the filtering unit, ID filtering is performed with the configured ID value and mask information to determine whether the received data needs to be received; If the filtering is successful, the received data is stored in the corresponding register via the receiving buffer.

[0011] The present application also provides a controller, the controller comprising a register module, a transmission buffer module, and a CANFD core comprising a bit timing unit, a bit stream processor, and an error management unit; The register module is used to obtain the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register in the register module; The data to be sent and the bit timing parameters are transmitted from the configuration register to the bit stream processor and the bit timing unit in the CANFD core through the transmission buffer module respectively; The bit timing unit is used to generate a sampling point and a sending point according to the bit timing parameter, and transmit the sampling point and the sending point to the bit stream processor; The bit stream processor is used to generate a transmission bit according to the data to be sent and the transmission point, so as to construct a CANFD frame, output the CANFD frame through a transmission port, and transmit the generated transmission bits to the error management unit in sequence; The CANFD frame is collected at the receiving port, transmitted to the bit timing unit, a sampling bit is generated according to the sampling point, and then the bit stream processor parses the CANFD frame according to the sampling bit, and transmits the parsing result to the error management unit in sequence; In the error management unit, for the data bits in the high-speed data bit period, the data to be sent is directly obtained from the configuration register, and each data bit in the data to be sent is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

[0012] In one embodiment, the controller further includes a receiving filtering module and a receiving buffering module; The bit stream processor transmits the ID value obtained by parsing the received data to the filtering unit; The filtering unit is used to perform ID filtering on the ID value in the received data, the configured ID value and the mask information, and determine whether the received data needs to be received; If the filtering is successful, the received data is stored in the corresponding register in the register module via the receiving buffer module.

[0013] The present application also provides a communication system, which is a CANFD communication system, including multiple communication nodes, each of which transmits information through a CAN bus, each of which includes a CANFD controller and a CANFD transceiver, wherein the CANFD controller of each of the communication nodes is the above-mentioned controller.

[0014] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps: Acquire the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register; The data to be sent and the bit timing parameters are transmitted from the configuration register to the bit stream processor and the bit timing unit in the CANFD core through the transmission buffer respectively; In the bit timing unit in the CANFD core, a sampling point and a sending point are generated according to the bit timing parameters, and the sampling point and the sending point are transmitted to the bit stream processor; In the bit stream processor, a transmission bit is generated according to the data to be transmitted and the transmission point, so as to construct a CANFD frame, and the CANFD frame is output through a transmission port, and the generated transmission bits are sequentially transmitted to an error management unit; The CANFD frame is collected at the receiving port, transmitted to the bit timing unit, a sampling bit is generated according to the sampling point, and then the bit stream processor parses the CANFD frame according to the sampling bit, and transmits the parsing result to the error management unit in sequence; In the error management unit, for the data bits in the high-speed data bit period, the data to be sent is directly obtained from the configuration register, and each data bit in the data to be sent is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

[0015] The above-mentioned bit error judgment method, controller and communication system for CANFD frames store the data to be sent and the bit timing parameters in the configuration register, and transmit them to the bit stream processor and the bit timing unit in the CANFD core through the transmission buffer, generate sampling points and transmission points according to the bit timing parameters in the bit timing unit, and transmit the sampling points and the transmission points to the bit stream processor, generate transmission bits according to the data to be sent and the transmission points in the bit stream processor, so as to construct a CANFD frame, and output the CANFD frame through the transmission port, and transmit the generated transmission bits to the error management unit in sequence, collect the CANFD frame at the receiving port, transmit it to the bit timing unit, generate sampling bits according to the sampling points, and then parse the CANFD frame according to the sampling bits by the bit stream processor, and transmit the parsing results to the error management unit in sequence, in the error management unit, for the data bits in the high-speed data bit period, directly obtain the data to be sent from the configuration register, and compare each data bit in the data to be sent with the parsing result of the CANFD frame in sequence, and judge it as a bit error if there is a difference. The use of this method can effectively avoid the difficulty and inaccuracy of calculating SSP in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a CAN bus network structure in one embodiment; Figure 2 A schematic diagram of a data sending node in a CAN bus network in one embodiment; Figure 3 Schematic diagram of the frame format of CANFD in one embodiment; Figure 4 It is a schematic diagram of performing bit error judgment according to the transmitted data TX and the retrieved data RX in one embodiment; Figure 5A schematic diagram of the delay time between sending data TX and retrieving data RX in one embodiment; Figure 6 is a schematic diagram of a second sampling point in an embodiment; Figure 7 A schematic diagram of inaccurate bit error determination using a second sampling point in one embodiment; Figure 8 1 is a flow chart of a method for determining a bit error of a CAN FD frame in one embodiment; Fig. 9 is a structural block diagram of a controller in one embodiment; Fig.10 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] like Figure 1 and 2 As shown in the figure, in the CAN (Controller Area Network) communication system, the CAN FD transceiver is an important component connecting the CAN FD controller and the CAN bus, in which the CAN FD transceiver and the CAN FD controller act as a communication node and communicate with other communication nodes through the CAN bus.

[0019] In the CANFD communication process, the signal is output from the CANFD controller's transmitter CAN_TX. The Transmitter in the CANFD transceiver converts the 0 and 1 digital level sequence into a differential level and sends it to the CAN bus through CANH and CANL. At the same time, the Receiver in the CANFD transceiver reads back the differential level on the CAN bus and converts it into 0 and 1 digital levels, which are transmitted to the CANFD controller's receiver CAN_RX, completing the transmission of the frame. MessageThe process of data transmission and data collection involves multiple links, including the propagation delay of the signal from the controller to the transceiver, the loop delay inside the transceiver, and the delay in the process of the signal returning from the transceiver to the controller. In particular, during the collection process, the CANFD transceiver undergoes two conversions: the Transmitter converts the 0 and 1 digital level sequence into a differential level; the Receiver converts the differential level into a 0 and 1 digital level sequence. Because the conversion takes time, there is bound to be a physical delay. Therefore, when CANFD sends a frame of message, the digital level change on the Rx pin will be delayed by some time compared to the Tx pin.

[0020] In order to ensure the reliability and consistency of transmitted data, the CAN (CANFD) protocol stipulates that when the sender sends a level, it determines whether a bit error occurs by detecting whether the received level is consistent with the sent level. When a CANFD node is used as a sending node, the CAN_TX pin sends a level to the bus while the CAN_RX pin receives the bus level for detection. When the output level is different from the detected bus level, a bit error occurs.

[0021] like Figure 3 The figure shows the frame format of CANFD, where the rate of the nominal bit time is less than 1Mbps, and the speed is changed at the BRS bit, and the bit rate of the high-speed data bit time after the speed change can reach up to 15Mbps. This results in that the data bits in the nominal bit time are wider, while the data bits in the high-speed data bit time are narrower.

[0022] like Figure 4 As shown in the figure, when the sent data, that is, the data output from the transmitting end CAN_TX, is compared with the data collected from the receiving end CAN_RX, for example, at the sampling point A of the res bit of the ordinary bit period of CANFD, RX samples a low level, and at the same time, TX is still at the sending stage A' of the res bit, and the sent level is also a low level. Therefore, the sending level is consistent with the detected receiving level, and there is no bit error.

[0023] However, due to the internal loop delay of the CANFD‌‌ transceiver, the protocol stipulates that the maximum delay is no more than 255ns. If the bit rate of the high-speed data bit period is 10Mbps, that is, one bit time is 100ns, the waveform of the receiving end RX may be delayed more than one bit time of the high-speed data bit period. At the sampling point B of the ESI bit of the high-speed data bit period of CANFD, RX samples a low level. Since the rate of the high-speed data bit period after the speed change is higher than that of the ordinary bit period, TX is already in the DLC position and sends a high level. Therefore, the high level sent at B and B' is detected as a low level, which will cause a bit error. The judgment of this bit error is wrong and is caused by an incorrect sampling point, and this incorrect sampling point is caused by delay and high rate.

[0024] To solve this problem, the CANFD protocol introduces the transmit delay compensation (TDC) technology. By adjusting the delay compensation offset of the transceiver, the sampling point can be moved from the edge to the middle point in the bit time, thus moving away from the edge and improving the sampling accuracy.

[0025] TDC technology is to delay a certain time when sending data bits in the high-speed data bit period, and sample the received bit at the second sampling point SSP (Secondary Sample Point) to correctly sample the received bit corresponding to the sent bit. Every bit in the high-speed data bit period needs to be sampled at the SSP for bit error detection. Quoting the original text on the protocol: "The transmitter shall ignore the bit error detected at the sampling point (SP). At the SSP, the received bit value shall be compared with the delayed sent bit value. If a bit error is detected at the SSP, the transmitter will respond to this bit error at the subsequent sampling point."

[0026] When performing SSP detection, the transmission delay must be measured first. According to the CANFD protocol, the CANFD controller will automatically measure the delay time between the FDF bit on the TX signal line to the falling edge of the res bit and the FDF bit on the RX signal line to the falling edge of the res bit, such as Figure 5 As shown, TDCV is the delay time. That is: SSP position = measurement delay TDCV + transmission delay compensation offset TDCO Furthermore, after calculating the position of the second sampling point (SSP), the transmitter caches the transmission level TX and delays it to the SSP of the bit, and compares the transmission level with the sampled RX level to determine the bit error, such as Figure 6 shown.

[0027] However, the above method will have certain difficulties and uncertainties. For example, the bit rate of the high-speed data bit period is relatively high, which is 10Mbps, that is, one bit time is 100ns, and the maximum possible transceiver loop delay is 255ns. Figure 7 As shown. When the transmitter TX sends the ESI bit, the position of the SSP must be delayed to point A, but at this time the DLC0 bit, DLC1 bit and DLC2 bit have all been sent, which means that before the SSP of ESI arrives, the next 3 bits DLC0, DLC1 and DLC2 must be delayed, and the SSP positions of these 3 bits must be calculated, which increases the difficulty of the design. If the loop delay is relatively small, such as 100ns, then it may be sufficient to only delay the next 1 bit DLC0. Therefore, the above method, i.e., the prior art, also has uncertainty.

[0028] In view of the above problems, in this application, Figure 8 As shown, a method for determining a bit error of a CANFD frame is provided. The method is applied to a CANFD controller and specifically includes the following steps: Step S100, obtaining the data to be sent and the bit timing parameters, and storing the data to be sent and the bit timing parameters in the configuration register.

[0029] Step S110, the data to be sent and the bit timing parameters are transmitted from the configuration register to the bit stream processor and the bit timing unit in the CANFD core respectively through the sending buffer.

[0030] Step S120: In the bit timing unit in the CANFD core, a sampling point and a sending point are generated according to the bit timing parameters, and the sampling point and the sending point are sent to the bit stream processor.

[0031] Step S130, in the bit stream processor, a transmission bit is generated according to the data to be sent and the transmission point, so as to construct a CANFD frame, and the CANFD frame is output through the transmission port, and the generated transmission bits are transmitted to the error management unit in sequence.

[0032] Step S140, sampling the CANFD frame at the receiving port, transmitting it to the bit timing unit, generating sampling bits according to the sampling points, and then the bit stream processor parses the CANFD frame according to the sampling bits, and transmits the parsing results to the error management unit in sequence.

[0033] Step S150, in the error management unit, for the data bits in the high-speed data bit period, directly obtain the data to be sent from the configuration register, and compare each data bit in the data to be sent with the parsing result of the CANFD frame in turn. If there is a difference, it is determined to be a bit error.

[0034] Considering that the value of each data bit sent is stored in different configuration registers before sending, the receiving end directly judges the bit error by sampling RX and comparing the level of a data bit in the received data with the level sent by the bit in the configuration register at the sampling point SP. In this way, a simple method can be used to avoid the difficulty and uncertainty of calculating the SSP point. Therefore, in this application, a method for judging the bit error of the high-speed data bit period of the CANFD frame is proposed. The method stores each bit of data to be sent in the configuration register at the sending end, samples the level received by the receiving end while sending each bit of data, and compares the received level with the data of the bit in the configuration register at the sampling point (SP). If the comparison result is inconsistent, it can be quickly judged as a bit error. The method can detect the bit error directly at the sending end without calculating the complex SSP position, thereby simplifying the process of bit error detection and improving the reliability and efficiency of the system. This method can reduce the dependence on the transmission delay compensation (TDC) technology, thereby simplifying the hardware design and software algorithm.

[0035] In step S100, the bit time (Bit Time) of the synchronization segment (Sync_Seg), Seg1 segment (Prop_Seg+Phase_Seg1) and Seg2 segment (Phase_Seg2) in each data bit in the data to be sent is configured according to the bit timing parameters. At the same time, the bit timing of the received sampling is configured according to the bit timing parameters, and the junction of the Seg1 segment and the Seg2 segment is used as the sampling point.

[0036] In this embodiment, the calculation of the sampling points is determined by the relationship between the transmission rate, the number of time quantizers and the number of sampling points. The selection of the number of sampling points needs to balance factors such as data sampling accuracy, anti-interference ability, bus load and transmission delay.

[0037] Preferably, the sampling points are located at 75% to 90% of the data bits.

[0038] In step S120, in the bit timing unit, a sampling bit is generated according to the received data and the sampling point, including: taking the level value of each data bit in the received data at the sampling point as the sampling bit of the data bit.

[0039] Specifically, the CANFD frame is sampled at the receiving end and sent to the bit timing unit, a sampling point is generated according to the bit timing unit, and the input CANFD frame is sampled at the sampling point to obtain the sampled bit. The bit stream processor parses the sampled bit to obtain that the received data is a certain bit in the CANFD frame format.

[0040] In step S130, the CAN FD frame is output through the sending port and transmitted to other destination communication nodes through the CAN bus.

[0041] In step S150, when performing bit error judgment in the error management unit, bit error judgment is performed on the high-speed data bit period of the received data by comparing each data bit in the data to be sent with the sampled bit of the received data, thereby effectively improving the judgment speed and the accuracy of the judgment.

[0042] In this embodiment, the bit stream processor also transmits the transmission bit and the CRC sequence value to the error bit management unit. In the error management unit, it is also determined whether the received data has a format error, an ACK error, a padding error, or a CRC error according to the received transmission bit and the CRC sequence value.

[0043] Specifically, a format error means that the bit stream processor detects an illegal bit at a fixed format bit. For example, the ACK delimiter is fixed to a high level, and if the bit stream processor detects a low level, the error management unit generates a format error.

[0044] Specifically, an ACK error means that when the CAN FD controller acts as a sending node, when the bit stream processor detects a high level in the ACK bit of the CAN FD message it sends, it will assume that no other node has received the message, and the error management unit will generate an ACK error.

[0045] Specifically, a stuffing error means that when transmitting a CAN FD message, if the bit stream processor detects 6 consecutive identical levels on the bus, the error management unit generates a stuffing error.

[0046] Specifically, a CRC error means that when the CAN FD controller acts as a receiving node, the received CRC sequence is different from the calculated CRC sequence value, and the error management unit generates a CRC error.

[0047] Furthermore, a bit error means that when the bit stream processor sends data, it outputs the sending bit at the sending point and obtains the bus level at the sampling point to obtain the sampling bit. When it is detected that the sending bit and the sampling bit are different, the error management unit issues a bit error.

[0048] In the above-mentioned bit error judgment method for CANFD frames, by directly detecting bit errors at the transmitting end SP, there is no need to calculate the complex SSP position, thereby simplifying the process of bit error detection and improving the reliability and efficiency of the system. This method reduces the reliance on the transmission delay compensation (TDC) technology, thereby simplifying the hardware design and software algorithm. This method simplifies the process of bit error detection and improves the reliability of the system, while avoiding the difficulty and uncertainty of calculating SSP, especially in high-speed communication, and is applicable to various CANFD communication systems without requiring extensive modifications to existing hardware.

[0049] This method can be applied to high-speed communication systems between automotive electronic control units (ECUs) to improve the accuracy and reliability of data transmission and reduce communication failures caused by bit errors.

[0050] It should be understood that although Figure 8 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 8 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0051] like Fig. 9As shown, the present application also proposes a controller according to the above-mentioned bit error judgment method for CANFD frames, including a register module, a sending buffer module, and a CANFD core including a bit timing unit, a bit stream processor and an error management unit. Among them, the register module is used to obtain the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register in the register module, and transmit the data to be sent and the bit timing parameters from the configuration register to the bit stream processor and the bit timing unit in the CANFD core through the sending buffer module. The bit timing unit is used to generate sampling points and sending points according to the bit timing parameters, and transmit the sampling points and the sending points to the bit stream processor. The bit stream processor is used to generate sending bits according to the data to be sent and the sending points, so as to construct a CANFD frame, and output the CANFD frame through the sending port, and at the same time, the generated sending bits are transmitted to the error management unit in sequence, and the CANFD frame is collected at the receiving port and transmitted to the bit timing unit, and the sampling bits are generated according to the sampling points. The bit stream processor parses the CANFD frame according to the sampling bits, and transmits the parsing results to the error management unit in sequence, and the generated sampling bits are transmitted to the error management unit in sequence. In the error management unit, for the data bits in the high-speed data bit period, the data to be sent is directly obtained from the configuration register, and each data bit in the data to be sent is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

[0052] In this embodiment, the bit timing parameters are configured through the configuration register, and the bit timing of the synchronization segment, Seg1 segment and Seg2 segment in each data bit in the transmitted data is configured according to the bit timing parameters. At the same time, the bit timing of the received sampling is configured according to the bit timing parameters, and the junction of the Seg1 segment and the Seg2 segment is used as the sampling point.

[0053] In this embodiment, the calculation of the sampling points is determined by the relationship between the transmission rate, the number of time quantizers and the number of sampling points. The selection of the number of sampling points needs to balance factors such as data sampling accuracy, anti-interference ability, bus load and transmission delay.

[0054] Preferably, the sampling points are located at 75% to 90% of the data bits.

[0055] In this embodiment, generating sampling bits in the bit timing unit according to the received data and the sampling points includes: taking the level value of each data bit in the received data at the sampling point as the sampling bit of the data bit.

[0056] In this embodiment, when the bit error judgment is performed in the error management unit: the bit error judgment is performed on the high-speed data segment of the received data by comparing each data bit in the data to be sent with the sampled bit of the received data, which effectively improves the judgment rate and the accuracy of the judgment.

[0057] In this embodiment, the bit stream processor also sends the transmission bits and the CRC sequence value to the error management unit. The error management unit also determines whether the received data has a format error, an ACK error, a padding error, or a CRC error based on the received transmission bits and the CRC sequence value.

[0058] Furthermore, the controller also includes a receiving filtering module and a receiving cache module, wherein the bit stream processor transmits the ID value obtained by parsing the received data to the filtering unit, and the filtering unit is used to perform ID filtering on the ID value in the received data and the configured ID value and mask information to determine whether the received data needs to be received. If the filtering is successful, the received data is stored in the corresponding register in the register module via the receiving cache module.

[0059] Specifically, the workflow of the CANFD controller includes configuring the parameter register through the CPU, and sending the timing parameters to the bit timing unit of the CANFD core to generate the bit timing of the CANFD transmission. The CPU configures the data, ID value and other information to be sent, that is, sends the data to the configuration register, and sends it to the sending buffer module for storage, and then sends this information to the bit stream processor. Next, the bit timing unit generates the sending point required for sending according to the timing parameters and sends it to the bit stream processor. At the same time, the bit stream processor constructs the data, ID value and other information into a CANFD frame, and outputs it to the CAN bus from the sending port CANTX at each sending point. At this point, the data sending work of the controller is completed.

[0060] Specifically, the workflow of the CANFD controller receiving includes: configuring the parameter register through the CPU, and sending the timing parameters to the bit timing unit of the CANFD core to generate the bit timing of the CANFD transmission. The CPU configures the ID value, mask and other information required for receiving into the configuration register, and sends them to the receiving filter module for ID filtering. The bit timing unit generates the sampling points required for receiving sampling according to the timing parameters, and sends them to the bit stream processor. The receiving port CANRX receives and retrieves the obtained CANFD frame, and sends it to the bit stream processor for parsing into data, ID value and other information. The received ID value is sent to the receiving filter module, and ID filtering is performed with the configured ID value and mask information to determine whether the CANFD frame needs to be received. If the filtering is successful, the data, ID value and other information are sent to the receiving cache, and the data, ID value and other information in the receiving cache are stored in the corresponding register, and finally the CPU reads the received information.

[0061] For the specific definition of the controller, please refer to the definition of the bit error judgment method for the CANFD frame in the above text, which will not be repeated here. Each module in the above controller can be implemented in whole or in part by software, hardware and their combination. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0062] The present application also provides a communication system, which is a CAN communication system, and its structure can be referred to Figure 1 , including multiple communication nodes, each communication node transmits information through a CANFD bus, each communication node includes a CANFD controller and a CANFD transceiver, wherein the CANFD controller of each communication node is the above-mentioned controller.

[0063] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.10 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a bit error judgment method for a CANFD frame is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0064] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0065] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented: Acquire the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register; The data to be sent and the bit timing parameters are transmitted from the configuration register to the bit stream processor and the bit timing unit in the CANFD core through the transmission buffer respectively; In the bit timing unit in the CANFD core, a sampling point and a sending point are generated according to the bit timing parameters, and the sampling point and the sending point are transmitted to the bit stream processor; In the bit stream processor, a transmission bit is generated according to the data to be transmitted and the transmission point, so as to construct a CANFD frame, and the CANFD frame is output through a transmission port, and the generated transmission bits are sequentially transmitted to an error management unit; The CANFD frame is collected at the receiving port, transmitted to the bit timing unit, a sampling bit is generated according to the sampling point, and then the bit stream processor parses the CANFD frame according to the sampling bit, and transmits the parsing result to the error management unit in sequence; In the error management unit, for the data bits in the high-speed data bit period, the data to be sent is directly obtained from the configuration register, and each data bit in the data to be sent is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

[0066] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: Acquire the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register; The data to be sent and the bit timing parameters are transmitted from the configuration register to the bit stream processor and the bit timing unit in the CANFD core through the transmission buffer respectively; In the bit timing unit in the CANFD core, a sampling point and a sending point are generated according to the bit timing parameters, and the sampling point and the sending point are transmitted to the bit stream processor; In the bit stream processor, a transmission bit is generated according to the data to be transmitted and the transmission point, so as to construct a CANFD frame, and the CANFD frame is output through a transmission port, and the generated transmission bits are sequentially transmitted to an error management unit; The CANFD frame is collected at the receiving port, transmitted to the bit timing unit, a sampling bit is generated according to the sampling point, and then the bit stream processor parses the CANFD frame according to the sampling bit, and transmits the parsing result to the error management unit in sequence; In the error management unit, for the data bits in the high-speed data bit period, the data to be sent is directly obtained from the configuration register, and each data bit in the data to be sent is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

[0067] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0068] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for determining a bit error of a CANFD frame, characterized in that: The method is applied to a CANFD controller, and the method comprises: Acquire the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register; The data to be sent and the bit timing parameters are transmitted from the configuration register to the bit stream processor and the bit timing unit in the CANFD core through the transmission buffer respectively; In the bit timing unit in the CANFD core, a sampling point and a sending point are generated according to the bit timing parameters, and the sampling point and the sending point are transmitted to the bit stream processor; In the bit stream processor, a transmission bit is generated according to the data to be transmitted and the transmission point, so as to construct a CANFD frame, and the CANFD frame is output through a transmission port, and the generated transmission bits are sequentially transmitted to an error management unit; The CANFD frame is collected at the receiving port, transmitted to the bit timing unit, a sampling bit is generated according to the sampling point, and then the bit stream processor parses the CANFD frame according to the sampling bit, and transmits the parsing result to the error management unit in sequence; In the error management unit, for the data bits in the high-speed data bit period, the data to be sent is directly obtained from the configuration register, and each data bit in the data to be sent is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

2. The bit error judgment method according to claim 1, characterized in that: The bit timing parameters are configured via the configuration register; According to the bit timing parameters, the bit timing of the synchronization segment, the Seg1 segment and the Seg2 segment in each data bit in the data to be sent is configured; At the same time, the bit timing of the received samples is configured according to the bit timing parameters, and the boundary between the Seg1 segment and the Seg2 segment is used as the sampling point.

3. The bit error judgment method according to claim 2, characterized in that: In the bit timing unit, the collected CANFD frame generates a sampling bit according to the sampling point, including: For the data bits in the high-speed data bit period, the level value of each received data bit at the sampling point is used as the sampling bit of the data bit.

4. The bit error judgment method according to any one of claims 1 to 3, characterized in that: When bit error judgment is performed in the error management unit: For data bits in a normal bit period, bit errors are determined by comparing the transmitted bit with the sampled bit at the sampling point.

5. The bit error judgment method according to claim 4, characterized in that: In the error management unit, it is also judged whether the received data has a format error, an ACK error, a padding error, or a CRC error.

6. The bit error judgment method according to claim 5, characterized in that: In the bit stream processor: The ID value obtained by parsing the received data is transmitted to the filtering unit; In the filtering unit, ID filtering is performed with the configured ID value and mask information to determine whether the received data needs to be received; If the filtering is successful, the received data is stored in the corresponding register via the receiving buffer.

7. A controller, characterized in that The controller includes a register module, a transmission buffer module, and a CANFD core including a bit timing unit, a bit stream processor and an error management unit; The register module is used to obtain the data to be sent and the bit timing parameters, and store the data to be sent and the bit timing parameters in the configuration register in the register module; The data to be sent and the bit timing parameters are transmitted from the configuration register to the bit stream processor and the bit timing unit in the CANFD core through the transmission buffer module respectively; The bit timing unit is used to generate a sampling point and a sending point according to the bit timing parameter, and transmit the sampling point and the sending point to the bit stream processor; The bit stream processor is used to generate a transmission bit according to the data to be sent and the transmission point, so as to construct a CANFD frame, output the CANFD frame through a transmission port, and transmit the generated transmission bits to the error management unit in sequence; The CANFD frame is collected at the receiving port, transmitted to the bit timing unit, a sampling bit is generated according to the sampling point, and then the bit stream processor parses the CANFD frame according to the sampling bit, and transmits the parsing result to the error management unit in sequence; In the error management unit, for the data bits in the high-speed data bit period, the data to be sent is directly obtained from the configuration register, and each data bit in the data to be sent is compared with the parsing result of the CANFD frame in turn. If there is a difference, it is judged as a bit error.

8. The controller according to claim 7, characterized in that: The controller also includes a receiving filtering module and a receiving buffering module; The bit stream processor transmits the ID value obtained by parsing the received data to the filtering unit; The filtering unit is used to perform ID filtering on the ID value in the received data, the configured ID value and the mask information, and determine whether the received data needs to be received; If the filtering is successful, the received data is stored in the corresponding register in the register module via the receiving buffer module.

9. A communication system, wherein the communication system is a CANFD communication system, comprising a plurality of communication nodes, each of which transmits information via a CAN bus, characterized in that: Each of the communication nodes comprises a CANFD controller and a CANFD transceiver, wherein the CANFD controller of each of the communication nodes is the controller described in claim 8 above.

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