Super junction MOSFET structure, preparation method and MOSFET device
By adopting a super junction cell region and stacked structure with a specific structure in the super junction MOSFET structure, the problems of large channel resistance and poor voltage resistance in the prior art are solved, and MOSFET devices with high efficiency, high blocking voltage and high stability are realized.
CN119730340APending Publication Date: 2025-03-28JINGFENG XINCHI (SHANGHAI) SEMICON TECH CO LTD +2
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Patent Information
- Application Number
- CN202411830461.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-03-28
AI Technical Summary
Technical Problem
The existing super junction MOSFET structure has the defects of large channel resistance and poor voltage resistance.
Method used
The superjunction cell region and a stacked structure are adopted with a specific structure, including alternately arranged trench, drift layer and stacked structure, with a groove angle of 50-60°. The stacked structure consists of a first P-type 4H-SiC layer, an N-type 4H-SiC layer and a second P-type 4H-SiC layer.
Benefits of technology
The super junction MOSFET structure performance is improved, and the MOSFET device produced has low channel resistance, high efficiency, high blocking voltage and high stability in harsh environments.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention relates to a super junction MOSFET structure, a preparation method and an MOSFET device, and relates to the field of semiconductors, the super junction MOSFET structure comprises a substrate, a buffer layer arranged on the substrate, and a super junction cellular region arranged on the buffer layer; the super junction cell region comprises alternately arranged grooves and a drift layer forming the grooves, at least one laminated structure is arranged in each groove, and each laminated structure comprises a P-type 4H-SiC layer, an N-type 4H-SiC layer and a P-type 4H-SiC layer which are sequentially arranged from the bottom of the corresponding groove; the thickness of the N-type 4H-SiC layer is smaller than that of the P-type 4H-SiC layer; the width of the table top of the super junction cellular area is equal to 0, and the angle of the groove is 50-60 degrees. According to the super-junction MOSFET structure provided by the invention, the performance is improved by adopting the super-junction cellular region with a specific structure and the laminated structure, and a manufactured MOSFET device has relatively low channel resistance and high breakdown voltage.
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