Stacked integrated circuit device
By adopting a combined design of multiple nanosheet stacking structures, sheet-shaped separation walls, multiple cladding patterns and gate electrodes in integrated circuit devices, the problem of difficult improvement in the operation characteristics of multi-gate MOSFETs in the prior art is solved, and better charge management and channel performance are achieved.
Patent Information
- Application Number
- CN202410828022.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-25
- Filing Date
- 2024-06-25
- Publication Date
- 2025-03-28
AI Technical Summary
In the process of reducing size and improving integration, existing integrated circuit devices are difficult to further improve performance, especially in terms of the operating characteristics of multi-gate MOSFETs.
An integrated circuit device design including multiple nanosheet stacking structures, sheet-like separation walls, multiple cladding patterns and gate electrodes is adopted. Through the combination of these structures, the operation characteristics of the multi-gate MOSFET are improved.
Through this design, the operation characteristics of integrated circuit devices can be improved, charge traps can be reduced, channel leakage current and effective channel length can be improved, thereby improving overall performance.