Preparation method of solar cell

Abstract

The invention discloses a preparation method of a solar cell, and the method comprises the following steps: providing a silicon substrate which comprises a first surface and a second surface which are oppositely arranged, and the second surface comprises a first region and a second region; preparing a tunneling layer and a second doping layer which are stacked in sequence on the second surface; processing the second doping layer on the first region by adopting a laser process, crystallizing the second doping layer on the first region, and forming an oxide layer on the surface of the second doping layer on the first region; removing the second doping layer on the second region and the oxide layer on the first region by adopting a chemical etching process, and reserving the tunneling layer and the second doping layer on the first region; and preparing a second electrode in contact with the second doped layer on the first region. The passivation effect can be considered, parasitic absorption can be reduced, and the cell efficiency and the double-sided rate are remarkably improved while the process window is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a method for preparing a solar cell. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also constantly increasing, and industry manufacturers have focused on the research and development of high-efficiency batteries. TOPCon (Tunnel Oxide Passivated Contact) cells can improve the surface passivation performance of the cell, reduce the metal contact composite current, and effectively increase the open circuit voltage and short circuit current of the cell by sequentially preparing an ultra-thin tunnel oxide layer and a doped polysilicon layer on the back of the silicon substrate. In recent years, the market share of TOPCon cells has risen rapidly, and has gradually surpassed PERC cells to become the mainstream technology for solar cells.

[0003] The back of the TOPCon cell uses a tunneling oxide layer and a doped polysilicon layer to form a tunneling passivation structure, which significantly increases the cell efficiency. The thicker the doped polysilicon on the back, the larger the window for metal paste burn-through resistance, but the higher the parasitic absorption. Therefore, one of the efficiency-enhancing solutions for TOPCon cells is the back SE structure. By reducing the thickness of doped polysilicon in the non-metallic area, the parasitic absorption of the long-wave band on the back can be reduced, but this requires controlling the thickness of polysilicon in the metal and non-metallic areas.

[0004] If the doped polysilicon in the metal area on the back is too thin, the slurry will penetrate the doped polysilicon during sintering, destroying the underlying tunnel oxide layer, resulting in poor passivation and low battery efficiency; if the doped polysilicon in the non-metal area on the back is too thick, the parasitic absorption is high and the battery efficiency is low; if the doped polysilicon in the non-metal area is too thin, the field passivation effect is poor and the battery efficiency is low. Currently, the thickness of the doped polysilicon layer on the back of mass-produced TOPCon cells is generally between 100nm and 150nm, and it cannot be thinned any further, which is mainly limited by the slurry sintering window.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a method for preparing a solar cell. Summary of the invention

[0006] The object of the present invention is to provide a method for preparing a solar cell to improve the conversion efficiency and bifaciality of the cell.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0008] A method for preparing a solar cell, the method comprising the following steps:

[0009] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region;

[0010] Prepare a tunneling layer and a second doping layer stacked in sequence on the second surface;

[0011] The second doping layer on the first region is processed by a laser process to crystallize the second doping layer on the first region and form an oxide layer on the surface of the second doping layer on the first region;

[0012] Using a chemical etching process, remove at least a portion of the second doped layer on the second region and the oxide layer on the first region, and retain the tunneling layer and the second doped layer on the first region;

[0013] A second electrode contacting the second doping layer is prepared on the first region.

[0014] In one embodiment, the second doped layer before the laser process is a doped amorphous silicon layer. The laser process crystallizes the doped amorphous silicon layer on the first region to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer, and at the same time forms a silicon oxide layer on the surface of the second doped layer on the first region.

[0015] In one embodiment, the laser process is performed in an atmosphere containing oxygen, and the volume concentration of oxygen is 20% to 80%; and / or,

[0016] The laser power in the laser process is 1W to 100W or 30W to 60W; and / or,

[0017] The laser frequency in the laser process is 1kHz to 1000kHz or 300kHz to 600kHz; and / or,

[0018] The laser scanning rate in the laser process is 10000 mm / s to 100000 mm / s or 30000 mm / s to 60000 mm / s; and / or,

[0019] The number of laser processing in the laser process is 1 to 100 times or 1 to 10 times.

[0020] In one embodiment, the silicon oxide layer has a thickness of 1 nm to 50 nm; and / or,

[0021] The doping type of the doped polysilicon layer is the same as the doping type of the silicon substrate, and the surface doping concentration of the doped polysilicon layer is 2E20cm -3 ~3E21cm -3 or 5E20cm -3 ~2E21cm -3 .

[0022] In one embodiment, the doping type of the doped amorphous silicon layer is the same as the doping type of the silicon substrate, and the doped amorphous silicon layer is a single doped amorphous silicon layer or multiple doped amorphous silicon layers with different doping concentrations; and / or,

[0023] The thickness of the doped amorphous silicon layer is 1 nm to 150 nm or 50 nm to 100 nm.

[0024] In one embodiment, the first region includes a plurality of first sub-regions that are distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines that are distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

[0025] In one embodiment, the chemical etching process includes:

[0026] Using the silicon oxide layer as a mask, removing all doped amorphous silicon layers on the second region using an alkaline solution, and then removing the tunneling layer on the second region and the silicon oxide layer on the first region using an acid solution; or,

[0027] Using the silicon oxide layer as a mask, an alkaline solution is used to remove part of the doped amorphous silicon layer on the second region, and then an acid solution is used to remove the silicon oxide layer on the first region.

[0028] In one embodiment, the preparation method further comprises:

[0029] The light trapping structure is prepared on the first surface and the second surface of the silicon substrate by a texturing process; and / or,

[0030] The second surface of the silicon substrate is polished before the tunneling layer and the second doping layer are prepared.

[0031] In one embodiment, the preparation method further comprises:

[0032] preparing a first doping layer at the first surface, wherein the doping type of the first doping layer is opposite to the doping type of the silicon substrate; and,

[0033] A first electrode is prepared on the first surface and in contact with the first doping layer.

[0034] In one embodiment, the preparation method further comprises:

[0035] Prepare a first passivation layer and / or a first anti-reflection layer on the first surface of the silicon substrate;

[0036] A second passivation layer and / or a second anti-reflection layer is prepared on the second surface of the silicon substrate.

[0037] In one embodiment, the first anti-reflection layer and / or the second anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm; and / or,

[0038] The first passivation layer and / or the second passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm.

[0039] In one embodiment, the tunneling layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of both, with a thickness of 1 nm to 3 nm; and / or,

[0040] The first doped layer is formed by a diffusion process or deposited by a PECVD process. The first doped layer is a P-type doped layer with a surface doping concentration of 3E18 cm -3 ~3E19cm -3 and / or,

[0041] The silicon substrate is an N-type silicon substrate.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The preparation process of the SE (Selective Emitter) structure on the back of the battery in the present invention is simple, and the oxidation and crystallization of the first area (metal area) can be completed by a one-step laser process, thereby eliminating the mask making process, annealing process, and front chain process before de-coating in the polysilicon process;

[0044] In addition, the present invention completely removes the doping layer in the second area (non-metal area) on the back of the battery, while the doping layer in the first area (metal area) is not affected. There is no need to change the slurry, and both the passivation effect and the reduction of parasitic absorption can be taken into account, thereby significantly improving the battery efficiency and bifaciality while improving the process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a schematic structural diagram of a solar cell in Example 1 of the present invention;

[0047] Figure 2 for Figure 1 Schematic diagram of the local structure at A in the middle;

[0048] Figure 3 is a schematic plan view of the second surface of the silicon substrate in Example 1 of the present invention;

[0049] Figure 4is a plan view schematically showing the second surface and the second electrode in Example 1 of the present invention;

[0050] Figures 5a to 5j is a process flow chart of preparing a solar cell in Example 1 of the present invention;

[0051] Figure 6 Schematic diagram of a laser scanning pattern in a laser process in Example 1 of the present invention;

[0052] Figure 7 is a schematic structural diagram of a solar cell in Example 2 of the present invention;

[0053] Figure 8 for Figure 7 Schematic diagram of the local structure at B in the middle;

[0054] Figures 9a to 9c This is a process flow chart for preparing a first doping layer on the first surface of a silicon substrate in Example 3 of the present invention.

[0055] Description of main reference numerals:

[0056] 10-substrate, 11-first doped layer, 11'-boron-doped amorphous silicon layer, 21-first passivation layer, 31-first anti-reflection layer, 12-tunneling layer, 13-second doped layer, 131-oxide layer, 22-second passivation layer, 32-second anti-reflection layer, 41-first electrode, 42-second electrode, 421-secondary gate line, S1-first surface, S2-second surface, S21-first region, S22-second region, 101-first sub-region, 102-second sub-region. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0058] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0059] The present invention discloses a method for preparing a solar cell, comprising the following steps:

[0060] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region;

[0061] Prepare a tunneling layer and a second doping layer stacked in sequence on the second surface;

[0062] The second doping layer on the first region is processed by a laser process to crystallize the second doping layer on the first region and form an oxide layer on the surface of the second doping layer on the first region;

[0063] Using a chemical etching process, remove at least a portion of the second doped layer on the second region and the oxide layer on the first region, and retain the tunneling layer and the second doped layer on the first region;

[0064] A second electrode contacting the second doping layer is prepared on the first region.

[0065] Furthermore, the preparation method also includes:

[0066] preparing a first doping layer at the first surface, wherein the doping type of the first doping layer is opposite to the doping type of the silicon substrate; and,

[0067] A first electrode in contact with the first doping is prepared on the first surface.

[0068] The present invention uses a laser process to oxidize the back metal area to form an oxide layer, and uses the instantaneous high temperature of the laser to crystallize the doped layer, and then uses a chemical etching process to remove the doped layer in the back non-metallic area using the oxide layer as a mask. This can take into account both the passivation effect and the reduction of parasitic absorption, thereby significantly improving the battery efficiency and bifaciality while increasing the process window.

[0069] The present invention is further described below in conjunction with specific embodiments.

[0070] Embodiment 1:

[0071] Ginseng Figure 1 The solar cell in this embodiment is a schematic diagram of the structure of the solar cell, which is a TOPCon cell, including a silicon substrate 10, Figure 5a As shown, the silicon substrate 10 includes a first surface S1 and a second surface S2 that are relatively arranged, and the second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0072] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0073] Furthermore, a light trapping structure is formed on the first surface S1 of the silicon substrate 10. For example, a pyramid texture structure can be formed on the first surface S1 of the silicon substrate 10 by alkali texturing, and the size of the pyramid is 0.5 μm to 3 μm.

[0074] In this embodiment, a first doping layer 11 (i.e., an emitter) is formed at the first surface S1 of the silicon substrate 10 by a diffusion process or a PECVD process, thereby forming a PN junction, and generating minority carrier-hole pairs after light exposure. For example, the first doping layer 11 is a P-type doping layer (i.e., a P+ emitter) formed by a boron doping process, and the surface doping concentration is 3E18cm -3 ~3E19cm -3 , square resistance is 40Ω / sq~300Ω / sq, preferably 150Ω / sq~250Ω / sq.

[0075] Ginseng Figure 1 Combined with Figure 2 As shown, in this embodiment, the second surface S2 of the silicon substrate 10 is a polished surface, which can be a surface after chemical polishing of the light trapping structure, or a surface after direct chemical polishing of the back side of the original silicon substrate. For example, in this embodiment, a pyramid velvet structure can be formed on the second surface S2 of the silicon substrate 10 by alkali texturing, and the pyramid size is 0.5μm to 3μm. The back side is then alkali polished to obtain a polished surface. Compared with the back side of a conventional silicon substrate, a plurality of tower bases will be formed on the polished surface (the tower base is the base left after the pyramid velvet structure is polished).

[0076] In this embodiment, a tunneling layer 12 and a second doping layer 13 are sequentially stacked on the first region S21 on the second surface S2 of the silicon substrate 10. The tunneling layer 12 can provide a good interface passivation effect, and the second doping layer 13 can provide a field passivation effect. At the same time, because the doping concentration of this layer is relatively high, the contact can be improved and the resistance can be reduced.

[0077] The tunneling layer 12 is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm; the second doping layer 13 is a phosphorus-doped polysilicon layer, with a surface doping concentration of 2E20 cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3The thickness is 1nm to 150nm, preferably 50nm to 100nm. The thickness of the second doping layer of this embodiment is further reduced, which can reduce parasitic absorption without affecting the metallization contact performance, increase the short-circuit current density of the battery, and significantly improve the battery efficiency and bifaciality.

[0078] Preferably, in this embodiment, a first passivation layer 21 and a first anti-reflection layer 31 are sequentially stacked on the first surface S1 of the silicon substrate 10, and a second passivation layer 22 and a second anti-reflection layer 32 are sequentially stacked on the second surface S2 of the silicon substrate 10, and the second passivation layer 22 and the second anti-reflection layer 32 cover the second doping layer 13 and extend into the second region S22. The first passivation layer 21 can provide excellent field passivation and chemical passivation effects, the second passivation layer 22 can provide a chemical passivation effect, and the first anti-reflection layer 31 can reduce reflectivity and increase light utilization.

[0079] Exemplarily, the first passivation layer 21 and the second passivation layer 22 are both aluminum oxide passivation layers with a thickness of 2nm to 7nm, preferably 3nm to 6nm; the first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm, preferably a silicon nitride layer. Silicon nitride is chemically inactive, has strong acid and alkali corrosion resistance, and can reduce the sensitivity of the battery to the environment.

[0080] In addition, the first electrode 41 in this embodiment is located on the first surface S1 of the silicon substrate 10 and contacts the first doping layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically on the first area S21 in the second surface S2, and contacts the second doping layer 13.

[0081] Ginseng Figure 3 As shown, in this embodiment, the first region S21 includes a plurality of first sub-regions 101 that are parallel and equally spaced, and the second region S22 includes a plurality of second sub-regions 102 that are parallel and equally spaced, and the first sub-regions 101 and the second sub-regions 102 are staggered. The width of the first sub-region 101 is smaller than the width of the second sub-region 102, for example, the ratio of the widths of the two can be 1: (5-20), preferably, the first region S21 occupies about 10% of the area of ​​the entire second surface S2.

[0082] Combination Figure 4 As shown, the second electrode 42 is a gate line electrode, which at least includes a plurality of parallel thin gate lines 421, and the width of the first sub-region 101 is greater than or equal to the width of the thin gate lines 421. Optionally, the second electrode 42 may also include a plurality of main gate lines (not shown) perpendicular to the thin gate lines 421.

[0083] In this embodiment, taking a 210TOPCon battery as an example, the size is 203.396±15mm, there are 230 fine grid lines 421, the width is 15μm to 100μm, and the spacing between adjacent fine grid lines is 0.907±0.015mm. The spacing between adjacent first sub-regions 101 is equal to the spacing between adjacent fine grid lines, and a fine grid line 421 is distributed on each first sub-region 101, and the width of the first sub-region 101 is greater than the width of the fine grid line 421. The width of the first sub-region is 50μm to 150μm, such as the width of the fine grid line is 40μm, and the width of the first sub-region is 80μm.

[0084] The method for preparing a solar cell in this embodiment specifically includes the following steps:

[0085] 1. Double-sided velveting

[0086] Ginseng Figure 5a As shown, a silicon substrate 10 is provided, and the silicon substrate 10 includes a first surface S1 and a second surface S2 that are arranged opposite to each other. The second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0087] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0088] Ginseng Figure 5b As shown, in this embodiment, the first surface S1 and the second surface S2 of the silicon substrate 10 are formed with a pyramid texture structure by an alkali texturing process, and the size of the pyramid is 0.5 μm to 3 μm.

[0089] 2. Boron Diffusion

[0090] Ginseng Figure 5c As shown, a P-type doped first doping layer (i.e., a P+ emitter) 11 is formed at the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, a boron source (e.g., BCl3 or BBr3, etc.) is used in a high-temperature furnace tube for diffusion, and a layer of silicon oxide is formed on the outer layer. After diffusion, the surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 , the square resistance is 40Ω / sq~300Ω / sq, preferably 150Ω / sq~250Ω / sq. In the boron diffusion process, BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0091] In this embodiment, the outer silicon layer of the first surface S1 of the silicon substrate 10 is transformed into a boron diffusion layer. Figure 5c The total thickness of the silicon substrate 10 and the first doping layer 11 after the boron diffusion is Figure 5b The thickness of the silicon substrate 10 before the boron diffusion is uniform.

[0092] 3. Back polishing

[0093] Ginseng Figure 5d As shown, the silicon substrate after boron diffusion is first passed through a single-sided chain device, and a hydrofluoric acid solution is used to remove the back silicon oxide. The back side is then alkaline polished to remove the edge junction and back side wrap (BSG), and finally cleaned.

[0094] 4. Preparation of back-side tunneling passivation structure

[0095] Ginseng Figure 5e As shown, a tunneling layer 12 and a second doping layer 13 stacked in sequence are prepared on the second surface S2.

[0096] Illustratively, in this embodiment, a PECVD process is used to first deposit a 1nm to 3nm thick silicon oxide tunneling layer on the back side, and then deposit a layer of phosphorus-doped amorphous silicon or multiple layers of phosphorus-doped amorphous silicon layers with different doping concentrations, with a total thickness of 1nm to 150nm, preferably 50nm to 100nm.

[0097] 5. Laser oxidation

[0098] Ginseng Figure 5f As shown, the second doping layer 13 on the first region S21 is processed by a laser process, the second doping layer 13 on the first region S21 is crystallized and an oxide layer 131 is formed on the surface of the second doping layer on the first region S21.

[0099] In this embodiment, the second doped layer 13 before the laser process is a phosphorus-doped amorphous silicon layer. The laser process can crystallize the phosphorus-doped amorphous silicon layer on the first region S21, activate phosphorus, and transform the phosphorus-doped amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer; at the same time, the instantaneous high temperature of the laser is used to form silicon oxide (SiO X ) layer, the silicon oxide layer serves as a mask for subsequent processes.

[0100] Specifically, the laser process is carried out in an atmosphere containing oxygen, and the volume concentration of oxygen is 20% to 80%; the laser power is 1W to 100W, preferably 30W to 60W; the laser frequency is 1kHz to 1000kHz, preferably 300kHz to 600kHz; the laser scanning rate is 10000mm / s to 100000mm / s, preferably 30000mm / s to 60000mm / s; the number of laser processing times is 1 to 100 times, preferably 1 to 10 times. The surface doping concentration of the second doping layer 13 after laser processing is 2E20cm-3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 The thickness of the formed oxide layer 131 is 1 nm to 50 nm.

[0101] For example, in a specific embodiment, the volume concentration of oxygen in the laser process is 50%, the laser power is 50 W, the laser frequency is 500 kHz, the laser scanning rate is 50000 mm / s, the number of laser processing times is 2 times, and the surface doping concentration of the phosphorus-doped amorphous silicon layer is 9E20 cm -3 The thickness of the silicon oxide layer formed by oxidation on the surface of the phosphorus-doped amorphous silicon layer is 0.01nm to 10nm.

[0102] Ginseng Figure 6 The figure shows the laser scanning pattern in the laser process of this embodiment. The black line portion corresponds to the laser scanning area, that is, the first area S21 (i.e., the metal area), and the blank portion is the second area S22 (i.e., the non-metal area). After the laser process, the first area S21 is a tunneling layer + phosphorus-doped polysilicon layer + silicon oxide layer structure, and the second area S22 is a tunneling layer + phosphorus-doped amorphous silicon layer structure.

[0103] It should be understood that the laser scanning pattern in the present invention can be designed according to different electrode structures, so as to crystallize the amorphous silicon layer under the laser scanning area (i.e., the back metal area) and form a patterned silicon oxide mask. The laser scanning patterns for other electrode structures will not be illustrated one by one here.

[0104] In the prior art, a doped amorphous silicon layer is usually converted into a doped polysilicon layer by high temperature annealing. At this time, a mask layer needs to be deposited separately by a process such as PECVD, and the mask is patterned. However, the present invention uses a one-step laser process to achieve the conversion of doped amorphous silicon to doped polysilicon and the preparation of a patterned mask, which greatly simplifies the process flow.

[0105] 6. De-plating and chemical etching

[0106] Ginseng Figure 5g As shown, a chemical etching process is used to remove all the second doping layer 13 on the second region S22 and the oxide layer 131 on the first region S21, and the tunneling layer 12 and the second doping layer 13 on the first region S21 are retained.

[0107] This step specifically includes:

[0108] Alkali etching: using an alkaline solution in an alkaline washing tank to remove all the second doping layer 13 on the second region S22, and simultaneously remove the front and edge plating, the mass fraction of the alkaline solution is 3% to 15%, and the processing time is 100s to 500s, preferably 350s;

[0109] Pickling: using an acid solution in a pickling tank to remove the tunneling layer 12 on the second region and the oxide layer 131 on the first region, and simultaneously remove the PSG on the front side, the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s, preferably 300s;

[0110] Finally, RCA cleaning is performed. RCA cleaning is a prior art and will not be described in detail here.

[0111] Preferably, the acid solution in this embodiment is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~40%) and water in a certain proportion, and the alkaline solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~32%) and water in a certain proportion.

[0112] In the prior art, a front chain process (pickling) is usually required before the alkaline etching step, and the silicon oxide mask with edge plating is removed on one side through a chain hydrofluoric acid tank. However, the silicon oxide mask is not prepared by the PECVD process, and no plating is formed on the edge, so there is no need to go through the front chain process.

[0113] During the alkaline etching process, the second doped layer 13 (i.e., the phosphorus-doped amorphous silicon layer) on the second region S22 is corroded, which can reduce the parasitic absorption on the back side of the battery and significantly improve the current. The first region S21 has silicon oxide to block the corrosion of the alkaline solution, thereby not affecting the contact performance between the back electrode and the second doped layer.

[0114] 7. Preparation of passivation layer

[0115] Ginseng Figure 5h As shown, the first passivation layer 21 and the second passivation layer 22 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate by the ALD process. The first passivation layer 21 and the second passivation layer 22 are both aluminum oxide passivation layers with a thickness of 2nm to 7nm, preferably 3nm to 6nm.

[0116] After the de-plating and chemical etching steps, the tunneling layer and the doped polysilicon layer on the first area S21 can still ensure the passivation effect, while there is no passivation layer protection on the second area S22. Therefore, while preparing the first passivation layer 21 on the front side, it is necessary to prepare the second passivation layer 22 on the back side at the same time, so as to ensure a good interface passivation effect on the second area S22.

[0117] In addition, under high-temperature sintering conditions to ensure good front contact, the second passivation layer 22 has a certain barrier effect on the back paste, so the second doping layer 13 can be further thinned, thereby improving the short-circuit current density of the battery.

[0118] 8. Preparation of anti-reflection layer

[0119] Ginseng Figure 5i As shown, a first anti-reflection layer 31 and a second anti-reflection layer 32 are respectively prepared on a first surface S1 and a second surface S2 of a silicon substrate by a PECVD process. The first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0120] 9. Printing metal electrodes

[0121] Ginseng Figure 5j As shown, the first electrode 41 and the second electrode 42 are printed on the front and back sides respectively by screen printing, and then sintering and light injection or electric injection treatment are performed to form ohmic contacts.

[0122] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, and usually include a main gate line and a fine gate line. It is worth noting that since the fine gate line in the second electrode 42 needs to be printed on the first region S21, the width of the first sub-region 101 needs to be greater than the width of the fine gate line 421 in the second electrode 42, so that the fine gate line 421 can be aligned.

[0123] TOPCon batteries can be prepared through the above steps, and finally the battery cells can be tested, sorted and stored.

[0124] Embodiment 2:

[0125] Ginseng Figure 7 The solar cell in this embodiment is a schematic diagram of the structure of the solar cell, which is a TOPCon cell. Figure 8 As shown, the solar cell in this embodiment has a different back structure from the solar cell in Embodiment 1. Specifically, the structures on the first region S21 (metal region) are the same, while the second region S22 (non-metal region) includes a tunneling layer 12, a second doping layer 13, a second passivation layer 22, and a second anti-reflection layer 32 stacked in sequence, but the thickness of the second doping layer 13 on the second region S22 is less than the thickness of the second doping layer 13 on the first region S21.

[0126] The method for preparing the solar cell in this embodiment is similar to that in Embodiment 1, except that the de-plating and chemical etching processes are different in step 6. In this embodiment, a chemical etching process is used to remove a portion of the second doping layer 13 on the second region S22 and the oxide layer 131 on the first region S21, retain the tunneling layer 12 and the second doping layer 13 on the first region S21, and retain the tunneling layer 12 and a portion of the second doping layer 13 on the second region S22.

[0127] This step specifically includes:

[0128] Alkali etching: using an alkaline solution in an alkaline washing tank to remove part of the second doping layer 13 on the second region S22, and removing the front surface and edge plating at the same time. The alkaline etching can achieve the removal of part of the second doping layer 13 by process parameters, such as shortening the alkaline etching time or reducing the mass fraction of the alkaline solution, which will not be described in detail here;

[0129] Pickling: using an acid solution in a pickling tank to remove the oxide layer 131 on the first region and remove the PSG on the front side;

[0130] Finally, RCA cleaning is performed.

[0131] It should be understood that in this embodiment, the second doped layer 13 on the first region S21 is a doped polysilicon layer processed by laser technology, and the portion of the second doped layer 13 retained on the second region S21 is a doped amorphous silicon layer not processed by laser technology.

[0132] In this embodiment, the second doping layer 13 (for example, phosphorus-doped polysilicon layer) on the second region S22 is thinned to reduce parasitic absorption on the back of the battery; the tunneling layer 12 and the second doping layer 13 on the first region S21, and the tunneling layer 12 and part of the second doping layer 13 on the second region S22 are retained, which has little effect on the lateral transmission of the battery. In addition, the corrosion thickness of the second doping layer 13 on the second region S22 is small, and the process requirements for the first region S21 in the alkaline washing tank are low, which can improve the production capacity of the battery cell.

[0133] Embodiment 3:

[0134] The solar cell and the preparation method in this embodiment are substantially the same as those in Embodiment 1, except that the first doping layer 11 in Embodiment 1 is prepared by a boron diffusion process, while the first doping layer 11 in this embodiment is prepared by a PECVD process.

[0135] Specifically, in this embodiment, a boron-doped amorphous silicon layer 11 ′ is first deposited on the first surface S1 by using a PECVD process, and then a first doped layer 11 , ie, a P-type doped polysilicon layer, is formed after high-temperature oxidation annealing.

[0136] Ginseng Figure 9a As shown, firstly, the silicon substrate 10 is double-sided textured, and the texture process is exactly the same as that in Example 1, which will not be described again here.

[0137] Ginseng Figure 9b As shown, a boron-doped amorphous silicon layer 11' is first deposited on the first surface S1 by a PECVD process. Exemplarily, in the PECVD process, N2O is first introduced to form a silicon oxide layer (not shown) on the first surface S1, then SiH4 and trimethyl boron are introduced to form a boron-doped amorphous silicon layer on the silicon oxide layer, and finally N2O is introduced to form a silicon oxynitride mask (not shown).

[0138] Ginseng Fig.9c As shown, finally, a first doped layer 11 is formed by a high temperature oxidation annealing process. The P-type doped amorphous silicon layer can be transformed into a P-type doped polysilicon layer by the high temperature oxidation annealing process.

[0139] Different from the first embodiment, in the present embodiment, a P-type doped polysilicon layer is prepared on the surface of the silicon substrate 10 by a PECVD process and an annealing method, and the thickness of the silicon substrate 10 is constant during this process. Fig.9c After the annealing, the total thickness of the silicon substrate 10 and the first doping layer 11 is equal to Figure 9b The total thickness of the silicon substrate 10 and the boron-doped amorphous silicon layer 11' before annealing is greater than Figure 9a The thickness of the silicon substrate 10 before the PECVD process.

[0140] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0141] The preparation process of the SE (Selective Emitter) structure on the back of the battery in the present invention is simple, and the oxidation and crystallization of the first area (metal area) can be completed by a one-step laser process, thereby eliminating the mask making process, annealing process, and front chain process before de-coating in the polysilicon process;

[0142] In addition, the present invention completely removes the doping layer in the second area (non-metal area) on the back of the battery, while the doping layer in the first area (metal area) is not affected. There is no need to change the slurry, and both the passivation effect and the reduction of parasitic absorption can be taken into account, thereby significantly improving the battery efficiency and bifaciality while improving the process window.

[0143] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0144] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region; Prepare a tunneling layer and a second doping layer stacked in sequence on the second surface; The second doping layer on the first region is processed by a laser process to crystallize the second doping layer on the first region and form an oxide layer on the surface of the second doping layer on the first region; Using a chemical etching process, remove at least a portion of the second doped layer on the second region and the oxide layer on the first region, and retain the tunneling layer and the second doped layer on the first region; A second electrode contacting the second doping layer is prepared on the first region.

2. The preparation method according to claim 1, characterized in that: The second doped layer before the laser process is a doped amorphous silicon layer. The laser process crystallizes the doped amorphous silicon layer on the first region to convert the doped amorphous silicon layer into a doped polysilicon layer, and at the same time forms a silicon oxide layer on the surface of the second doped layer on the first region.

3. The preparation method according to claim 2, characterized in that: The laser process is carried out in an atmosphere containing oxygen, the volume concentration of oxygen being 20% ​​to 80%; and / or, The laser power in the laser process is 1W to 100W or 30W to 60W; and / or, The laser frequency in the laser process is 1kHz to 1000kHz or 300kHz to 600kHz; and / or, The laser scanning rate in the laser process is 10000 mm / s to 100000 mm / s or 30000 mm / s to 60000 mm / s; and / or, The number of laser processing in the laser process is 1 to 100 times or 1 to 10 times.

4. The preparation method according to claim 2, characterized in that: The silicon oxide layer has a thickness of 1 nm to 50 nm; and / or, The doping type of the doped polysilicon layer is the same as the doping type of the silicon substrate, and the surface doping concentration of the doped polysilicon layer is 2E20cm -3 ~3E21cm -3 or 5E20cm -3 ~2E21cm -3 .

5. The preparation method according to claim 2, characterized in that: The doping type of the doped amorphous silicon layer is the same as the doping type of the silicon substrate, and the doped amorphous silicon layer is a single doped amorphous silicon layer or multiple doped amorphous silicon layers with different doping concentrations; and / or, The thickness of the doped amorphous silicon layer is 1 nm to 150 nm or 50 nm to 100 nm.

6. The preparation method according to claim 1, characterized in that: The first region includes a plurality of first sub-regions that are distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines that are distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

7. The preparation method according to claim 2, characterized in that: The chemical etching process comprises: Using the silicon oxide layer as a mask, removing all doped amorphous silicon layers on the second region using an alkaline solution, and then removing the tunneling layer on the second region and the silicon oxide layer on the first region using an acid solution; or, Using the silicon oxide layer as a mask, an alkaline solution is used to remove part of the doped amorphous silicon layer on the second region, and then an acid solution is used to remove the silicon oxide layer on the first region.

8. The preparation method according to claim 1, characterized in that: The preparation method further comprises: The light trapping structure is prepared on the first surface and the second surface of the silicon substrate by a texturing process; and / or, The second surface of the silicon substrate is polished before the tunneling layer and the second doping layer are prepared.

9. The preparation method according to claim 1, characterized in that: The preparation method further comprises: preparing a first doping layer at the first surface, wherein the doping type of the first doping layer is opposite to the doping type of the silicon substrate; and, A first electrode is prepared on the first surface and in contact with the first doping layer.

10. The preparation method according to claim 9, characterized in that: The preparation method further comprises: Prepare a first passivation layer and / or a first anti-reflection layer on the first surface of the silicon substrate; A second passivation layer and / or a second anti-reflection layer is prepared on the second surface of the silicon substrate.

11. The preparation method according to claim 10, characterized in that: The first anti-reflection layer and / or the second anti-reflection layer is a laminated film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm; and / or, The first passivation layer and / or the second passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm.

12. The preparation method according to claim 9, characterized in that: The tunneling layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, and has a thickness of 0.5 nm to 3 nm; and / or, The first doped layer is formed by a diffusion process or deposited by a PECVD process. The first doped layer is a P-type doped layer with a surface doping concentration of 3E18 cm -3 ~3E19cm -3 and / or, The silicon substrate is an N-type silicon substrate.

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