A method for implementing a digital pulse signal counter based on FPGA

Through the digital pulse signal counter based on FPGA, the dual timer alternate operation and signal latch mechanism are adopted, the problems of limited speed and inflexible parameter adjustment in the prior art counter in high-frequency real-time counting are solved, and the counting effect of high precision, stability and fast response is achieved.

CN119743138BActive Publication Date: 2025-09-05CHENGDU UNIVERSITY OF TECHNOLOGY
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Patent Information

Application Number
CN202411681002.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-11-22
Publication Date
2025-09-05
Estimated Expiration
2044-11-22

AI Technical Summary

Technical Problem

The existing pulse signal counters have problems such as limited speed, inflexible parameter adjustment, data conflicts and unstable counting in high-frequency real-time counting, which is difficult to meet the accuracy and flexibility requirements of variable application scenarios.

Method used

The digital pulse signal counter based on FPGA is adopted to optimize signal determination, timer design and data storage mechanism to realize dynamic parameter adjustment and real-time updates, and the alternating operation of dual timers and signal latch mechanism are used to ensure the accuracy and stability of counting.

Benefits of technology

It improves the counting accuracy and flexibility in high-frequency measurement scenarios, enhances the adaptability and stability of the system, and achieves efficient utilization and rapid response of hardware resources.

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Abstract

The present application discloses a method for implementing a digital pulse signal counter based on an FPGA, comprising: receiving continuously input digital pulse signals through the FPGA, the input digital pulse signals entering a signal determination module, and generating an enable signal when the input digital pulse signal exceeds a determination condition of the sum of a baseline value and a threshold value; setting a first timer and a second timer with the same timing period; starting the first timer, and starting the second timer after the first timer completes a timing; starting the first timer again after the second timer completes a timing, and the two methods are operated alternately in sequence; counting the number of enable signals generated inside the FPGA within the timing period of the first timer and storing the count in a first register; storing the counted number of enable signals within the timing period of the second timer in a second register; and accumulating the count value in the first register or the second register to a total counter after each timing period ends, thereby realizing real-time cumulative update of the number of enable signals.
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