A reconfigurable SoC architecture FMCW radar
By employing a reconfigurable SoC architecture in FMCW radar, integrating RF transceiver and baseband signal processing modules into a single chip, the reliability and adaptability issues of existing FMCW radar systems are resolved, achieving a high-resolution, low-power, and flexible radar system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIHANG UNIV
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-12
AI Technical Summary
Existing FMCW radar systems suffer from low reliability and poor convenience due to the lack of integrated solutions, failing to meet the requirements for detection range and accuracy in different application scenarios, and are greatly affected by the supply chain.
The system adopts a reconfigurable SoC architecture, integrating the RF transceiver subsystem and the baseband signal processing subsystem into the chip. It includes an ASIC algorithm processing module, a SoC MCU module, and a SoC peripheral interface module. Information interaction and control are achieved through the SoC bus, realizing the time-domain to frequency-domain conversion and processing of signals.
It improves the structural simplicity, stability, resolution, and applicability of FMCW radar, reduces power consumption, enhances system flexibility and adaptability, and reduces dependence on the supply chain.
Smart Images
Figure CN119758322B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radar technology, specifically to a reconfigurable SoC architecture FMCW radar. Background Technology
[0002] Frequency Modulated Continuous Wave (FMCW) is a radar technology solution characterized by strong anti-interference capabilities, high transmission rate, high resolution, strong penetration, simple system structure, low power consumption, and high security. It can be widely used in rescue, disaster relief, security, and medical monitoring, among other fields, and has a very rich range of applications and a broad market prospect. Current FMCW radar technology solutions mainly involve building radar systems using discrete chips, or, based on a specific application scenario, integrating key modules such as the RF transceiver into the radar system and then using other on-chip modules to build the radar system.
[0003] Currently, the main implementation solutions for FMCW radar technology both domestically and internationally are to build FMCW radar using discrete components, such as the CEM400 product from Huano Starry Sky Technology Co., Ltd., which adopts a multiple-transmit multiple-receive (MIMO) architecture for ultra-wideband radar. It can penetrate non-metallic, low-moisture objects such as brick walls, stone slabs, doors, and concrete walls. However, these products basically use commercially available discrete components to build the FMCW radio frequency front-end transceiver system, resulting in low integration, low reliability, poor convenience, performance dependence on commercially available chips, and susceptibility to supply chain fluctuations. In academic research, the domestic and international academic communities have made some progress in the research of FMCW radar chips. For example, the literature (10.1109 / ISSCC.2019.8662536) uses an on-chip radar transceiver to realize an FMCW radar transceiver chip that meets the UWB standards of multiple countries. However, the integration level of the relevant achievements is not high, and the current research is only designed for specific industry protocols and industry standards. This results in the reconfigurability and compatibility of the relevant FMCW radar systems being very limited, and they cannot meet the different requirements of FMCW radar for core indicators such as detection range and detection accuracy in different application scenarios.
[0004] In summary, while FMCW radar currently has a promising market outlook, the lack of successful integration solutions has resulted in related products failing to meet market expectations in terms of unit cost, adaptability, and, most importantly, reliability. Therefore, the market urgently needs an on-chip FMCW radar system to overcome the aforementioned problems encountered by existing discrete component-based FMCW radar solutions. Summary of the Invention
[0005] This invention provides a reconfigurable SoC architecture FMCW radar to address the problems in the background art.
[0006] To achieve the above objectives, the present invention provides the following technical solution: a reconfigurable SoC architecture FMCW radar, comprising a radio frequency transceiver subsystem and a baseband signal processing subsystem, wherein the radio frequency transceiver subsystem and the baseband signal processing subsystem are electrically connected; the baseband signal processing subsystem includes a chip with an ASIC algorithm processing module, an SoC bus, an SoC microprocessor with an SoC MCU module, and an SoC peripheral interface module; the SoC MCU module is used to control the radio frequency transceiver subsystem and adjust it according to external information of the chip and feedback signals from the radio frequency transceiver subsystem;
[0007] The ASIC algorithm processing module is used to process the time-domain signal output by the RF transceiver subsystem. It converts the time-domain signal into a frequency-domain signal through an algorithm, and can transmit the frequency-domain signal to the SoC MCU module or to an external device via the SoC peripheral interface module for processing and analysis.
[0008] The radio frequency transceiver subsystem includes a receiving channel, a transmitting channel, a frequency synthesizer, and a mixer. The radio frequency transceiver subsystem interacts with various sub-modules inside the chip through the SoC bus. It can drive the operation of the transceiver subsystem according to the control information of the on-chip main control chip and transmit the signals to the ASIC algorithm processing module for processing.
[0009] Furthermore, both the radio frequency transceiver subsystem and the baseband signal processing subsystem are configured with at least one N-channel configuration, where N is an integer greater than or equal to 1.
[0010] Furthermore, the radio frequency transceiver subsystem is directly connected to the ASIC algorithm processing module inside the chip. The ASIC algorithm processing module converts the time-domain signal obtained by the radio frequency transceiver subsystem through mixing into a frequency-domain signal, and transmits the frequency-domain signal to the SoC MCU module for further processing through the SoC bus. The original time-domain signal obtained by mixing and the processed frequency-domain signal can be directly transmitted to the external terminal for further processing through the SoC peripheral interface.
[0011] Furthermore, control commands output by the user terminal or SoC MCU module control the operation of the RF transceiver subsystem via the SoC bus.
[0012] Furthermore, the RF transceiver subsystem architecture is reconfigurable; the transmit channel includes a passive matching network, a power amplifier, and an off-chip antenna.
[0013] Furthermore, the receiving channel includes an off-chip antenna, a low-noise amplifier, a mixer, a transconductance amplifier, a bandpass filter, and an analog-to-digital converter. The mixer can transform the time-domain signal obtained by mixing into two signals with a 90° phase difference, namely the I-channel signal and the Q-channel signal. The two channel signals are respectively input to independent BPF and ADC for filtering, sampling, and signal conversion.
[0014] Furthermore, the frequency synthesizer includes an on-chip crystal oscillator circuit, a chirp signal generator, a phase-locked loop, a matching network, and a power divider;
[0015] The phase-locked loop is used to generate FMCW signals in a specific frequency band for signal transmission in the transmit channel and signal mixing in the receive channel;
[0016] The chirp signal generator generates a sequence of control signals that control the phase-locked loop output with a specific frequency bandwidth and chirp slope based on the control signal. At the start and end of the chirp, the chirp signal generator will feed back the corresponding trigger signal to the baseband signal processing subsystem to ensure that the SoC MCU or off-chip terminal is synchronized with the chirp signal.
[0017] The power divider splits the single FMCW signal generated by the phase-locked loop into two FMCW signals of equal power. One signal is used for signal transmission in the transmitting channel, and the other signal is mixed with the received signal in the receiving channel. The oscillator type used by the frequency synthesizer is reconfigurable.
[0018] Furthermore, it also includes a phase-locked loop architecture for low-quantization-noise chirp signal injection technology in the radio frequency transceiver subsystem, wherein the phase-locked loop includes a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a true fractional divider, and an output buffer.
[0019] The chirp signal generator controls a true fractional frequency divider to generate a corresponding true fractional + integer division ratio via parallel digital signals. The phase-locked loop responds accordingly, changing its frequency in response to the signal generated by the chirp signal generator, thus generating the corresponding FMCW signal.
[0020] Furthermore, the ASIC algorithm processing module includes a retiming unit and a fast Fourier transform unit. The retiming unit receives the start and end trigger signals of the Chirp signal from the RF transceiver subsystem, or receives the start and end trigger signals of the Chirp signal actively controlled by the user terminal or SoC MCU to determine the start time of receiving data from the RF transceiver subsystem, and sends the received data to the FFT unit and the SoC MCU or user terminal, or sends the unretiped raw data to the SoC MCU or user terminal.
[0021] Furthermore, the FFT unit receives data from the retiming unit, converts the time-domain digital signal into a frequency-domain digital signal through FFT, and sends the frequency-domain digital signal to the SoC MCU or user terminal.
[0022] Compared with existing technologies, this invention provides a reconfigurable SoC architecture FMCW radar with the following advantages:
[0023] This reconfigurable SoC architecture FMCW radar integrates the reconfigurable FMCW radar RF transceiver and related data processing modules into a chip through SoC system architecture design. It has the advantages of simple structure, high stability, high resolution, low power consumption and strong applicability. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the overall architecture of a reconfigurable SoC architecture FMCW radar according to the present invention;
[0026] Figure 2 This is a schematic diagram of the radio frequency transceiver subsystem architecture of a reconfigurable SoC architecture FMCW radar according to the present invention;
[0027] Figure 3 This is a schematic diagram of the phase-locked loop architecture for a low-quantization noise chirp signal injection technology for a reconfigurable SoC architecture FMCW radar according to the present invention.
[0028] Figure 4 This is a schematic diagram of the ASIC algorithm processing module of a reconfigurable SoC architecture FMCW radar according to the present invention. Detailed Implementation
[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0030] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0031] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.
[0032] Please see Figure 1-4 This invention discloses a reconfigurable SoC architecture FMCW radar, the architecture including at least N radio frequency transceiver subsystems and at least N baseband signal processing subsystems, where N is an integer greater than or equal to 1; the baseband signal processing subsystem includes at least one chip with an ASIC algorithm processing module, at least one SoC bus, at least one SoC microprocessor module, and at least one SoC peripheral interface module; the SoC microprocessor (MCU) module internally includes an SoC MCU module, the MCU module being used to control the radio frequency transceiver subsystems and to adjust them according to external chip information and feedback signals from the radio frequency transceiver subsystems.
[0033] The ASIC algorithm processing module is used to process the time-domain signal output by the RF transceiver subsystem. It converts the time-domain signal into a frequency-domain signal through an algorithm, and can transmit the frequency-domain signal to the MCU module or to an external device via the SoC peripheral interface module for processing and analysis.
[0034] The radio frequency transceiver subsystem includes at least one receiving channel, at least one transmitting channel, at least one frequency synthesizer, and at least one mixer. The radio frequency transceiver subsystem interacts with the various sub-modules inside the chip through the SoC bus. It can drive the operation of the transceiver subsystem according to the control information of the on-chip main control chip and transmit the signals to the ASIC algorithm processing module for processing.
[0035] like Figure 1 As shown: The FMCW radar SoC includes a radio frequency transceiver subsystem and a baseband signal processing subsystem. This invention employs a radio frequency transceiver subsystem consisting of a multiple-transmitter-multiple-receiver array (MIMO). The radio frequency transceiver subsystem is directly connected to the ASIC algorithm processing module inside the chip. The ASIC algorithm processing module converts the time-domain signal obtained by mixing in the radio frequency transceiver subsystem into a frequency-domain signal, and transmits the frequency-domain signal to the SoC MCU module for further processing via the SoC bus. At the same time, the original time-domain signal obtained by mixing and the processed frequency-domain signal can be directly transmitted to an external terminal for further processing via the SoC peripheral interface, thereby improving the application flexibility of this invention.
[0036] Figure 1Control commands output from the user terminal or SoC MCU can control the operation enable and various operating modes of the RF transceiver subsystem via the SoC bus. It should be noted that... Figure 1 The specific control method is as follows: the control signal controls the operation of the synthesizer, so that the frequency synthesizer generates the target frequency and the target chirp signal, and at the same time the frequency synthesizer feeds back the chirp signal start trigger signal and end trigger signal to the baseband processing subsystem.
[0037] like Figure 2 As shown: This invention also includes an architecture implementation scheme for an RF transceiver subsystem, the architecture of which is reconfigurable; the transmit channel includes a passive matching network, a power amplifier (PA), and an off-chip antenna, using a passive matching network to achieve high in-band flatness; the receive channel includes an off-chip antenna, a low-noise amplifier (LNA), a mixer (MIXER), a transconductance amplifier (TIA), a bandpass filter (BPF), and an analog-to-digital converter (ADC). In this invention, the MIXER can transform the time-domain signal obtained by mixing into two signals with a 90° phase difference, namely the I-channel signal and the Q-channel signal. The two channel signals are respectively input to independent BPF and ADC for filtering, sampling, and signal conversion, thereby achieving high anti-aliasing performance and noise immunity; the frequency synthesizer includes an on-chip crystal oscillator (XO), a chirp generator, a phase-locked loop, a matching network, and a power divider (PD). In this invention, the phase-locked loop is used to generate FMCW signals in a specific frequency band for signal transmission in the transmit channel and signal mixing in the receive channel; the chirp... Gen generates a sequence of control signals that control the PLL output at a specific frequency bandwidth and chirp slope based on the control signals. At the start and end of the chirp, Chirp Gen feeds back corresponding trigger signals to the baseband signal processing subsystem to ensure that the SoC MCU or off-chip terminal can synchronize with the chirp signal. Meanwhile, the PD in this invention divides the FMCW signal generated by the PLL into two FMCW signals with equal power. One of them is used for signal transmission in the transmit channel, and the other is mixed with the received signal in the receive channel.
[0038] Furthermore, the type of oscillator used by the frequency synthesizer can be reconfigured. In a specific embodiment, a ring oscillator with multiple outputs of different phases can be used as the oscillator. The power divider can be omitted when the frequency synthesizer uses a ring oscillator with multiple outputs of different phases.
[0039] The reconfigurability in the RF transceiver subsystem architecture of this invention refers to the reconfigurability of performance indicators such as the output power and matching bandwidth of the transmit channel; the reconfigurability of performance indicators such as the signal gain and filter bandwidth of the receive channel; and the reconfigurability of performance indicators such as the output frequency range, chirp signal slope, and chirp signal waveform of the frequency synthesizer. The advantage of reconfigurability is that it enables this invention to have high adaptability to multiple scenarios. It can autonomously calibrate and adjust the performance indicators of the modules according to the target distance, target size, ambient space size, and ambient temperature of different application scenarios, thereby achieving the best FMCW radar measurement and sensing effect. Performance indicators not mentioned above but that can be autonomously configured by the SoC MCU and off-chip user terminals in this invention are all subject to the reconfigurable concept mentioned in this invention.
[0040] like Figure 3 As shown: This invention also includes a phase-locked loop (PLL) architecture for low quantization noise (Q-Noise) chirp signal injection technology in an RF transceiver subsystem. The PLL of this invention includes a phase-frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), a true-fractional divider (TF-Divider), and an output buffer. The chirp generator module in this invention controls the TF-Divider to generate a corresponding fractional-to-integer division ratio through parallel digital signals. The PLL responds accordingly, thereby changing its frequency to follow the signal generated by the chirp generator, thus generating the corresponding FMCW signal. Since the TF-Divider can generate a true fractional division, the quantization accuracy during chirp signal injection is higher, resulting in lower Q-Noise and higher linearity of the FMCW signal.
[0041] Regarding the TF-Divider mentioned above in this invention, for example, if the present invention needs to generate a frequency division signal corresponding to N+0.3, and if a general frequency divider is used instead of a TF-Divider, that is, a frequency divider that only generates N or N+1 frequency divisions, then in any frequency division, the division ratio, that is, the ratio of the input frequency to the output frequency, is only N or N+1, and its average division ratio over time is N+1. Therefore, the quantization division ratio error generated in any frequency division, that is, the difference between the required division ratio and the actual division ratio, is 0.3 or -0.7, with probabilities of 0.7 and 0.3 respectively. Now, further assuming that the injected signal of this general frequency divider is a uniformly distributed random number sequence, then the mean square error of the division ratio in this frequency division process is:
[0042]
[0043] Further assuming the use of a TF-Divider, and specifically a 6-bit TF-Divider in a certain implementation of this invention, with a minimum division ratio step size of 0.015625, then for the division ratio corresponding to N+0.3, the two closest division ratios of this TF-Divider are 0.296875 and 0.3125, respectively. The corresponding division ratio errors for their occurrence probabilities are 0.003125 or -0.0125, respectively, while their occurrence probabilities are 0.8 and 0.2, respectively. Therefore, the mean square error of the division ratio when using a TF-Divider in this example is:
[0044]
[0045] It can be assumed that the mean square error can be used to quantize the magnitude of the quantization error of the frequency division error. Therefore, it can be further assumed that the TF-Divider proposed in this invention can effectively reduce the quantization noise introduced during FMCW signal injection.
[0046] like Figure 4 As shown, this invention also includes an implementation scheme for an ASIC algorithm processing module in the baseband signal processing subsystem. The ASIC algorithm processing module includes a retiming unit and a Fast Fourier Transform (FFT) unit. The retiming unit receives the start and end trigger signals of the chirp signal from the RF transceiver subsystem, or receives the start and end trigger signals of the chirp signal actively controlled by the user terminal or SoCMCU from the RF transceiver subsystem, thereby determining the start time of data reception from the RF transceiver subsystem and sending the received data to the FFT unit and the SoC MCU or user terminal, or sending the unretiped raw data to the SoC MCU or user terminal. The FFT unit receives data from the retiming unit, converts the time-domain digital signal into a frequency-domain digital signal using FFT, and sends the frequency-domain digital signal to the SoC MCU or user terminal. Using this ASIC algorithm processing module architecture, necessary processing of signals received by the FMCW radar can be performed within the SoC, eliminating the need for data processing chips in existing discrete FMCW radar systems. This not only saves system power consumption and cost but also avoids various problems in data transmission from discrete devices, thereby effectively improving signal processing speed.
[0047] Specifically, in Figure 1 In alternative embodiments, the matching network submodule in the transmit channel described herein may be included inside the transmit channel, thereby implementing the matching network inside the chip.
[0048] Specifically, the SoC microprocessor in the embodiment may need to use certain existing digital IP cores, which may be interchangeable with the digital circuits used in this embodiment.
[0049] Specifically, the baseband signal processing subsystem may be implemented using existing discrete components, such as FPGAs and dedicated digital chips, in alternative embodiments.
[0050] Specifically, the control circuitry for the multiple transmit / receive antenna array may be implemented off-chip in alternative embodiments.
[0051] Specifically, in alternative embodiments, the on-chip crystal oscillator circuit may use the following approach: an off-chip active crystal oscillator chip is used, and the on-chip start-up circuit is no longer designed; only the drive circuit is used.
[0052] In summary, this reconfigurable SoC architecture FMCW radar integrates the reconfigurable FMCW radar RF transceiver and related data processing modules into a chip through SoC system architecture design, and has the advantages of simple structure, high stability, high resolution, low power consumption and strong applicability.
[0053] The on-chip phase-locked loop circuit implementation scheme of this invention has advantages such as reconfigurability, large frequency modulation bandwidth, and high frequency modulation linearity. The on-chip adjustable bandpass filter circuit implementation scheme has advantages such as the ability to adjust the intermediate frequency bandwidth and gain according to the target and scenario. The SoC overall architecture scheme of this invention has advantages such as monolithic integration, high stability, and low mass production cost. The ASIC algorithm architecture scheme of this invention has advantages such as autonomous processing and computation, and efficient interaction.
[0054] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.
[0055] More specific examples (a non-exhaustive list) of computer-readable media include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.
[0056] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0057] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A reconfigurable SoC architecture FMCW radar, comprising a radio frequency transceiver subsystem and a baseband signal processing subsystem, characterized in that: The radio frequency (RF) transceiver subsystem is electrically connected to the baseband signal processing subsystem. The baseband signal processing subsystem includes a chip with an ASIC algorithm processing module, a SoC bus, a SoC microprocessor with an SoC MCU module, and an SoC peripheral interface module. The SoC MCU module controls the RF transceiver subsystem, adjusting it based on external information from the chip and feedback signals from the RF transceiver subsystem. The ASIC algorithm processing module processes the time-domain signal output by the RF transceiver subsystem, converting it into a frequency-domain signal using an algorithm. This frequency-domain signal can be transmitted to the SoC MCU module or, via the SoC peripheral interface module, to an external device for processing and analysis. The RF transceiver subsystem includes a receiving channel, a transmitting channel, a frequency synthesizer, and a mixer. The RF transceiver subsystem interacts with various sub-modules within the chip via the SoC bus, driving its operation based on control information from the on-chip main control chip and transmitting signals to the ASIC algorithm processing module for processing. The frequency synthesizer includes an on-chip crystal oscillator circuit, a chirp signal generator, a phase-locked loop (PLL), a matching network, and a power divider. The PLL generates an FMCW signal in a specific frequency band for signal transmission in the transmit channel and signal mixing in the receive channel. The chirp signal generator generates a sequence of control signals that control the PLL output to a specific frequency bandwidth and chirp slope based on the control signal. At the start and end of the chirp, the chirp signal generator feeds back corresponding trigger signals to the baseband signal processing subsystem to ensure that the SoC MCU or external terminal is synchronized with the chirp signal. The power divider splits the single FMCW signal generated by the phase-locked loop into two FMCW signals of equal power. One signal is used for transmission in the transmit channel, and the other is mixed with the received signal in the receive channel. The oscillator type used by the frequency synthesizer is reconfigurable. The system also includes a phase-locked loop architecture with low-quantization-noise chirp signal injection technology in the RF transceiver subsystem. The phase-locked loop includes a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a true fractional divider, and an output buffer. The chirp signal generator controls the true fractional divider to generate a corresponding fractional-to-integer division ratio via parallel digital signals. The phase-locked loop responds accordingly, changing its frequency to follow the signal generated by the chirp signal generator, thus generating the corresponding FMCW signal.
2. The reconfigurable SoC architecture FMCW radar according to claim 1, characterized in that: Both the radio frequency transceiver subsystem and the baseband signal processing subsystem are configured with at least one N-channel configuration, where N is an integer greater than or equal to 1.
3. The reconfigurable SoC architecture FMCW radar according to claim 1, characterized in that: The radio frequency transceiver subsystem is directly connected to the ASIC algorithm processing module inside the chip. The ASIC algorithm processing module converts the time-domain signal obtained by the radio frequency transceiver subsystem through mixing into a frequency-domain signal, and transmits the frequency-domain signal to the SoC MCU module for further processing through the SoC bus. The original time-domain signal obtained by mixing and the processed frequency-domain signal can be directly transmitted to the external terminal for processing through the SoC peripheral interface.
4. The reconfigurable SoC architecture FMCW radar according to claim 2, characterized in that: Control commands output by the user terminal or SoCMCU module control the operation of the RF transceiver subsystem via the SoC bus.
5. The reconfigurable SoC architecture FMCW radar according to claim 1, characterized in that: The RF transceiver subsystem architecture is reconfigurable; the transmit channel includes a passive matching network, a power amplifier, and an off-chip antenna.
6. The reconfigurable SoC architecture FMCW radar according to claim 5, characterized in that: The receiving channel includes an off-chip antenna, a low-noise amplifier, a mixer, a transconductance amplifier, a bandpass filter, and an analog-to-digital converter. The mixer can transform the time-domain signal obtained by mixing into two signals with a 90° phase difference, namely the I-channel signal and the Q-channel signal. The two channel signals are respectively input to independent BPF and ADC for filtering, sampling, and signal conversion.
7. The reconfigurable SoC architecture FMCW radar according to claim 1, characterized in that: The ASIC algorithm processing module includes a retiming unit and a fast Fourier transform unit. The retiming unit receives the start and end trigger signals of the Chirp signal from the radio frequency transceiver subsystem. It can either receive the start and end trigger signals of the Chirp signal from the user terminal or SoC MCU to actively control the RF transceiver subsystem, determine the start time of receiving data from the RF transceiver subsystem, and send the received data to the FFT unit and the SoC MCU or user terminal, or send the untimed raw data to the SoC MCU or user terminal.
8. A reconfigurable SoC architecture FMCW radar according to claim 7, characterized in that: The FFT unit receives data from the retiming unit, converts the time-domain digital signal into a frequency-domain digital signal through FFT, and sends the frequency-domain digital signal to the SoC MCU or user terminal.