Detection-recognition-communication integrated hardware system based on mercuric chloride processor and FPGA and use method of detection-recognition-communication integrated hardware system based on mercuric chloride processor and FPGA

Abstract

The invention discloses a detection-recognition-communication integrated hardware system based on a mercuric chloride processor and an FPGA and a use method. The detection-recognition-communication integrated hardware system based on the mercuric chloride processor and the FPGA comprises an intelligent data processing subsystem and a signal acquisition and processing subsystem. Wherein the signal acquisition and processing subsystem comprises an FPGA (Field Programmable Gate Array) module and an analog front-end module and is responsible for modulation of detection-communication signals and acquisition, decoding and transmission optimization of echo signals; the intelligent data processing subsystem comprises an Atlas 200I A2 acceleration module and is responsible for analyzing a sonar signal, identifying a sonar image and sending a control command; according to the invention, the problems of insufficient real-time performance and limited data processing capability in a traditional scheme are effectively solved, the intelligent degree and the integration degree of the system are effectively improved, and the system is suitable for being applied to an intelligent underwater detection and communication system in the future.

Description

Technical Field

[0001] The present invention belongs to the technical field of marine acoustic equipment, and specifically relates to a detection-identification-communication integrated hardware system based on Ascend processor and FPGA and a use method thereof. Background Art

[0002] Hydroacoustic control systems refer to systems that are based on hydroacoustic technology and are used to control and adjust the operating status of underwater equipment or systems, perform tasks, or transmit data. Such systems usually rely on the propagation characteristics of sound waves to achieve underwater communication, positioning, navigation, monitoring, and control functions, and are widely used in underwater robots, underwater sonar, deep-sea detection equipment, marine scientific research, military defense, and other fields.

[0003] During underwater propagation, underwater acoustic signals are prone to multipath effects, that is, the same signal reaches the receiving end through different paths, resulting in signal superposition, interference or distortion, affecting the clarity of the signal and the response of the system. The impact of nonlinear effects and multipath propagation is particularly significant in complex water environments, and advanced algorithms and signal processing technologies are required to compensate and correct them. At the same time, underwater acoustic control systems often need to process large amounts of data in real time, especially in applications such as underwater positioning, navigation, communication and control, where the system needs to respond quickly to sensor inputs and execute control instructions. Due to the complexity of the underwater environment, this high real-time requirement places high standards on computing resources, processor performance and hardware design, especially for high-precision sonar positioning and underwater acoustic communication systems, where latency and computing power are key factors.

[0004] Existing single-function underwater acoustic systems still have significant limitations in terms of information acquisition efficiency, target identification accuracy and communication reliability.

[0005] In the prior art, the Ascend 310 series processor is a system on chip (SoC), which contains two types of AI computing engines: AI CPU and AI Core. The AI ​​CPU is used to undertake non-matrix computing, and the AI ​​Core provides neural network computing power. For the Ascend 310B processor, its CPU Core uses the ARM-based TaishanV200M quad-core, with a main frequency of 1.8GHz, supports all the features of the ARMv8.2-A architecture, is responsible for processor control, as well as efficient allocation and scheduling of computing tasks and hardware resources; while the AI ​​Core uses the DaVinci V300 architecture, which includes the matrix multiplication unit 3D Cube, vector computing unit, scalar computing unit and rich on-chip buffers. Its special 3DCube uses elastic Scaledown / multi-core stacking technology to expand the computing architecture from one dimension to three dimensions, and can complete the operation of two 16*16 matrices in one cycle. The computing time and energy consumption are greatly reduced compared to traditional CPUs and GPUs. At the same time, the deep learning of the Da Vinci architecture is full of a large number of matrix operations, and the deployment of networks such as Yolo and CenterNet-Keypoint in the detection sonar image processing has also greatly improved the efficiency. In addition, the Ascend 310B processor also has image processing modules such as GPU, DVPP, ISP, and a variety of low-speed and high-speed interfaces. Therefore, the Ascend 310 series processors are suitable for processing low-speed signals such as sensors and system debugging, and can also receive massive data at multi-channel and high sampling rates from the sonar lower computer. Combined with the complete full-stack software and hardware development platform of the Ascend series processors, system development is convenient and reliable, with low cost and short cycle.

[0006] FPGA, which is also an existing technology, has rich logic resources and can realize true hardware-level parallel processing. For the high real-time requirements in underwater acoustic signal processing, FPGA can efficiently complete the parallel operation of complex algorithms, far exceeding the single-thread performance of traditional CPU or DSP. Summary of the invention

[0007] In response to the above problems, the present invention proposes an integrated detection-identification-communication hardware system based on Ascend processor and FPGA and a usage method. The idea is to combine the Ascend processor's adaptability to various communication protocols and control requirements with the efficient information processing capabilities of FPGA chips in the prior art to achieve rapid response of underwater target detection, accurate target identification, and ensure communication stability and low power consumption.

[0008] In the first aspect, the present invention discloses a detection-recognition-communication integrated hardware system based on Ascend processor and FPGA, comprising an intelligent data processing subsystem and a signal acquisition and processing subsystem; the signal acquisition and processing subsystem is provided with a power supply module;

[0009] The signal acquisition and processing subsystem includes an FPGA module and an analog front-end module, wherein the analog front-end module has a built-in DA module, a TVG module and an amplification and filtering module; the FPGA module transmits the voltage pulse period, pulse width and frequency to the external transmitting board through the transmitting module and drives the external transmitting transducer; the amplification and filtering module of the analog front-end module receives the transducer signal from the external transmitting transducer, filters the transducer signal and transmits it to the TVG module;

[0010] The FPGA module transmits the preset modulation signal to the DA module, and the DA module converts the modulation signal from a digital signal into an electrical signal and transmits it to the TVG module; the TVG module performs gain compensation on the transducer signal according to the modulation signal and transmits it to the AD module, and the AD module converts the transducer signal from an electrical signal into a digital signal and transmits it to the FPGA module via SPI; the FPGA module is respectively connected to the SD card module and the DDR module for bidirectional data transmission, and the echo data, configuration files and logs are stored through the SD card module, and the digital signal data generated by the AD module and the modulation calculation results of the FPGA module are quickly accessed and processed through the DDR module;

[0011] The FPGA module transmits the transducer signal to the intelligent data processing subsystem through the first high-speed bus interface on the signal acquisition and processing subsystem;

[0012] The intelligent data processing subsystem includes an Atlas 200I A2 acceleration module; the Atlas 200I A2 acceleration module receives the transducer signal from the first high-speed bus interface through the second high-speed bus interface set on the intelligent data processing subsystem, parses and encodes and decodes the transducer signal, converts the original data into an image or video stream, and outputs the decoded signal to the Gigabit network communication module; the Gigabit network communication module uploads the decoded signal to an external host computer; the Atlas 200I A2 acceleration module is connected to the SD card module and the debugging interface and performs bidirectional data transmission respectively, stores system parameters and startup data through the SD card module, and accesses the Linux operating system inside the processor through the debugging interface to configure system parameters and protocol drivers.

[0013] More specifically, the second high-speed bus interface includes four PCIe transceiver channels, one of which is connected to the SSD and performs bidirectional data transmission, and stores and backs up the imaging and recognition data; two of which are used for data transmission with the first high-speed bus interface; and one of which is used for data transmission with the Atlas 200I A2 acceleration module.

[0014] More specifically, the Gigabit network communication module has a built-in PHY chip and an RJ45 network port with a transformer.

[0015] More specifically, the Atlas 200I A2 acceleration module has a built-in Da Vinci architecture AI core, GPU module and DVPP module.

[0016] More specifically, the FPGA module contains an FPGA chip; the FPGA chip performs bidirectional data transmission with the crystal oscillator unit, Flash unit, JTAG unit and reset unit as peripheral circuits; the reset unit provides a clock signal, the Flash unit stores configuration files, the JTAG unit implements debugging and configuration of the FPGA chip, and the reset unit can initialize the internal logic of the FPGA. In a second aspect, the present invention discloses a method for using the above-mentioned detection-recognition-communication integrated hardware system based on the Ascend processor and FPGA, and the steps include:

[0017] A. Drive the transmitter board signal modulation;

[0018] A1. The host computer issues a control command, and the intelligent data processing subsystem transmits the data to be sent to the detection - communication signal acquisition and processing subsystem FPGA module through the second high-speed bus interface and the first high-speed bus interface;

[0019] A2. FPGA module scrambles, encodes and interleaves the data to be transmitted, and generates a specific PWM waveform signal according to the detection requirements;

[0020] A3. The FPGA module maps the real and imaginary parts of the interleaved bit data stream into in-phase (I) and quadrature (Q) data signals, and uses QPSK modulation to modulate the I and Q signals onto two mutually orthogonal carriers.

[0021] A4.FPGA module uses block pilots to insert pilot information into the QPSK modulated data frame to facilitate receiver signal synchronization and channel estimation;

[0022] A5. FPGA module performs IFFT processing on the data stream with inserted pilot information, modulates the signal onto each subcarrier, and forms OFDM symbols. s The equivalent baseband signal expression of an OFDM symbol at the beginning is:

[0023]

[0024] Where N is the number of subcarriers, T is the duration of an OFDM symbol, and d i (i=0,1,…,N-1) is the data symbol of each subcarrier, and the rectangular function rect(t)=1;

[0025] A6. The FPGA module divides the OFDM symbol equivalent baseband signal into cyclic prefixes to eliminate inter-symbol interference (ISI) and achieve detection requirements. It retains part of the traditional cyclic prefix to support multipath interference countermeasures, and adds the remaining part to the PWM waveform signal through frequency modulation to achieve detection function.

[0026] A7.FPGA module uses DDS IP core to realize linear frequency modulation signal, and adds the linear frequency modulation signal as frame header information before the OFDM symbol equivalent baseband signal. The real number representation formula of linear frequency modulation signal is:

[0027]

[0028] Where lfm is the real number of the linear frequency modulation signal, T is the pulse width, B is the frequency variation range, and f l is the center frequency, k=B / T is the linear frequency modulation signal slope;

[0029] A8.FPGA module converts the OFDM symbol equivalent baseband signal into an analog signal;

[0030] A9.FPGA module converts the OFDM symbol equivalent baseband signal to radio frequency, sends it to the transmitting board through the transmitting module, and drives the underwater acoustic transducer to emit sound wave signals.

[0031] B. Transducer signal reception and processing;

[0032] B1. The FPGA module transmits the voltage pulse period, pulse width and frequency to the external transmitting board through the transmitting module, thereby driving the external transmitting transducer; the amplifying and filtering module receives the transducer signal from the external transmitting transducer and performs filtering on the amplified signal. Its transfer function (Gain function) is:

[0033]

[0034] Where ω is the angular frequency, ω c is the cutoff frequency of the amplification filter module, ε is the parameter that defines the passband fluctuation, controlling the maximum fluctuation amplitude within the passband, T n (x) is an n-th order Chebyshev polynomial, defined as: T n (x) = cos(ncos -1 (x));

[0035] B2.DA module converts the modulation signal output by FPGA module from digital signal to electrical signal, so as to accurately control TVG module to perform gain compensation on the filtered signal. The gain formula is:

[0036]

[0037] Where VGAIN is the gain control voltage output by the DA chip, R FBK is the feedback resistor, R P and R N is the resistance of the positive and negative terminals of the amplifier input; dB is the preset gain;

[0038] B3. The gain-compensated signal enters the AD module in differential form for analog-to-digital conversion, and the generated digital signal is transmitted to the FPGA module;

[0039] B4. The FPGA module mixes the received digital signal to the baseband, performs downsampling and low-pass filtering, and obtains the baseband I and Q signals. The LFM pilot signal is used to locate the starting position of the OFDM symbol, and a synchronization module is designed separately for the PWM detection signal to locate its starting time through periodic template matching.

[0040] B5.FPGA module uses traditional time reversal processing to aggregate signal delays caused by multipath propagation and reduce inter-symbol interference;

[0041] B6. The FPGA module performs Doppler frequency compensation on the OFDM symbol equivalent baseband signal based on the pilot frequency deviation estimation, and performs reverse compression or reverse expansion on the signal to restore the original signal;

[0042] B7. The FPGA module extracts the PWM signal embedded in the cyclic prefix, performs frequency domain and time domain analysis to obtain imaging data, and passes the payload portion after removing the cyclic prefix to the communication processing module;

[0043] B8.FPGA module uses channel estimation based on pilot signal to equalize the communication signal;

[0044] B9.FPGA module uses FFT to convert the signal from time domain to frequency domain, and completes symbol demodulation, deinterleaving and channel decoding to restore the original communication data;

[0045] C. Detection target classification and identification;

[0046] C1. The FPGA module transmits the imaging data to the Atlas 200I A2 acceleration module through the first high-speed bus interface and the second high-speed bus interface;

[0047] C2. The Atlas 200I A2 acceleration module uses imaging algorithms to analyze the imaging data processed by the FPGA module, and uses the built-in Mali G52 single-core GPU and DVPP module to encode and decode the imaging data to generate real-time imaging sonar detection images;

[0048] The Da Vinci architecture AI core built into the C3.Atlas 200I A2 acceleration module analyzes the real-time imaging sonar detection image, implements the application of relevant algorithms such as target recognition and classification based on deep learning, and stores the imaging data, recognition data, etc. in the SSD through the PCIe transceiver channel of the second high-speed bus interface for backup. The beneficial effects of the present invention are:

[0049] (1) The system computing power has been improved, which can efficiently analyze the target echo data. By deploying AI algorithms, it can realize intelligent functions such as target recognition, classification and tracking, which significantly improves the intelligence level and response speed of target detection.

[0050] (2) The FPGA module can quickly perform signal acquisition and encoding and decoding, ensuring that the processed data can seamlessly interact with external devices through a variety of communication protocols, meeting the communication needs in different scenarios and enhancing the adaptability and scalability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a structural diagram of a detection-recognition-communication integrated hardware system based on Ascend processor and FPGA of the present invention.

[0052] Figure 2 It is a signal modulation flow chart of the driving transmitting board of the present invention.

[0053] Figure 3 It is a flow chart of transducer signal receiving and processing of the present invention. DETAILED DESCRIPTION

[0054] The technical solution of the present invention will be described in more detail below with reference to the accompanying drawings.

[0055] according to Figure 1 , a detection-recognition-communication integrated hardware system based on Ascend processor and FPGA includes an intelligent data processing subsystem and a signal acquisition and processing subsystem; the signal acquisition and processing subsystem is provided with a power supply module;

[0056] The signal acquisition and processing subsystem includes an FPGA module and an analog front-end module, wherein the analog front-end module has a built-in DA module, a TVG module and an amplification and filtering module; the FPGA module transmits the voltage pulse period, pulse width and frequency to the external transmitting board through the transmitting module and drives the external transmitting transducer; the amplification and filtering module of the analog front-end module receives the transducer signal from the external transmitting transducer, filters the transducer signal and transmits it to the TVG module;

[0057] The FPGA module transmits the preset modulation signal to the DA module, and the DA module converts the modulation signal from a digital signal into an electrical signal and transmits it to the TVG module; the TVG module performs gain compensation on the transducer signal according to the modulation signal and transmits it to the AD module, and the AD module converts the transducer signal from an electrical signal into a digital signal and transmits it to the FPGA module via SPI; the FPGA module is respectively connected to the SD card module and the DDR module for bidirectional data transmission, and the echo data, configuration files and logs are stored through the SD card module, and the digital signal data generated by the AD module and the modulation calculation results of the FPGA module are quickly accessed and processed through the DDR module;

[0058] The FPGA module transmits the transducer signal to the intelligent data processing subsystem through the first high-speed bus interface on the signal acquisition and processing subsystem;

[0059] The intelligent data processing subsystem includes an Atlas 200I A2 acceleration module; the Atlas 200I A2 acceleration module receives the transducer signal from the first high-speed bus interface through the second high-speed bus interface set on the intelligent data processing subsystem, parses and encodes and decodes the transducer signal, converts the original data into an image or video stream, and outputs the decoded signal to the Gigabit network communication module; the Gigabit network communication module uploads the decoded signal to an external host computer; the Atlas 200I A2 acceleration module is connected to the SD card module and the debugging interface and performs bidirectional data transmission respectively, stores system parameters and startup data through the SD card module, and accesses the Linux operating system inside the processor through the debugging interface to configure system parameters and protocol drivers.

[0060] More specifically, the second high-speed bus interface includes four PCIe transceiver channels, one of which is connected to the SSD and performs bidirectional data transmission, and stores and backs up the imaging and recognition data; two of which are used for data transmission with the first high-speed bus interface; and one of which is used for data transmission with the Atlas 200I A2 acceleration module.

[0061] More specifically, the Gigabit network communication module has a built-in PHY chip and an RJ45 network port with a transformer.

[0062] More specifically, the Atlas 200I A2 acceleration module has a built-in Da Vinci architecture AI core, GPU module and DVPP module.

[0063] More specifically, the FPGA module contains an FPGA chip; the FPGA chip performs bidirectional data transmission with the crystal oscillator unit, Flash unit, JTAG unit and reset unit as peripheral circuits; the reset unit provides a clock signal, the Flash unit stores configuration files, the JTAG unit implements debugging and configuration of the FPGA chip, and the reset unit can initialize the internal logic of the FPGA. In a second aspect, the present invention discloses a method for using the above-mentioned detection-recognition-communication integrated hardware system based on the Ascend processor and FPGA, and the steps include:

[0064] A. Drive the transmitter board signal modulation, such as Figure 2 As shown;

[0065] A1. The host computer issues a control command, and the intelligent data processing subsystem transmits the data to be sent to the detection - communication signal acquisition and processing subsystem FPGA module through the second high-speed bus interface and the first high-speed bus interface;

[0066] A2. The FPGA module scrambles, encodes, and interleaves the data to be transmitted, i.e., preprocesses the data, and generates a specific PWM waveform signal according to the detection requirements;

[0067] A3. The FPGA module maps the real and imaginary parts of the interleaved bit data stream into in-phase (I) and quadrature (Q) data signals, and uses QPSK modulation to modulate the I and Q signals onto two mutually orthogonal carriers.

[0068] A4.FPGA module uses block pilots to insert pilot information into the QPSK modulated data frame to facilitate receiver signal synchronization and channel estimation;

[0069] A5. FPGA module performs IFFT processing on the data stream with inserted pilot information, modulates the signal onto each subcarrier, and forms OFDM symbols. s The equivalent baseband signal expression of an OFDM symbol at the beginning is:

[0070]

[0071] Where N is the number of subcarriers, T is the duration of an OFDM symbol, and d i (i=0,1,…,N-1) is the data symbol of each subcarrier, and the rectangular function rect(t)=1;

[0072] A6. The FPGA module divides the OFDM symbol equivalent baseband signal into cyclic prefixes to eliminate inter-symbol interference (ISI) and achieve detection requirements. It retains part of the traditional cyclic prefix to support multipath interference countermeasures, and adds the remaining part to the PWM waveform signal through frequency modulation to achieve detection function.

[0073] A7.FPGA module uses DDS IP core to realize linear frequency modulation signal, and adds the linear frequency modulation signal as frame header information before the OFDM symbol equivalent baseband signal. The real number representation formula of linear frequency modulation signal is:

[0074]

[0075] Where lfm is the real number of the linear frequency modulation signal, T is the pulse width, B is the frequency variation range, and f l is the center frequency, k=B / T is the linear frequency modulation signal slope;

[0076] A8.FPGA module converts the OFDM symbol equivalent baseband signal into an analog signal;

[0077] A9.FPGA module converts the OFDM symbol equivalent baseband signal to radio frequency, sends it to the transmitting board through the transmitting module, and drives the underwater acoustic transducer to emit sound wave signals.

[0078] B. Transducer signal reception and processing, such as Figure 3 As shown;

[0079] B1. The FPGA module transmits the voltage pulse period, pulse width and frequency to the external transmitting board through the transmitting module, thereby driving the external transmitting transducer; the amplifying and filtering module receives the transducer signal from the external transmitting transducer and performs filtering on the amplified signal. Its transfer function (Gain function) is:

[0080]

[0081] Where ω is the angular frequency, ω c is the cutoff frequency of the amplification filter module, ε is the parameter that defines the passband fluctuation, controlling the maximum fluctuation amplitude within the passband, T n (x) is an n-th order Chebyshev polynomial, defined as: T n (x) = cos(ncos -1 (x));

[0082] B2.DA module converts the modulation signal output by FPGA module from digital signal to electrical signal, so as to accurately control TVG module to perform gain compensation on the filtered signal. The gain formula is:

[0083]

[0084] Where V GAIN is the gain control voltage output by the DA chip, R FBK is the feedback resistor, R P and R Nis the resistance of the positive and negative terminals of the amplifier input; dB is the preset gain;

[0085] B3. The gain-compensated signal enters the AD module in differential form for analog-to-digital conversion, and the generated digital signal is transmitted to the FPGA module;

[0086] B4. The FPGA module mixes the received digital signal to the baseband, performs downsampling and low-pass filtering, and obtains the baseband I and Q signals. The LFM pilot signal is used to locate the starting position of the OFDM symbol, and a synchronization module is designed separately for the PWM detection signal to locate its starting time through periodic template matching.

[0087] B5.FPGA module uses traditional time reversal processing to aggregate signal delays caused by multipath propagation and reduce inter-symbol interference;

[0088] B6. The FPGA module performs Doppler frequency compensation on the OFDM symbol equivalent baseband signal based on the pilot frequency deviation estimation, and performs reverse compression or reverse expansion on the signal to restore the original signal;

[0089] B7. The FPGA module extracts the PWM signal embedded in the cyclic prefix, performs frequency domain and time domain analysis to obtain imaging data, and passes the payload portion after removing the cyclic prefix to the communication processing module;

[0090] B8.FPGA module uses channel estimation based on pilot signal to equalize the communication signal;

[0091] B9.FPGA module uses FFT to convert the signal from time domain to frequency domain, and completes symbol demodulation, deinterleaving and channel decoding to restore the original communication data;

[0092] C. Detection target classification and identification;

[0093] C1. The FPGA module transmits the imaging data to the Atlas 200I A2 acceleration module through the first high-speed bus interface and the second high-speed bus interface;

[0094] C2. The Atlas 200I A2 acceleration module uses imaging algorithms to analyze the imaging data processed by the FPGA module, and uses the built-in Mali G52 single-core GPU and DVPP module to encode and decode the imaging data to generate real-time imaging sonar detection images;

[0095] The Da Vinci architecture AI core built into the C3.Atlas 200I A2 acceleration module analyzes the real-time imaging sonar detection images, implements the application of related algorithms such as target recognition and classification based on deep learning, and stores the imaging data, recognition data, etc. in the SSD through the PCIe transceiver channel of the second high-speed bus interface for backup.

[0096] The beneficial effects of the present invention are:

[0097] (1) The system computing power has been improved, which can efficiently analyze the target echo data. By deploying AI algorithms, it can realize intelligent functions such as target recognition, classification and tracking, which significantly improves the intelligence level and response speed of target detection.

[0098] (2) The FPGA module can quickly perform signal acquisition and encoding and decoding, ensuring that the processed data can seamlessly interact with external devices through a variety of communication protocols, meeting the communication needs in different scenarios and enhancing the adaptability and scalability of the system.

[0099] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A detection-recognition-communication integrated hardware system based on Ascend processor and FPGA, characterized by: It includes an intelligent data processing subsystem and a signal acquisition and processing subsystem; the signal acquisition and processing subsystem is provided with a power supply module; The signal acquisition and processing subsystem includes an FPGA module and an analog front-end module, wherein the analog front-end module has a built-in DA module, a TVG module and an amplification and filtering module; the FPGA module transmits the voltage pulse period, pulse width and frequency to the external transmitting board through the transmitting module and drives the external transmitting transducer; the amplification and filtering module of the analog front-end module receives the transducer signal from the external transmitting transducer, filters the transducer signal and transmits it to the TVG module; The FPGA module transmits the preset modulation signal to the DA module, and the DA module converts the modulation signal from a digital signal into an electrical signal and transmits it to the TVG module; the TVG module performs gain compensation on the transducer signal according to the modulation signal and transmits it to the AD module, and the AD module converts the transducer signal from an electrical signal into a digital signal and transmits it to the FPGA module via SPI; the FPGA module is respectively connected to the SD card module and the DDR module for bidirectional data transmission, and the echo data, configuration files and logs are stored through the SD card module, and the digital signal data generated by the AD module and the modulation calculation results of the FPGA module are quickly accessed and processed through the DDR module; The FPGA module transmits the transducer signal to the intelligent data processing subsystem through the first high-speed bus interface on the signal acquisition and processing subsystem; The intelligent data processing subsystem includes an Atlas 200IA2 acceleration module; the Atlas 200IA2 acceleration module receives the transducer signal from the first high-speed bus interface through the second high-speed bus interface set on the intelligent data processing subsystem, parses and encodes and decodes the transducer signal, converts the original data into an image or video stream, and outputs the decoded signal to the Gigabit network communication module; the Gigabit network communication module uploads the decoded signal to an external host computer; the Atlas 200IA2 acceleration module connects the SD card module and the debugging interface and performs two-way data transmission respectively, stores system parameters and startup data through the SD card module, and accesses the Linux operating system inside the processor through the debugging interface to configure system parameters and protocol drivers.

2. The detection-recognition-communication integrated hardware system based on Ascend processor and FPGA according to claim 1, characterized in that: The second high-speed bus interface includes four PCIe transceiver channels, one of which is connected to the SSD for bidirectional data transmission and storage backup of imaging and recognition data; two of which are used for data transmission with the first high-speed bus interface; and one of which is used for data transmission with the Atlas 200IA2 acceleration module.

3. The detection-recognition-communication integrated hardware system based on Ascend processor and FPGA according to claim 1, characterized in that: The Gigabit Ethernet communication module has a built-in PHY chip and an RJ45 network port with a transformer.

4. The detection-recognition-communication integrated hardware system based on Ascend processor and FPGA according to claim 1, characterized in that: The Atlas 200IA2 acceleration module has built-in Da Vinci architecture AI core, GPU module and DVPP module.

5. The detection-recognition-communication integrated hardware system based on Ascend processor and FPGA according to claim 1, characterized in that: The FPGA module contains an FPGA chip, which performs bidirectional data transmission with the crystal oscillator unit, Flash unit, JTAG unit and reset unit as peripheral circuits; the reset unit provides clock signals, the Flash unit stores configuration files, the JTAG unit implements debugging and configuration of the FPGA chip, and the reset unit can initialize the internal logic of the FPGA.

6. The method for using the detection-recognition-communication integrated hardware system based on Ascend processor and FPGA according to claim 1, wherein the steps include: A. Drive the transmitter board signal modulation; A1. The host computer issues a control command, and the intelligent data processing subsystem transmits the data to be sent to the detection - communication signal acquisition and processing subsystem FPGA module through the second high-speed bus interface and the first high-speed bus interface; A2. FPGA module scrambles, encodes and interleaves the data to be transmitted, and generates a specific PWM waveform signal according to the detection requirements; A3. The FPGA module maps the real and imaginary parts of the interleaved bit data stream into in-phase (I) and quadrature (Q) data signals, and uses QPSK modulation to modulate the I and Q signals onto two mutually orthogonal carriers. A4.FPGA module uses block pilots to insert pilot information into the QPSK modulated data frame to facilitate receiver signal synchronization and channel estimation; A5. FPGA module performs IFFT processing on the data stream with inserted pilot information, modulates the signal onto each subcarrier, and forms OFDM symbols. s The equivalent baseband signal expression of an OFDM symbol at the beginning is: Where N is the number of subcarriers, T is the duration of an OFDM symbol, and d i (i=0,1,…,N-1) is the data symbol of each subcarrier, and the rectangular function rect(t)=1; A6. The FPGA module divides the OFDM symbol equivalent baseband signal into cyclic prefixes to eliminate inter-symbol interference (ISI) and achieve detection requirements. It retains part of the traditional cyclic prefix to support multipath interference countermeasures, and adds the remaining part to the PWM waveform signal through frequency modulation to achieve detection function. A7.FPGA module uses DDS IP core to realize linear frequency modulation signal, and adds the linear frequency modulation signal as frame header information before the OFDM symbol equivalent baseband signal. The real number representation formula of linear frequency modulation signal is: Where lfm is the real number of the linear frequency modulation signal, T is the pulse width, B is the frequency variation range, and f l is the center frequency, k=B / T is the slope of the linear frequency modulation signal; A8.FPGA module converts the OFDM symbol equivalent baseband signal into an analog signal; A9. The FPGA module converts the OFDM symbol equivalent baseband signal to radio frequency, sends it to the transmitting board through the transmitting module, and drives the underwater acoustic transducer to emit sound wave signals. B. Transducer signal reception and processing; B1. The FPGA module transmits the voltage pulse period, pulse width and frequency to the external transmitting board through the transmitting module, thereby driving the external transmitting transducer; the amplifying and filtering module receives the transducer signal from the external transmitting transducer and performs filtering on the amplified signal. Its transfer function (Gain function) is: Where ω is the angular frequency, ω c is the cutoff frequency of the amplification filter module, ε is the parameter that defines the passband fluctuation, controlling the maximum fluctuation amplitude within the passband, T n (x) is an n-th order Chebyshev polynomial, defined as: T n (x) = Cos(ncos -1 (x)); B2.DA module converts the modulation signal output by FPGA module from digital signal to electrical signal, so as to accurately control TVG module to perform gain compensation on the filtered signal. The gain formula is: Where V GAIN is the gain control voltage output by the DA chip, R FBK is the feedback resistor, R P and R N is the resistance of the positive and negative terminals of the amplifier input; dB is the preset gain; B3. The gain-compensated signal enters the AD module in differential form for analog-to-digital conversion, and the generated digital signal is transmitted to the FPGA module; B4. The FPGA module mixes the received digital signal to the baseband, performs downsampling and low-pass filtering, and obtains the baseband I and Q signals. The LFM pilot signal is used to locate the starting position of the OFDM symbol, and a synchronization module is designed separately for the PWM detection signal to locate its starting time through periodic template matching. B5.FPGA module uses traditional time reversal processing to aggregate signal delays caused by multipath propagation and reduce inter-symbol interference; B6. The FPGA module performs Doppler frequency compensation on the OFDM symbol equivalent baseband signal based on the pilot frequency deviation estimation, and performs reverse compression or reverse expansion on the signal to restore the original signal; B7. The FPGA module extracts the PWM signal embedded in the cyclic prefix, performs frequency domain and time domain analysis to obtain imaging data, and passes the payload portion after removing the cyclic prefix to the communication processing module; B8.FPGA module uses channel estimation based on pilot signal to equalize the communication signal; B9.FPGA module uses FFT to convert the signal from time domain to frequency domain, and completes symbol demodulation, deinterleaving and channel decoding to restore the original communication data; C. Detection target classification and identification; C1. The FPGA module transmits the imaging data to the Atlas200IA2 acceleration module through the first high-speed bus interface and the second high-speed bus interface; C2. The Atlas 200IA2 acceleration module uses the imaging algorithm to analyze the imaging data processed by the FPGA module, and uses the built-in MaliG52 single-core GPU and DVPP module to encode and decode the imaging data to generate real-time imaging sonar detection images; The Da Vinci architecture AI core built into the C3.Atlas 200IA2 acceleration module analyzes the real-time imaging sonar detection images, implements the application of related algorithms such as target recognition and classification based on deep learning, and stores the imaging data, recognition data, etc. in the SSD for backup through the PCIe transceiver channel of the second high-speed bus interface.

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