Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device. The display panel comprises pixels arranged in an array, data lines corresponding to pixel columns and scanning lines corresponding to pixel rows, and the scanning lines are arranged in the row direction; each scanning line is configured to output a write-in level signal in a time-sharing manner in a data write-in stage of the corresponding pixel row, so that the pixels of the pixel row write in data signals output by the data lines corresponding to the pixels of the pixel row in different time-sharing periods; therefore, for each pixel row, when the scanning line outputs the write-in level signal in a time-sharing manner, the pixel in each pixel row can directly write in the required data signal, pre-charging is not needed, and the influence of jumping of the next data signal on the previous data signal is avoided.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] With the advent of the era of full-screen design, in order to pursue process and cost, the number of PIN pins of IC in display panel is often reduced. After the number of PIN pins of IC is reduced, MUX circuit is often needed to realize the multiplexing of source drive signal.

[0003] In actual applications, it is found that due to the introduction of the MUX circuit, the pixel circuit in the display panel usually adopts a pre-charge or partial direct charge method to write data signals during the data writing stage. This is easily interfered by other jump signals, thereby reducing the screen quality. Summary of the invention

[0004] In order to solve the above problems, the inventors found the causes of the problems through research and development and formed solutions.

[0005] In a first aspect, the present invention provides a display panel, characterized by comprising:

[0006] Pixels arranged in an array, comprising a plurality of pixel rows and a plurality of pixel columns, wherein the plurality of pixel columns are divided into a plurality of pixel groups in a column direction;

[0007] A data line corresponding to each pixel column, wherein the data lines are arranged along a column direction;

[0008] A scan line corresponding to each pixel row, wherein the scan lines are arranged along a row direction;

[0009] Wherein, each scan line is configured to output a write level signal in a time-sharing manner during the data writing phase of the corresponding pixel row, so that the pixels of the pixel row write the data signals output by the data line corresponding to the pixels of the pixel row in different time-sharing periods; wherein the number of the time-sharing periods is determined according to the number of pixel columns in the pixel group in the column direction or the number of pixel groups in the column direction.

[0010] Furthermore, in the above display panel,

[0011] At least two sequentially adjacent pixel columns are divided into a pixel group in a column direction;

[0012] The number of the time division periods is the same as the number of pixel columns in each column-directional pixel group.

[0013] Furthermore, in the above display panel,

[0014] There is no overlapping time period between each of the time-sharing time periods, and the total duration of all the time-sharing time periods approaches the refresh time of each pixel row.

[0015] Furthermore, in the above display panel,

[0016] The odd-numbered pixel columns are divided into an odd-numbered pixel group in a column direction, and the even-numbered pixel columns are divided into an even-numbered pixel group in a column direction;

[0017] The number of the time-division periods and the number of the pixel groups in the column direction are both 2.

[0018] Furthermore, in the above display panel,

[0019] The display panel further includes a first gating circuit and a second gating circuit;

[0020] The first gating circuit is configured to select pixels of the even pixel group to write data signals;

[0021] The second gating circuit is configured to select pixels of the odd pixel group to write data signals.

[0022] Furthermore, in the above display panel,

[0023] The data lines include odd data lines and even data lines, wherein the odd data lines are connected to odd pixels in the pixel column, and the even data lines are connected to even pixels in the pixel column;

[0024] The display panel further includes a first gating circuit, a second gating circuit, a third gating circuit and a fourth gating circuit;

[0025] The first gating circuit is configured to select pixels in odd pixel rows in the even pixel group to write data signals to the odd data lines;

[0026] The third gating circuit is configured to select pixels in even pixel rows in the even pixel group to write data signals to the even data lines;

[0027] The second gating circuit is configured to select pixels in odd pixel rows in the odd pixel group to write data signals to the odd data lines;

[0028] The fourth gating circuit is configured to select pixels in even pixel rows in the odd pixel group to write data signals to the even data lines.

[0029] Furthermore, in the above display panel,

[0030] There is an overlapping time period between the two time-sharing time periods, and each of the time-sharing time periods is close to the refresh time of each pixel row.

[0031] Furthermore, in the above display panel,

[0032] The pixel circuit corresponding to the pixel includes a writing transistor and a compensation transistor;

[0033] The scanning line includes a plurality of sub-scanning lines which are equal in number to the time-sharing periods;

[0034] The plurality of sub-scan lines are all located on the same side of the gate of the write transistor and the gate of the compensation transistor, or at least two of the plurality of sub-scan lines are located on different sides of the gate of the write transistor and the gate of the compensation transistor.

[0035] In a second aspect, the present invention provides a method for driving a display panel as described in any one of the above, characterized by comprising:

[0036] In the data writing phase of each pixel row, the corresponding scanning line is controlled to output the writing level signal in time division, so that the pixels of the pixel row are written with the data signal output by the data line corresponding to the pixels of the pixel row in different time division periods;

[0037] The number of the time-division periods is determined according to the number of pixel columns in the pixel group in the column direction or the number of pixel groups in the column direction.

[0038] In a third aspect, the present invention provides a display device, comprising any one of the display panels described above.

[0039] The above one or more technical solutions of the present invention have at least one or more of the following beneficial effects:

[0040] When implementing the technical solution of the present invention, by dividing a plurality of pixel columns into a plurality of pixel groups in the column direction, and determining the time-sharing period for writing data in each pixel row according to the number of pixel columns in the pixel group in the column direction or the number of pixel groups in the column direction, in this way, in the data writing stage, the scanning line corresponding to each pixel row can be controlled to output the writing level signal in time-sharing, so that the pixels of the pixel row write the data signal output by the data line corresponding to the pixels of the pixel row in different time-sharing periods. In this way, for each pixel row, when the scanning line outputs the writing level signal in time-sharing, the pixels in each pixel row can directly write the required data signal without precharging, thereby avoiding the influence of the jump of the latter data signal on the previous data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The disclosure of the present invention will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In addition, similar numbers in the drawings are used to represent similar components, wherein:

[0042] Figure 1 It is a schematic diagram of pixel arrangement of a display panel;

[0043] Figure 2 yes Figure 1 A schematic diagram of a power supply method for a display panel shown;

[0044] Figure 3 yes Figure 1 A driving timing control diagram of the display panel shown;

[0045] Figure 4 is a structural schematic diagram of a display panel of the present invention;

[0046] Figure 5 It is another schematic diagram of pixel arrangement of a display panel;

[0047] Figure 6 yes Figure 5 A driving timing control diagram of the display panel shown;

[0048] Figure 7 It is a circuit diagram of a pixel circuit in a display panel;

[0049] Figure 8 It is another schematic diagram of pixel arrangement of a display panel;

[0050] Fig. 9 yes Figure 8 A driving timing control diagram of the display panel shown;

[0051] Fig.10 It is another pixel arrangement schematic diagram of a display panel;

[0052] Fig.11 yes Fig.10 A driving timing control diagram of the display panel shown;

[0053] Fig.12 yes Figure 2 Another timing control diagram of the display panel under the power supply mode;

[0054] Fig.13 yes Figure 1 A schematic diagram of another power supply method for the display panel shown;

[0055] Fig.14 yes Fig.13 Another timing control diagram of the display panel under the power supply mode;

[0056] Fig.15 is based on Fig.10 A layout structure of the display panel shown;

[0057] Fig.16 is a schematic diagram of a display device of the present invention;

[0058] Fig.17 is another schematic diagram of the display device of the present invention;

[0059] Fig.18 is another schematic diagram of the display device of the present invention. DETAILED DESCRIPTION

[0060] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0061] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, in the present invention, unless otherwise clearly specified and defined, the terms "connected", "connected", and the like should be understood in a broad sense. For example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0062] In the description of the present invention, the transistors used in the circuits provided in the embodiments may be thin film transistors, field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples. The control terminal of any transistor mentioned is the gate of the transistor, the first terminal of any transistor is one of the source and drain of the transistor, and the second terminal of any transistor is the other of the source and drain of the transistor.

[0063] In the description of the present invention, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. For another example, the term "coupled" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0064] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0065] As used herein, "about," "substantially," "approximately," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0066] With the advent of the era of full-screen design, after the number of PIN pins in IC is reduced, it is often necessary to introduce a MUX circuit to achieve multiplexing of source drive signals. However, the pixel circuit in the display panel usually uses pre-charging or partial direct charging to write data signals during the data writing stage, which is easily interfered by other jump signals, thereby reducing the screen quality.

[0067] Specifically, Figure 1 It is a pixel arrangement diagram of a display panel. Figure 2 yes Figure 1 A schematic diagram of a power supply method for a display panel is shown. Figure 3 yes Figure 1 A driving timing control diagram of the display panel shown in FIG. Figures 1 to 3 , the four data lines in the display panel are marked as Date1 to Date4 in sequence, and the pixel columns of the display panel are selected by two MUX circuits, marked as MUX1 and MUX2, where MUX1 selects the even pixel columns to write data, and MUX2 selects the cardinal pixel columns to write data. The pixel arrangement of the odd pixel rows is RG1BG2, and the pixel arrangement of the even pixel rows is BG2RG1. Figure 3As shown, the conventional writing method in the data writing stage is: for each pixel row, MUX1 controls the corresponding transistor to turn on, and the data signal dateG1G2 corresponding to the G1G2 pixel (wherein the data signal dateG1G2 is provided by the source driving circuit source1 and the source driving circuit source2 during the period when MUX1 is turned on) is pre-charged. After MUX2 controls the corresponding transistor to turn on, the scanning line GateN of each pixel row is turned on, N=1, 2, 3, 4, and the data signal dateRB corresponding to the RB pixel (wherein the data signal dateRB is provided by the source driving circuit source1 and the source driving circuit source2 during the period when MUX2 is turned on) is directly written, and the data signal corresponding to the G1G2 pixel is pre-charged. According to research, this writing method has the following problems: if the coupling capacitance between the data line of the adjacent G1G2 pixel and the data line corresponding to the RB pixel is large, when the data signal corresponding to the RB pixel jumps, it will cause the data signal on the data line of the G1G2 pixel to change, reducing the screen quality, thereby affecting the screen display effect.

[0068] It should be noted that in order to distinguish whether the signal has passed through the MUX circuit, the signal coming out of the chip IC is generally regarded as a source signal before passing through the MUX circuit and as a data signal after passing through the MUX circuit.

[0069] Therefore, based on the problem found, the present invention provides the following technical means:

[0070] Figure 4 is a schematic diagram of the structure of the display panel of the present invention, such as Figure 4 As shown, the display panel includes pixels arranged in an array, which includes a plurality of pixel rows and a plurality of pixel columns. The display panel also includes a data line corresponding to each pixel column, the data line is arranged along the column direction; and a scan line corresponding to each pixel row, the scan line is arranged along the row direction. Figure 4 In the figure, four rows and eight columns are taken as an example for description, namely, including scan lines Gate1 to scan lines Gate4 and data lines Date1 to data lines Date8.

[0071] In a specific implementation process, multiple pixel columns can be divided into multiple pixel groups in the column direction, and the time-sharing period for writing data in each pixel row can be determined according to the number of pixel columns in the pixel group in the column direction or the number of pixel groups in the column direction. In this way, in the data writing stage, the scanning line corresponding to each pixel row can be controlled to output the writing level signal in time-sharing, so that the pixels in the pixel row write the data signal output by the data line corresponding to the pixels in the pixel row in different time-sharing periods. In this way, for each pixel row, when the scanning line outputs the writing level signal in time-sharing, the pixels in each pixel row can directly write the required data signal without precharging, so as to avoid the influence of the jump of the latter data signal on the previous data signal.

[0072] Specifically, Figure 5 It is another pixel arrangement diagram of the display panel. Figure 6 yes Figure 5 A driving timing control diagram of the display panel shown in FIG. Figure 7 It is a circuit diagram of a pixel circuit in a display panel. Among them, Figure 5 Only one row of pixel rows is shown, that is, an arrangement with RG1BG2 as a period. Figure 5 In the example, four adjacent pixel columns are divided into a pixel group in the column direction, and a total of four pixel groups in the column direction are divided. Each pixel group in the column direction receives a source driving signal output by a corresponding source driving circuit. The four source driving circuits are respectively recorded as source1, source2, source3, and source4.

[0073] In a specific implementation process, the time period during which the scan line corresponding to each pixel row outputs the write level signal in time-division is the same as the number of pixel columns in each pixel group in the column direction. Figure 5 and Figure 6 As shown, there are four time-sharing periods in this embodiment. The scan line includes a plurality of sub-scan lines having the same number as the time-sharing periods, that is, in this embodiment, each row of scan lines GateP_1 may include 4 sub-scan lines, denoted as GateP_1_4n to GateP_1_4n+3, and the scan signal input of each sub-scan line Figure 7 The gate terminals of the compensation transistor T2 and the writing transistor T4 are connected to the corresponding sub-scanning lines, and the pixels in each pixel group in the column direction are connected to the corresponding sub-scanning lines.

[0074] like Figure 6 As shown, the driving method of the display panel is:

[0075] When GateP_1_4n outputs a low level signal (i.e. a write level signal), Figure 7The write transistor T4 and the compensation transistor T2 are turned on, and the data signal dateR corresponding to all R pixels in the row is written via the Date terminal (data signal input terminal) of the write transistor T4;

[0076] Similarly, when GateP_1_4n+1 outputs a low-level signal, the data signal dateG1 corresponding to all G1 pixels in the row is written via the Date end of the write crystal T4; when GateP_1_4n+2 outputs a low-level signal, the data signal dateB corresponding to all B pixels in the row is written via the Date end of the write crystal T4; when GateP_1_4n+3 outputs a low-level signal, the data signal dateG2 corresponding to all G2 pixels in the row is written via the Date end of the write crystal T4. In other words, the writing of data signals adopts a completely direct-charge method, which enhances the anti-interference ability of each data line in the pixel circuit, avoids the influence of the jump of the latter data signal on the previous data signal, improves the screen quality, and thus ensures the screen display effect.

[0077] Figure 8 This is another pixel arrangement diagram of a display panel. Fig. 9 yes Figure 8 A driving timing control diagram of the display panel shown in FIG. Figure 5 and Figure 8 The difference between the two is that Figure 8 Arrangement with RGB as the cycle. Figure 8 In the example, four adjacent pixel columns are divided into a pixel group in the column direction, and a total of four pixel groups in the column direction are divided. Each pixel group in the column direction receives a source driving signal output by a corresponding source driving circuit. The four source driving circuits are respectively recorded as source1, source2, source3, and source4. Figure 8 For the display panel shown, the number of time-division periods corresponding to each row of scan lines is 3, and the scan line includes 3 sub-scan lines, which are recorded as GateP_1_3n to GateP_1_3n+2.

[0078] like Fig. 9 As shown, the driving method of the display panel is:

[0079] When GateP_1_3n outputs a low level signal (i.e. a write level signal), Figure 7 The second write transistor T4 and the compensation transistor T2 are turned on, and the data signal dateR corresponding to all R pixels in the row is written via the Date terminal of the write transistor T4;

[0080] Similarly, when GateP_1_3n+1 outputs a low level signal, the data signal dateG corresponding to all G pixels in the row is written via the Date end of the write crystal T4; when GateP_1_3n+2 outputs a low level signal, the data signal dateB corresponding to all B pixels in the row is written via the Date end of the write crystal T4. The effect that can be achieved is the same as Figure 5 The effect of the actual panel shown is similar and will not be described in detail here.

[0081] Fig.10 It is another pixel arrangement diagram of the display panel. Fig.11 yes Fig.10 A driving timing control diagram of the display panel shown in FIG. Figure 5 and Fig.10 The difference between the two is that Figure 8 The arrangement is based on RG1BG2 period. Fig.10 In the example, two adjacent pixel columns are divided into a pixel group in the column direction, and a total of 8 pixel groups in the column direction are divided. Each pixel group in the column direction receives a source driving signal output by a corresponding source driving circuit. Among them, the 8 source driving circuits are respectively recorded as source1 to source8. Fig.10 For the display panel shown, the number of time-division periods corresponding to each row of scan lines is 2, and the scan line includes 2 sub-scan lines, which are recorded as GateP_1_2n to GateP_1_2n+2.

[0082] like Fig.11 As shown, the driving method of the display panel is:

[0083] When GateP_1_2n outputs a low level signal (i.e. a write level signal), Figure 7 The second write transistor T4 and the compensation transistor T2 in the row are turned on, and the data signals dateR corresponding to all R pixels in the row are written via the Date end of the write crystal T4, and the data signals dateB corresponding to all B pixels are written via the Date end of the write crystal T4. The data signals corresponding to all R pixels are provided by the source drive circuits of the pixel groups in the odd column direction, that is, source1, source3, source5, and source7 can output the data signals corresponding to the R pixels during the period when GateP_1_2n outputs a low-level signal. The data signals corresponding to all B pixels are provided by the source drive circuits of the pixel groups in the even column direction, that is, source2, source4, source6, and source8 can output the data signals corresponding to the B pixels during the period when GateP_1_2n outputs a low-level signal.

[0084] Similarly, when GateP_1_2n+1 outputs a low-level signal, the data signals dateG1 corresponding to all G1 pixels in the row are written via the Date end of the write crystal T4, and the data signals dateG2 corresponding to all G2 pixels are written via the Date end of the write crystal T4. Among them, the data signals corresponding to all G1 pixels are provided by the source driving circuits of the pixel groups in the odd column direction, that is, source1, source3, source5, and source7 can output the data signals corresponding to the G1 pixels during the period when GateP_1_2n+1 outputs a low-level signal. The data signals corresponding to all G2 pixels are provided by the source driving circuits of the pixel groups in the even column direction, that is, source2, source4, source6, and source8 can output the data signals corresponding to the G2 pixels during the period when GateP_1_2n+1 outputs a low-level signal. Fig.10 exist Fig.11 Under the timing drive, the effect it can achieve is similar to Figure 5 The effect of the actual panel shown is similar and will not be described in detail here.

[0085] In a specific implementation process, the above Figure 5 , Figure 8 , Fig.10 In the timing control diagram corresponding to the illustrated embodiment, there is no overlapping time period between each of the time-sharing time periods, and the total duration of all the time-sharing time periods approaches the refresh time of each pixel row. In this way, the data writing time can be guaranteed as much as possible to ensure the display quality.

[0086] In a specific implementation process, Table 1 shows the refresh time corresponding to the clock signal CK / control signal CB in the case of multiple scan lines of a mobile phone and a watch. As can be seen from Table 1, for a watch, it has more than enough time to use the above Figure 5 , Figure 8 , Fig.10 The embodiment shown converts the products of MUX1:2, MUX1:3, and MUX1:4. For a mobile phone, in the case of MUX1:2, MUX1:3, and MUX1:4, it is necessary to ensure that CK / CB is less than 1.49 μs.

[0087] Table 1

[0088]

[0089] In a specific implementation process, the above Figure 5 , Figure 8 , Fig.10The embodiments shown are all examples without MUX circuits. In applications, for a display panel with a MUX circuit, a similar method can also be used to output a write level signal in a time-sharing manner for the scan line corresponding to each pixel row during the data writing phase, so that the pixels of the pixel row are written with the data signals output by the data lines corresponding to the pixels of the pixel row in different time-sharing periods. It can also perform direct charge writing to avoid the influence of the jump of the latter data signal on the previous data signal.

[0090] Specifically, when there is a MUX circuit, odd-numbered pixel columns can be divided into an odd-numbered pixel group in the column direction, and even-numbered pixel columns can be divided into an even-numbered pixel group in the column direction; in this case, the number of time-sharing periods and the number of pixel groups in the column direction are both 2.

[0091] Fig.12 yes Figure 2 Another timing control diagram of the display panel under the power supply mode. Figure 1 and 12 As shown, the first selection circuit (MUX1) is configured to select the pixels of the even pixel group to write the data signal, and the second selection circuit (MUX2) is configured to select the pixels of the odd pixel group to write the data signal. Fig.12 The naming of GOA output signals is mainly to distinguish odd and even rows, such as *_O / E_*, and to sort odd and even rows separately, such as *_O1 / E1_, *_O2 / E2_*, where O represents odd rows and E represents even rows.

[0092] For the first pixel row, the driving method is as follows:

[0093] GOA_O1_G1G2 is set low, and the G1 pixel is written by the first data signal provided by source1, and the G2 pixel is written by the first data signal provided by source2. GOA_O1_RB is set low, and the R pixel is written by the second data signal provided by source1, and the B pixel is written by the second data signal provided by source2. There is an overlapping time period between the two time-sharing periods, and each of the time-sharing periods approaches the refresh time of each pixel row. In this way, each data signal is first written in a partial direct charge manner, and then written in a partial pre-charge form, which increases the data signal writing time and alleviates the problem of insufficient data signal writing time during row-by-row driving.

[0094] Similarly, the driving method for the driving process of the second pixel row is as follows:

[0095] GOA_E1_G1G2 is set low, the G2 pixel is written by the third data signal provided by source1, and the G1 pixel is written by the third data signal provided by source2. GOA_E1_RB is set low, the R pixel is written by the fourth data signal provided by source1, and the B pixel is written by the fourth data signal provided by source2.

[0096] The driving method for the driving process of the third pixel row is as follows:

[0097] GOA_O2_G1G2 is set low, the G1 pixel is written by the first data signal provided by source1, and the G2 pixel is written by the first data signal provided by source2. GOA_O2_RB is set low, the R pixel is written by the second data signal provided by source1, and the B pixel is written by the second data signal provided by source2.

[0098] The driving method for the driving process of the fourth pixel row is as follows:

[0099] GOA_E2_G1G2 is set low, the G2 pixel is written by the third data signal provided by source1, and the G1 pixel is written by the third data signal provided by source2. GOA_E2_RB is set low, the R pixel is written by the fourth data signal provided by source1, and the B pixel is written by the fourth data signal provided by source2.

[0100] It should be noted that the data signals provided by the above-mentioned source driving circuits are Fig.12 The signal corresponding to date.

[0101] Fig.13 yes Figure 1 Another schematic diagram of a power supply method for a display panel is shown in FIG. Fig.14 yes Fig.13 Another timing control diagram of the display panel under the power supply mode.

[0102] like Fig.13 As shown, the display panel is selected by four MUX circuits, denoted as MUX1, MUX2, MUX3 and MUX4, and the data lines corresponding to each pixel column include odd data lines and even data lines, wherein the odd data lines are connected to the odd pixels in the pixel column, and the even data lines are connected to the even pixels in the pixel column. Fig.13, MUX1 selects the pixels in the odd pixel rows in the even pixel group to write the data signals of the odd data lines, MUX2 selects the pixels in the odd pixel rows in the odd pixel group to write the data signals of the odd data lines, MUX3 selects the pixels in the even pixel rows in the even pixel group to write the data signals of the even data lines, and MUX4 selects the pixels in the even pixel rows in the odd pixel group to write the data signals of the even data lines.

[0103] like Fig.14 As shown, for the first pixel row, the driving method is as follows:

[0104] GOA_O1_G1G2 is set low, and the G1 pixel is written by the first data signal provided by source1, and the G2 pixel is written by the first data signal provided by source2. GOA_O1_RB is set low, and the R pixel is written by the second data signal provided by source1, and the B pixel is written by the second data signal provided by source2. There is an overlapping time period between the two time-sharing periods, and each of the time-sharing periods approaches the refresh time of each pixel row. In this way, each data signal is first written in a partial direct-charge manner, and then written in a partial pre-charge form, which increases the data signal writing time and alleviates the problem of insufficient data signal writing time during row-by-row driving. In addition, since each of the time-sharing periods approaches the refresh time of each pixel row, rather than the refresh time of two pixel rows, crosstalk between the data signals of the odd data lines and the data signals of the even data lines in two adjacent pixel columns can be avoided.

[0105] Specifically, Fig.14 In the example, the conversion of GOA_O1_G1G2 from a low level signal to a high level signal occurs before MUX2 outputs a low level signal, that is, the opening time of GOA_O1_G1G2 approaches the refresh time of one pixel row. If the opening time of GOA_O1_G1G2 approaches the refresh time of two pixel rows, that is, the conversion of GOA_O1_G1G2 from a low level signal to a high level signal occurs before MUX3 outputs a low level signal, at this time, when the pixels in the odd columns of the second pixel row are writing data, the even columns of the first pixel row are still writing data, and the data signals of the two data lines are prone to crosstalk, affecting the display effect.

[0106] Similarly, the driving method for the driving process of the second pixel row is as follows:

[0107] GOA_E1_G1G2 is set low, the G2 pixel is written by the third data signal provided by source1, and the G1 pixel is written by the third data signal provided by source2. GOA_E1_RB is set low, the R pixel is written by the fourth data signal provided by source1, and the B pixel is written by the fourth data signal provided by source2.

[0108] The driving method for the driving process of the third pixel row is as follows:

[0109] GOA_O2_G1G2 is set low, the G1 pixel is written by the first data signal provided by source1, and the G2 pixel is written by the first data signal provided by source2. GOA_O2_RB is set low, the R pixel is written by the second data signal provided by source1, and the B pixel is written by the second data signal provided by source2.

[0110] The driving method for the driving process of the fourth pixel row is as follows:

[0111] GOA_E2_G1G2 is set low, the G2 pixel is written by the third data signal provided by source1, and the G1 pixel is written by the third data signal provided by source2. GOA_E2_RB is set low, the R pixel is written by the fourth data signal provided by source1, and the B pixel is written by the fourth data signal provided by source2.

[0112] It should be noted that the data signals provided by the above-mentioned source driving circuits are Fig.13 The signal corresponding to date.

[0113] In a specific implementation process, in the above embodiments, when each row of pixels uses multiple sub-scan lines to implement time-sharing data writing, the multiple sub-scan lines can be located on the same side of the gate of the write transistor and the gate of the compensation transistor in each pixel in each row of pixels, or at least two of the multiple sub-scan lines are located on different sides of the gate of the write transistor and the gate of the compensation transistor.

[0114] Fig.15 is based on Fig.10 The layout structure of the display panel is shown in FIG. Fig.15 As shown, Fig.15 The left side of the middle is the original layout structure, where each pixel is connected by a scan line. The solution of using multiple sub-scan lines to write data in time is Fig.15 In the layout on the right side of the figure, the first sub-scan line GateP_1_2n connects the pixels of the odd pixel columns, and the second sub-scan line GateP_1_2n+1 connects the pixels of the even pixel columns. Fig.15The first sub-scanning line GateP_1_2n and the second sub-scanning line GateP_1_2n+1 are located on the same side of the gate of the write transistor and the gate of the compensation transistor, and the case where they are located on different sides is not further described. Fig.15 It is only a schematic illustration of the arrangement of the two sub-scanning lines, and the arrangement of the transistors and other related elements in the figure remains unchanged. For details, please refer to the existing related technology and will not be repeated here.

[0115] It should be noted that the layout structure of the above other display panels is similar to Fig.15 There are many types of arrangement, and I will not give examples one by one here.

[0116] Furthermore, the present invention also provides a method for driving a display panel, the method for driving a display panel comprising:

[0117] In the data writing phase of each pixel row, the corresponding scanning line is controlled to output the writing level signal in time division, so that the pixels of the pixel row are written with the data signal output by the data line corresponding to the pixels of the pixel row in different time division periods;

[0118] The number of the time-division periods is determined according to the number of pixel columns in the pixel group in the column direction or the number of pixel groups in the column direction.

[0119] Furthermore, the present invention also provides a display device, which includes the display panel of the above embodiment. The display device may include a mobile phone or a watch.

[0120] Fig.16 is a schematic diagram of a display device of the present invention, the display device adopts Figure 5 The display panel shown. Gate drive circuits are arranged on both sides of the display area AA of the display panel. The light emitting control signal line EMk in the gate drive circuit corresponds to two rows of pixels. Wherein, k=1, 2, 3...N / 2, and N is a function of the pixel row. The scan line in the gate drive circuit corresponds to one row of pixels, and the scan line of each row of pixels includes 4 sub-scan lines, which are respectively recorded as GateP_i_4n to GateP_i_4n+3, and i=1, 2, 3...N.

[0121] Fig.17 is another schematic diagram of the display device of the present invention, the display device adopts Figure 8 The display panel shown. The gate drive circuit is set on both sides of the display area of ​​the display panel. Among them, the light control signal line in the gate drive circuit corresponds to two rows of pixels. The scanning signal line in the gate drive circuit corresponds to one row of pixels, and the scanning line of each row of pixels includes 3 sub-scanning lines, which are respectively recorded as GateP_i_3n to GateP_i_3n+3, i=1, 2, 3...N.

[0122] Fig.18 is another schematic diagram of the display device of the present invention, the display device adopts Figure 8 The display panel shown. The gate driving circuit is set on both sides of the display area of ​​the display panel. Among them, the light control signal line in the gate driving circuit corresponds to two rows of pixels. The scanning signal line in the gate driving circuit corresponds to one row of pixels, and the scanning line of each row of pixels includes 2 sub-scanning lines, which are respectively recorded as GateP_i_2n to GateP_i_2n+2, i=1, 2, 3...N.

[0123] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: Pixels arranged in an array, comprising a plurality of pixel rows and a plurality of pixel columns, wherein the plurality of pixel columns are divided into a plurality of pixel groups in a column direction; A data line corresponding to each pixel column, wherein the data lines are arranged along a column direction; A scan line corresponding to each pixel row, wherein the scan lines are arranged along a row direction; Wherein, each scan line is configured to output a write level signal in a time-sharing manner during the data writing phase of the corresponding pixel row, so that the pixels of the pixel row write the data signals output by the data line corresponding to the pixels of the pixel row in different time-sharing periods; wherein the number of the time-sharing periods is determined according to the number of pixel columns in the pixel group in the column direction or the number of pixel groups in the column direction.

2. The display panel according to claim 1, characterized in that: At least two sequentially adjacent pixel columns are divided into a pixel group in a column direction; The number of the time division periods is the same as the number of pixel columns in each column-directional pixel group.

3. The display panel according to claim 2, characterized in that: There is no overlapping time period between each of the time-sharing time periods, and the total duration of all the time-sharing time periods approaches the refresh time of each pixel row.

4. The display panel according to claim 1, characterized in that: The odd-numbered pixel columns are divided into an odd-numbered pixel group in a column direction, and the even-numbered pixel columns are divided into an even-numbered pixel group in a column direction; The number of the time-division periods and the number of the pixel groups in the column direction are both 2.

5. The display panel according to claim 4, characterized in that: The display panel further includes a first gating circuit and a second gating circuit; The first gating circuit is configured to select pixels of the even pixel group to write data signals; The second gating circuit is configured to select pixels of the odd pixel group to write data signals.

6. The display panel according to claim 4, characterized in that: The data lines include odd data lines and even data lines, wherein the odd data lines are connected to odd pixels in the pixel column, and the even data lines are connected to even pixels in the pixel column; The display panel further includes a first gating circuit, a second gating circuit, a third gating circuit and a fourth gating circuit; The first gating circuit is configured to select pixels in odd pixel rows in the even pixel group to write data signals to the odd data lines; The third gating circuit is configured to select pixels in even pixel rows in the even pixel group to write data signals to the even data lines; The second gating circuit is configured to select pixels in odd pixel rows in the odd pixel group to write data signals to the odd data lines; The fourth gating circuit is configured to select pixels in even pixel rows in the odd pixel group to write data signals to the even data lines.

7. The display panel according to claim 5 or 6, characterized in that: There is an overlapping time period between the two time-sharing time periods, and each of the time-sharing time periods is close to the refresh time of each pixel row.

8. The display panel according to any one of claims 1 to 6, characterized in that: The pixel circuit corresponding to the pixel includes a writing transistor and a compensation transistor; The scanning line includes a plurality of sub-scanning lines which are equal in number to the time-sharing periods; The plurality of sub-scan lines are all located on the same side of the gate of the write transistor and the gate of the compensation transistor, or at least two of the plurality of sub-scan lines are located on different sides of the gate of the write transistor and the gate of the compensation transistor.

9. A method for driving a display panel according to any one of claims 1 to 8, characterized in that: include: In the data writing phase of each pixel row, the corresponding scanning line is controlled to output the writing level signal in time division, so that the pixels of the pixel row are written with the data signal output by the data line corresponding to the pixels of the pixel row in different time division periods; The number of the time-division periods is determined according to the number of pixel columns in the pixel group in the column direction or the number of pixel groups in the column direction.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 8.

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