Parallel power switch

Abstract

The power switch system comprises: a plurality of power switch units, each power switch unit comprising a corresponding power switch; a communication system configured to transmit a system-wide switching command to the power switching unit along a communication channel; and circuitry included in each of the power switching cells configured to delay execution of the system-wide switching command by a delay time.

Description

Technical Field

[0001] This specification relates to the parallel connection of power switches. Background Art

[0002] A power switch is a switching device designed to switch relatively high voltages and currents. Embodiments of power switches include insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), etc. These power switches are typically made using semiconductor materials such as silicon, silicon carbide, gallium nitride, or other semiconductor materials. In some cases, a single power switch will include more than one physical transistor. For example, two transistors in a common source and common gate configuration can form a single power switch.

[0003] In practice, individual power switches are typically associated with dedicated control, communication, and fault protection circuitry. Providing drive signals to the power switches is handled by the associated circuitry.

[0004] Even when a single power switch has device characteristics tailored to switch relatively high voltages and currents, a single power switch is often unable to meet the needs of some applications. To address such needs, multiple power switches are often connected in parallel so that each power switch conducts only a portion of the total current. Typically, the total current flowing through the components of the power switch is monitored.

[0005] Additionally, the voltage between the main terminals of the individual power switches (ie, the collector-to-emitter voltage or the drain-to-source voltage) may be monitored for various purposes. For example, dedicated fault protection circuitry may monitor such voltages of the individual power switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic representation of a system in which the switching of different power switches is coordinated to switch the total current and voltage.

[0007] Figure 2A-2D Different methods to determine the current carrying behavior of an IGBT during a switching transition based on VCE sensing information are schematically illustrated.

[0008] Figure 3 is a schematic representation of one implementation of a power switch and associated circuitry.

[0009] Figure 4 It is a swim lane diagram showing the operations in the system for coordinating the switching of different power switches.

[0010] Figure 5is a schematic representation of the structure of a bus that can be used to implement a communication channel between a master driver and one or more slave drivers in a system for coordinating the switching of different power switches.

[0011] Like reference symbols in the various drawings indicate like elements.

[0012] For teaching purposes, the detailed description is based on an insulated gate bipolar transistor (IGBT) power switch. However, the corresponding teachings can be applied to a variety of different enhancement or depletion mode devices (e.g., bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), or high electron mobility transistors (HEMTs)) with electron or hole charge carriers, either alone or in combination with other transistors. The device can be implemented in silicon, silicon carbide, gallium nitride, or other semiconductor materials. DETAILED DESCRIPTION

[0013] The switching of multiple power switches can be coordinated. This coordination can be used to achieve any of a number of different goals and advantages.

[0014] For example, in some embodiments described herein, the switching of power switches is customized to ensure that the currents carried by the different switches are balanced. In balanced current sharing, the total current is relatively equally divided among the switches. The more evenly the current is distributed among the power switches, the fewer switches are required to switch a given total current while ensuring safe operation.

[0015] By way of example, assume that 3000A will be switched using a power switch with a rated or nominal current of 650A. The rated or nominal current of a power switch may be defined as the maximum continuous DC current that can safely flow through the power switch under defined conditions (e.g., at a defined maximum junction temperature). Returning to the embodiment, if the current sharing is unbalanced, there may be relatively large differences between the currents switched by different switches. For example, if one attempts to operate all switches at a target current of 600A, a 15% change in the currents switched by different power switches will cause one power switch to conduct 510A while another conducts 690A. It is possible that the current through at least one switch will exceed the rated collector current. The designer will accommodate this change by adding additional switches so that the target current carried by any given switch remains below the rated collector current. For example, instead of operating five switches at a target current of 600A, six switches operating at a target current of 500A may be used.

[0016] Alternatively, if the current is more evenly distributed and the current sharing is better balanced (e.g., the currents switched by the different switches have only a 5% variation from the target current of 600 A), then five switches may be used for a target current of 600 A. Furthermore, a relatively large safety margin relative to the maximum rated current of the switches may be maintained.

[0017] As another example, in some embodiments described herein, the switching of the power switches is customized to ensure that the current carried by different switches is unbalanced. In contrast to balanced current sharing, unbalanced current sharing causes the total current to be unevenly distributed among the power switches. Even if the switches nominally have the same power rating (i.e., the same voltage and current capacity) or are of the same type (i.e., are identical within manufacturing tolerances), the current may be unevenly distributed.

[0018] In some embodiments described herein, an intentional current imbalance can accommodate deviations between devices. The deviation can be inherent in the switch (i.e., present in the switch at the time of manufacture) or can occur over time. For example, over time, the temperature of the power switch can change or the structure of the power switch can degrade. Regardless of the cause, the deviation can be accommodated, for example, to more closely tailor the switch capacity to the requirements of the operating environment, or to respond to conditions that arise during operation.

[0019] By way of example, again assume that 3000 A is to be switched using a power switch with a rated current of 650 A. Initially, the current is almost evenly distributed, e.g., between the five switches, the current switched by the different switches has only a 5% variation from the target current of 600 A. However, at some point during the operating life of the switches, assume that one of the switches begins to degrade. For example, thermal fatigue or mechanical fatigue may degrade the performance of one of the switches.

[0020] By reducing the current carried by this degraded switch, the life of that switch, and therefore the life of the system of switches, can be extended. For example, the target current through the degraded power switch can be reduced to 540A, while the target current through the other four switches is increased to 615A. If the current through the other four switches is kept well balanced with only a 5% variation, this will keep all of them below their maximum rated current of 650A and reduce wear on the degraded switch. The life of the entire system can be extended.

[0021] In some embodiments described herein, the switching of different power switches is actively tailored on a switching-cycle-by-switching-cycle basis. Deviations from a desired balance / imbalance can be quickly resolved.

[0022] In some embodiments described herein, information that has been measured for other reasons is used to actively customize the switching of different power switches, for example, to limit overvoltage transients during a turn-off switch event. For example, the measurement of the voltage between the main terminals of a separate power switch can be used to coordinate the switching of different power switches within the system. In some cases, the voltage between the main terminals can be sensed directly. In other cases, the voltage between the main terminals can be sensed indirectly, such as by measuring the current flowing through an impedance network.

[0023] Figure 1 is a schematic representation of a system 100 in which the switching of different power switches is coordinated to switch a total current I SW and voltage VCC. The system 100 includes a plurality of individually addressable switch units 110, 111, 112. Each switch unit 110, 111, 112 includes an IGBT power switch 115 and an associated switch controller and driver circuitry 120. In operation, the switching of the IGBT power switches 115 in the system 100 is coordinated to achieve a desired distribution of current flowing through the IGBT power switches 115.

[0024] In more detail, the illustrated embodiment of the system 100 includes three switch units 110, 111, 112. The first of these units (i.e., unit 110) acts as a "master unit" and is configured to coordinate the switching of the switch units 110, 111, 112 with adjustments addressed to the individual power switches. In addition, the switch unit 110 can be coupled to a system controller 105. The system controller 105 is the component responsible for controlling the timing of power switching in the system 100 - with system-level commands addressed to the entire system 100. The system controller 105 can be implemented using a microcontroller or a field programmable gate array (FPGA).

[0025] The system controller 105 is communicatively coupled to the switch unit 110 via one or more communication channels 117. The system controller 105 is configured to send signals to the switch unit 110 along the channel(s) 117. The signals specify when the IGBT power switch 115 is to switch from an open, substantially non-conducting, disconnected state to a closed, current-conducting, conductive state, and vice versa. However, the switching commands are for the entire system 100, rather than being individually addressed to any one of the switch units 110, 111, 112. The switch unit 110 is configured to receive those system-wide switching commands and implement them itself and relay them to the other switch units 111, 112.

[0026] In addition to these system-wide switching commands, the switch unit 110 sends timing adjustments to each switch unit 111, 112 that will be made to these system-wide switching commands. Typically, the switch unit 110 will also apply its own timing adjustments to the system-wide switching commands. The adjustments are individually customized and specific to each switch unit 110, 111, 112, and as further discussed below, specify relatively fine adjustments to the timing of the disconnection / conduction and / or conduction / disconnection transitions of the IGBT power switches 115 in those switch units. The adjustments further refine the switching of the switch units 110, 111, 112 with greater precision to achieve the desired distribution of the current flowing through the IGBT power switches 115. Although the duration of the relatively fine adjustments is theoretically unlimited, as a practical matter, for a given set of operating conditions in the system 100, the duration of the adjustments is typically only a fraction of one of the intrinsic rise time or fall time of the gate. For example, in some embodiments, the adjustment may be between 0 and 1000 nanoseconds, such as between 0 and 300 nanoseconds under typical operating conditions.

[0027] Typically, but not necessarily, communication along channel(s) 117 is bidirectional, and the switch unit 110 will also transmit information to the system controller 105. Examples of information transmitted from the master unit 110 to the system controller 105 may include error / fault information and operational information (e.g., temperature).

[0028] In the illustrated embodiment, the switch controller and driver circuit system 120 in the switch units 110, 111, 112 includes an external switch unit communication circuit system 122 and an internal switch unit communication circuit system 125. The external switch unit communication circuit system 122 is a circuit system configured to exchange information with components other than the switch unit. For example, in the switch unit 110, the external switch unit communication circuit system 122 is configured to exchange information with the system controller 105 through (one or more) channels 117. Although each switch unit 110, 111, 112 in the illustrated embodiment includes an external switch unit communication circuit system 122, this is not necessarily the case, and in some embodiments, the external switch unit communication circuit system 122 can be omitted from one or both of the switch units 111, 112.

[0029] The internal switch unit communication circuit system 125 is a circuit system configured to exchange commands and information with other switch units in the system 100 through one or more channels 130. Communication along the channels 130 is bidirectional. As discussed further below, the information exchanged can include operational details communicated from the slave switch units 111, 112 to the master switch unit 110, as well as signals specifying adjustments to the timing of switching transitions of the IGBT power switches 115 in the switch units 111, 112.

[0030] In addition to the communication circuitry 122, 125, each switch controller and driver circuitry 120 includes circuitry for driving the corresponding IGBT power switch 115 between the on state and the off state and circuitry for controlling the driving. The driving function is typically implemented using a totem pole (pull-up, pull-down) driver, although direct drive and other drivers are possible. The control function may include timing adjustments and reliance on the collector-to-emitter voltage V of the sensed IGBT power switch 115. CE Therefore, each switch unit 110, 111, 112 includes a switch controller and a driver circuit system 120 that allows the collector-to-emitter voltage V of the IGBT power switch 115 to be sensed. CE VCE sense line 135. As discussed further below, the switch controller and driver circuitry 120 may be configured to determine:

[0031] - the time(s) required for the collector-to-emitter voltage VCE to fall and / or rise to one or more threshold voltage levels,

[0032] - the value(s) of the collector-to-emitter voltage VCE at one or more defined times, or

[0033] -both such time(s) and such value(s).

[0034] In many embodiments, the communication circuitry 122, 125 is galvanically isolated from the IGBT 115 and its associated drive circuitry and the VCE sense line 135. In these cases, the switch controller and driver circuitry 120 includes internal communication circuitry and components (e.g., optocouplers, transformers, capacitors, and associated switch circuitry) for bidirectional communication across the galvanic isolation. The bidirectional communication can be performed via a bidirectional communication channel or two (or more) unidirectional communication channels that communicate in opposite directions. There are commands that encode switching instructions and data signals that encode VCE sensing information in the communication.

[0035] In some embodiments, the system 100 may be operable to adjust the timing of the switching transitions of the IGBTs 115 in the switch cells 110, 111, 112 on a switching cycle-by-switching cycle basis using VCE sensing information collected during previous switching cycles. For example, in operation, the system controller 105 may transmit switching commands to the switch cells 110 along the channel(s) 117. The switching commands will generally indicate the times at which the IGBTs 115 will be switched into conduction and out of conduction. The switch controller and driver circuitry 120 receives the switching commands at the external system communication circuitry 122. For the first such switching command (e.g., the first command after startup or a reset after a fault condition), the switch controller and driver circuitry 120 in the switch cell 110 relays the switching commands to the switch cells 110, 111, 112 using the internal switch cell communication circuitry 125 and the channel 130. Incidentally, by routing the switching commands for the switch unit 110 through the same internal switch unit communication circuitry 125 and channel 130 that transmits the switching commands to the switch units 111, 112, the switch units 110, 111, 112 are all subject to the same propagation delay caused by placing the switching commands on the channel 130. In other words, the switch units 110, 111, 112 all respond to the switching commands on the channel 130. The propagation delay associated with placing the switching commands on the channel 130 is the same.

[0036] In any case, the switch cells 110, 111, 112 receive the switching commands on the channel 130 and route the switching commands through their respective switch controllers and driver circuit systems 120 to switch their respective IGBTs 115 into conduction or out of conduction in response to and according to the relayed switching commands. Since each switch controller and driver circuit system 120 in the different switch cells 110, 111, 112 is almost identical, this also reduces the differences in propagation delays. In some embodiments, additional fine-tuning circuit systems can be included to further reduce any differences.

[0037] During switching transitions between conduction states, the switch controller and driver circuitry 120 in each switch cell receives the VCE sense line 135 for the corresponding IGBT 115. CE Sensing Information. Each switch controller and driver circuit system 120 can be configured to measure:

[0038] - the time(s) required for the collector-to-emitter voltage VCE to fall and / or rise to one or more threshold voltage levels,

[0039] - the value(s) of the collector-to-emitter voltage VCE at one or more defined times, or

[0040] -both such time(s) and such value(s).

[0041] Thus, the time or value may be measured during either or both of an on / off transition or an off / on transition. Furthermore, the time or value characterizes the actual current conduction through the IGBT 115 during such a transition. This contrasts with schemes in which parameters such as the gate-to-emitter voltage VGE are sensed and the current conduction is assumed to follow. Specifically, the operating current-carrying behavior of the IGBT 115 is sensed - reflecting manufacturing variability and temperature effects. In any case, the determined time or value is transmitted from the switch controller and driver circuitry 120 in the switch cells 111, 112 to the switch cell 110 via the channel(s) 130 using the internal switch cell communication circuitry 125.

[0042] In some embodiments, the clocks in different switch cells 110, 111, 112 can be synchronized, for example using phase locking. In some embodiments, the clocks on both the primary and secondary sides of the switch cells 110, 111, 112 can be synchronized. As discussed further below, the synchronized clocks can provide a common time reference for measuring the time required for the collector-to-emitter voltage VCE to exceed a threshold in different switch cells 110, 111, 112, or for defining the time at which the value of the collector-to-emitter voltage VCE will be measured. For example, in Figure 2A , Figure 2B , Figure 2C , Figure 2D In the contact, the synchronized clock can provide a common time reference for time A and C.

[0043] The switch controller and driver circuit system 120 in the switch unit 110 determines a relatively fine, higher precision adjustment to be made to the timing of the switch transition of the IGBT power switch 115 in the switch unit 110, 111, 112 in the next switch cycle. In the initial switch cycle, all adjustments will be delayed. However, in subsequent cycles, the delay can also be reduced. In some embodiments, the adjustment can be decomposed into discrete time steps, such as increments of 1-10 nanoseconds, and for a given set of operating conditions is usually only a small part of the inherent rise time or fall time of the gate. The adjustment is customized for each switch unit 110, 111, 112. In some cases, the adjustment of the timing of the switch transition for the switch unit 110 will be different from the adjustment of the timing of the switch transition for the switch unit 111, and the adjustment of the timing of the switch transition for the switch unit 111 will be different from the adjustment of the timing of the switch transition for the switch unit 112.

[0044] In some embodiments, the adjustment is designed to gradually approach the desired current distribution over multiple switching cycles. For example, instead of using a relatively large adjustment to try to immediately achieve the desired current distribution in the next switching cycle, a more gradual adjustment that is expected to result in a less unbalanced current distribution can be applied in the next switching cycle. Similarly, a gradual adjustment that will not immediately achieve the desired current distribution can be applied in subsequent switching cycles. In addition, after the adjustment is applied, the collector-to-emitter voltage V CE The time / value of may indicate that the desired current profile has been overshoot. In other words, before the adjustment is applied, the current conducted by the switch cell may be too low. After the adjustment is applied, the current conducted by the same switch cell may be too high. In such a case, an adjustment in the opposite direction (i.e., a "reduced" or even "negative" adjustment) may be applied in a subsequent switching cycle.

[0045] In any case, signals representing adjustments for the switch cells 111, 112 are transmitted from the switch controller and driver circuitry 120 in the switch cell 110 to the switch cells 111 and 112 over the channel(s) 130 using the internal switch cell communication circuitry 125. The adjustments are individually addressed to the corresponding switch cells 111, 112. The adjustments may include:

[0046] - Zero adjustment or no adjustment;

[0047] - Adjustment of the timing of executing the switch-on command;

[0048] - Adjustment of the timing of executing the shutdown command;

[0049] - Adjustment of the timing of executing both the switch-on command and the switch-off command.

[0050] The timing adjustment can be expressed as:

[0051] - with respect to the receipt of a switching command by the switching unit in each individual switching cycle, or

[0052] - relative to the timing adjusted in a previous (eg, immediately preceding or otherwise) switching cycle.

[0053] In the former case, each timing adjustment will simply be represented as zero (ie, no adjustment) or as a positive value, which indicates a delay in the transition. In the latter case, the timing adjustment may also be a negative value, which indicates an earlier start of the transition than in the previous switching cycle.

[0054] In some embodiments, the slowest of the switch cells 110, 111, 112 is designated as the reference switch cell. To balance the currents between the switch cells 110, 111, 112, a signal having a positive value representing a delay may be sent to the rest of the switch cells 110, 111, 112. If the collector-to-emitter voltage V CE Indicating that a desired current set point has been crossed, the delay time can be adjusted.

[0055] In the embodiments described above, the timing of the switching transitions of the IGBTs 115 in the switching units 110, 111, 112 uses only the V CEThe sensed information is adjusted on a switch cycle by switch cycle basis. This need not be the case. For example, in some embodiments, the timing of a switch transition only needs to be adjusted every N switch cycles, where N is greater than 1, or mathematically: N>1. Therefore, the switch adjustment can be applied in the next immediately subsequent switch cycle or in another subsequent switch cycle. By adjusting the timing every N switch cycles, sufficient time can be provided to complete the calculation of the delay time and communicate the relevant information to the device. As another example, in some embodiments, the adjustment of the timing of the switch transition can take into account the V collected during the previous M switch cycles. CE Sensing information, where M is greater than 1, or mathematically: M>1. For example, V CE The average or weighted average of the sensed information. In some cases, N>1 and M>1.

[0056] Furthermore, in the embodiments described above, the switch controller and driver circuit system 120 in the switch unit 110 determine the adjustments to be made to the timing of the switch transitions of the IGBT power switches 115 in the switch units 110, 111, 112. This is not necessarily the case. Instead, in other embodiments, some or all of the determinations may be performed elsewhere. For example, in some embodiments, the system controller 105 may determine the adjustments. As another example, in some embodiments, the system controller 105 may determine some adjustments, and the switch controller and driver circuit system 120 in the switch unit 110 may determine other adjustments. For example, the switch controller and driver circuit system 120 in the switch unit 110 may be responsible for determining the adjustments in the case where the current will be balanced, while the system controller 105 may be responsible for determining the adjustments in the case where the current will be unbalanced. As yet another example, in some embodiments, a human user may specify the adjustments.

[0057] Figure 2A-2D Different methods for determining the current carrying behavior of an IGBT based on VCE sensing information during a switching transition are schematically illustrated. Specifically, Figure 2A , Figure 2B Schematically illustrates the collector-to-emitter voltage V of three different IGBT switches as a function of time during a transition from an off state to an on state in three different switching cells CE and collector current I C ,and Figure 2C , Figure 2D Schematically illustrates the collector-to-emitter voltage V of three different IGBTs switched as a function of time during the transition from the on-state to the off-state CE and collector current I C .

[0058] Figure 2A , Figure 2B The off / on transition illustrated in FIG. 1 is triggered by an on command 205 occurring at time A. In system 100 ( Figure 1 ), the switch-on command 205 may be received by the master switch unit 110 from the system controller 105 via the communication channel(s) 117. The switch-on command 205 is relayed from the master switch unit 110 to itself and to the slave switch units 111, 112 via the communication channel(s) 130.

[0059] Even though the switching commands are transmitted to the switch units 110, 111, 112 via the same communication channel(s) 130, it should be understood that there are still differences in propagation delays within the system 100. In some embodiments, the propagation delay is measured during the initialization phase. An example is discussed below. In the system 100 ( Figure 1 ), the occurrence of time A in different switch units 110, 111, 112 will be defined and recorded - at least temporarily - at the switch controller and driver circuit system 120 within the master switch unit 110. In other embodiments, the clocks at the different switch units 110, 111, 112 are synchronized, and it is assumed that the time A at which each switch-on command 205 occurs is the same in the different switch units 110, 111, 112.

[0060] The driver circuitry in the different switch cells responds to the on command 205 by appropriately biasing the gates of the (one or more) IGBTs in those switch cells to cause an off-to-on transition. In response, the corresponding collector-to-emitter voltage V CE1 、V CE2 、V CE3 The collector-to-emitter voltage V during the IGBT off time CE(off) Reduced to nearly zero. Collector current I C1 ,I C2 ,I C3 The collector-to-emitter voltage V CE1 、V CE2 、V CE3 The reduction will be reflected in V CE sensing information, and can be based on V CE The sensing information identifies information about the current carrying behavior of the IGBT switch.

[0061] For example, in Figure 2AIn , a voltage threshold level X 210 is defined for all three switches. The collector to emitter voltage V CE1 、V CE2 、V CE3 The time B1, B2, B3 to drop to or below the voltage threshold level X 210 can be measured by each switching unit. Figure 1 ), the times B1, B2, B3 will be determined by the switch controller and driver circuit system 120 in the switch units 110, 111, 112. The data representing the times B1, B2, B3 are transmitted to the switch controller and driver circuit system 120 in the main switch unit 110 via the channel 130.

[0062] By the way, in some embodiments, the voltage threshold level X 210 (and other voltage threshold levels described herein) can be customized for individual switch cells 110, 111, 112 over time. For example, the collector-to-emitter voltage at each switch cell 110, 111, 112 can be measured in the off state, and the voltage threshold level can be set relative to the off-state measurement result. The switch cells 110, 111, 112 can repeatedly perform measurements and settings to accommodate differences between the switch cells 110, 111, 112 and changes in the operating environment (e.g., temperature and voltage levels).

[0063] Due to variations between switch units, the times B1, B2, B3 will typically vary from switch unit to switch unit. In embodiments where the clocks in the different switch units 110, 111, 112 are synchronized, the time A at which each turn-on command 205 occurs is substantially common, and the times B1, B2, B3 embody information about the current-carrying behavior of the individual IGBT switches. The same information may be embodied in the respective turn-on times T of each IGBT. ON1_M1 , T ON1_M2 , T ON1_M3 The on-time T ON1_M1 , T ON1_M2 , T ON1_M3 It is the duration between time B1, B2, B3 and time A. On time T ON1_M1 , T ON1_M2 , T ON1_M3 Indicates that the power switch is controlled to conduct with the collector to emitter voltage V CE1 、V CE2 、V CE3 The delay between reaching the voltage threshold level X210.

[0064] exist Figure 2A In the schematic illustration, during the off-to-on transition, the collector-to-emitter voltage VCE2 The downward slope of the collector-to-emitter voltage V CE1 、V CE3 The slope is slightly steeper, and V CE3 The slope is higher than V CE1 、V CE2 The slope of is slightly more gradual. The on time T ON_M2 T ON_M1 Slightly shorter, the on time T ON_M1 Then, the on time T ON_M3 Slightly shorter. Times B1, B2, B3 and on-time T ON1_M1 , T ON1_M2 , T ON1_M3 Information about the current carrying behavior of the IGBT switching cell during a switching cycle is embodied. Furthermore, as discussed above, this information can be used to determine relatively fine adjustments to be made to the timing of the switching transitions in the next switching cycle.

[0065] Multiple voltage thresholds can also be used depending on V CE The sensing information identifies the current-carrying behavior of the IGBT. Figure 2B In FIG. 2 , an additional voltage threshold level Y 215 is defined for all three switch cells. The collector-to-emitter voltage V CE1 、V CE2 、V CE3 The time C1, C2, C3 of the voltage threshold level Y 215 or the time C2, C3 of the voltage threshold level Y 215. Figure 1 ), the times C1, C2, C3 will be determined by the switch controller and driver circuit system 120 in the switch units 110, 111, 112. The data representing the times C1, C2, C3 are transmitted to the switch controller and driver circuit system 120 in the main switch unit 110 via the channel 130.

[0066] As with B1, B2, B3, the times C1, C2, C3 will typically vary from switch unit to switch unit. Again assuming synchronization, the time A at which each on command 205 occurs is common to the switch units, and the times B1, B2, B3, C1, C2, C3 embody information about the current carrying behavior of the individual IGBTs. The same information can be embodied in the corresponding on time T of the first switch unit. ON1_M1 and T ON2_M1 , T of the second switch unit ON1_M2 and T ON2_M2 and the third switch unit T ON1_M3 and T ON2_M3 The on-time T ON1_M1 , T ON1_M2 , TON1_M3 is the duration between time B1, B2, B3 and time A, and T ON2_M1 , T ON2_M2 , T ON2_M3 is the duration between time C1, C2, C3 and time A. In system 100 ( Figure 1 ), the switch controller and driver circuit system 120 in the master switch unit 110 or the individual slave switch units 111, 112 can use the occurrence time of time B1, B2, B3, C1, C2, C3 and time A to calculate the turn-on time T ON1_M1 , T ON1_M2 , T ON1_M3 , T ON2_M1 , T ON2_M2 , T ON2_M3 .

[0067] Go to Figure 2C , Figure 2D , Figure 2C , Figure 2D The on / off transition illustrated in FIG. 1 is triggered by a shutdown command 220 occurring at time C. In the system 100 ( Figure 1 ), the on command 205 may be received by the master switch unit 110 from the system controller 105 via the communication channel(s) 117 and will be relayed to the switch controller and driver circuitry within the driver circuitry 120. The off command 220 may also be received by the slave switch units 111, 112 from the master switch unit 110 via the communication channel(s) 130 and relayed to the switch controller and driver circuitry within the driver circuitry 120. Assuming clock synchronization, the time C at which each off command 220 occurs is the same in different switch units, regardless of the path of the off command 200 to the driver circuitry within those switch units. In the system 100( Figure 1 ), the occurrence of time C will be defined and recorded - at least temporarily - at the switch controller and driver circuit system 120 within the main switch unit 110.

[0068] The driver circuitry in the different switch cells responds to the turn-off command 220 by appropriately biasing the gates of the (one or more) IGBTs in those switch cells to cause an on / off transition. In response, the corresponding collector-to-emitter voltage V CE1 、V CE2 、V CE3 will increase from near zero to a voltage V CE(off) . Collector current I C1 ,I C2 ,I C3The level of current conducted by the switch cell in the on state is reduced to nearly zero (i.e., only leakage current). The collector-to-emitter voltage V CE1 、V CE2 、V CE3 The increase will be reflected in V CE sensing information, and can be based on V CE The sensing information identifies information about the current carrying behavior of the IGBT.

[0069] For example, in Figure 2C In FIG. 2 , a voltage threshold level Z 225 is defined for all three switch cells. The collector-to-emitter voltage V CE1 、V CE2 、V CE3 The time D1, D2, D3 for the voltage to rise to or above the voltage threshold level Z 225. In the system 100 ( Figure 1 ), the times D1, D2, D3 will be determined by the switch controller and driver circuit system 120 in the switch units 110, 111, 112. The data representing the times D1, D2, D3 are transmitted to the switch controller and driver circuit system 120 in the main switch unit 110 via the channel 130.

[0070] The times D1, D2, D3 will typically vary from switch cell to switch cell due to variations between, for example, the IGBTs and the paths of the turn-off commands 205 to the driver circuitry within those switch cells. Assuming clock synchronization, the time C at which each turn-off command 220 occurs is common to the switch cells, and the times D1, D2, D3 embody information about the current carrying behavior of the individual IGBTs. The same information may be embodied in the respective turn-off times T of each IGBT. OFF1 M1 , T OFF1 M2 , T OFFl_M3 The off time T OFF1_M1 , T OFF1-M2 , T OFF1_M3 It is the duration between time D1, D2, D3 and time C. Off time T OFF1_M1 , T OFF1_M2 , T OFFl_M3 represents the delay between when the power switches are controlled to be turned off and when the collector-to-emitter voltages VCE1, VCE2, and VCE3 reach the voltage threshold level Z 225. In system 100 ( Figure 1 In some embodiments of the present invention, the switch controller and the driver circuit system 120 in the main switch unit 110 can use the occurrence time of the time D1, D2, D3 and the time C to calculate the turn-off time T. OFF1_M1 , TOFF1_M2 , T OFFl_M3 .

[0071] exist Figure 2C In the schematic illustration, during the on-to-off transition, the collector-to-emitter voltage V CE2 The upward slope of the collector-to-emitter voltage V CE1 、V CE3 The slope is slightly steeper, and V CE3 The slope is higher than V CE1 、V CE2 The slope of the off time T OFF1_M2 T OFF1_M1 Slightly shorter, the off time T OFF1_M1 Then the off time T OFF1_M3 Slightly shorter. Times D1, D2, D3 and the off time T OFF1_M1 , T OFF1_M2 , T OFFl_M3 Information about the current carrying behavior of the IGBT during a switching cycle is embodied. Furthermore, as discussed above, this information can be used to determine relatively fine adjustments to be made to the timing of the switching transitions in the next switching cycle.

[0072] Multiple voltage thresholds can also be used depending on V CE The sensing information identifies the current-carrying behavior of the IGBT. Figure 2D In the system 100 ( Figure 1 ), the times E1, E2, E3 will be determined by the switch controller and driver circuit system 120 in the switch units 110, 111, 112. The data representing the times E1, E2, E3 are transmitted to the switch controller and driver circuit system 120 in the main switch unit 110 via the channel 130.

[0073] Like D1, D2, D3, the times E1, E2, E3 will typically vary from switch unit to switch unit. Assuming clock synchronization, the time C at which each shutdown command 220 occurs is common to the switch units, and the times D1, D2, D3, E1, E2, E3 embody information about the current-carrying behavior of the individual IGBTs. The same information can be embodied in the corresponding shutdown time T of the first switch unit. OFF1_M1 and T OFF2_M1 , T of the second switch unit OFF1_M2 and T OFF2_M2 and the third switch unit TOFF1_M3 and T OFF2_M3 The off time T OFF1_M1 , T OFF1_M2 , T OFF1_M3 is the duration between times D1, D2, D3 and time C, and T OFF2_M1 , T OFF2_M2 , T OFF2_M3 is the duration between time E1, E2, E3 and time C. In system 100 ( Figure 1 ), the switch controller and driver circuit system 120 in the master switch unit 110 or the slave switch units 111, 112 can use the occurrence time of time D1, D2, D3, E1, E2, E3 and time C to calculate the turn-off time T OFF1_M1 , T OFF1_M2 , T OFF1_M3 , T OFF2_M1 , T OFF2_M2 , T OFF2_M3 .

[0074] although Figure 2A-2D Only based on the collector to emitter voltage V CE The time required to fall or rise to one or more threshold voltage levels is plotted. In other embodiments, the collector-to-emitter voltage V at one or more defined times is plotted. CE The value can be used based on the V CE The sensing information determines the current carrying behavior of the IGBT. For example, after one or more times defined relative to the turn-on command 205 or the turn-off command 220, the collector-to-emitter voltage V in different IGBTs may be measured. CE . Collector to emitter voltage V CE1 、V CE2 、V CE3 An increase or decrease in current will be reflected in these voltage measurements and information about the current carrying behavior of the individual IGBTs can be identified.

[0075] Figure 3 300 is a schematic representation of an embodiment of a switch unit 300. The switch unit 300 may be part of a system in which switching of different power switches is coordinated, such as the system 100 ( Figure 1 ) in the switch units 110, 111, 112. For simplicity, the switch unit 300 as described acts as a master switch unit that interfaces with the system controller and coordinates the switching of any slave switch units.

[0076] The switch cell 300 includes one or more IGBT power switches 115 and switch controller and driver circuitry 120. The switch controller and driver circuitry 120 includes external switch cell communication circuitry 122 and internal switch cell communication circuitry 125 that can communicate with the system controller and slave switch cells via channels 117, 130.

[0077] In the illustrated embodiment of the switch unit 300, the control and communication interface circuit system portion 305 is galvanically isolated from the driver circuit system portion 310. The portions 305, 310 communicate across the galvanic barrier using respective transceivers 315, 320. The transceivers 315, 320 can be implemented to communicate using, for example, optocouplers, transformers, coupled lead frames, capacitors, and associated switch circuit systems. Again, bidirectional communication can be implemented using a bidirectional channel and / or multiple unidirectional channels.

[0078] In addition to transceiver 320 , driver circuitry portion 310 also includes VCE measurement circuitry 325 , switch driver control circuitry 330 , pull-up transistor 331 , and pull-down transistor 332 .

[0079] VCE measurement circuitry 325 is coupled to VCE sense line 135 and is configured to measure the collector-to-emitter voltage V CE The time required to reach the threshold or the collector-to-emitter voltage V after the defined time CE The time measurement may be implemented using, for example, a voltage or current comparator, and the voltage or current level measurement may be implemented using, for example, a timer circuit system and an analog-to-digital converter that senses the collector-to-emitter voltage V on the sense line 135 in response to a trigger from the timer circuit system. CE Regardless of the implementation details, VCE measurement circuitry 325 is configured to communicate information representative of the measured time or voltage level to transceiver 320, typically on a switching cycle-by-switching cycle basis.

[0080] Incidentally, the information on the VCE sense line 135 will typically be used to implement additional control functions (eg, over-current protection, over-voltage protection).

[0081] The switch driver control circuitry 330 is configured to control the driving of the IGBT power switch 115 by switching the pull-up transistor 331 and the pull-down transistor 332 into and out of conduction. In the illustrated embodiment, this will alternately couple:

[0082] - coupling a voltage that is positive with respect to the emitter voltage of the IGBT power switch 115 (ie, VPOS) to the high output terminal GH and a gate resistor, which in turn is coupled to the gate of the IGBT power switch 115, and

[0083] A voltage that is negative with respect to the emitter voltage of the IGBT power switch 115 , ie VPNEG, is coupled to the low output terminal GL and a gate resistor, which in turn is coupled to the gate of the IGBT power switch 115 .

[0084] Other implementations are possible. For example, in some implementations, the pull-down transistor 332 couples the emitter of the IGBT power switch 115 to the gate of the IGBT power switch 115. As another example, in some implementations, a single output terminal and gate resistor are used. In another example, a current source gate driver output stage is used. As another example, in some implementations, the timing adjustment is implemented by a driver controller.

[0085] Control and communication interface circuitry portion 305 includes both external switch cell communication circuitry 122 and internal switch cell communication circuitry 125 and transceiver 315 .

[0086] The external switch unit communication circuit system 122 includes a communication interface 335, which can communicate with components outside the switch unit using one or more communication protocols. For example, the information that the communication interface 335 can receive includes a system switching command 336. The system switching command 336 indicates that the system 100 ( Figure 1 )'s desired state for all IGBT switches 115 in the system.

[0087] The internal switch unit communication circuit system 125 includes a communication interface 340, which can communicate with other switch units using one or more communication protocols. For example, in some embodiments, the system switching command 336 received at the communication interface 335 is simply relayed to other switch units via the communication interface 340. In some embodiments, the system switching command 336 sent to other switch units is frequency encoded. For example, a relatively high frequency AC clock signal can indicate that all switch units will be in the on state, while an AC clock signal with a distinguishable frequency (e.g., 1 / 10 to 1 / 2 or 2 to 10 times the frequency, indicating that all switch units will be in the on state) can indicate that all switch units will be in the off state. Such encoding is robust in the case of power switches. Specifically, even if the transition between frequencies of the system switching command 336 is obscured by noise, the signal that can be interpreted by the communication interface 335 will be quickly decoded, and the communication interface 335 will respond accordingly.

[0088] As another example of communication between the communication interface 340 and other switch units, as discussed in more detail below, a frame-based communication protocol may be used to receive collector-to-emitter voltages V of other power switches during switching transitions. CE The SENSE_OFF signal 341 represents the collector-to-emitter voltage V of the other power switches during the transition from the on state to the off state. CE , the SENSE_ON signal 342 represents the collector-to-emitter voltage VCE of the other power switches during the transition from the off state to the on state, the ADJ_ON signal 343 represents the adjustment to be made to the switch timing for the transition to the on state, and the ADJ_OFF signal 344 represents the adjustment to be made to the switch timing for the transition to the off state.

[0089] In some embodiments, the timing adjustment represented by signals 343, 344 and transmitted to the slave switch unit can be made according to the number of cycles of the clock signal encoding the system switching command 336. For example, assume that the system switching command 336 encodes the on state using a 100 MHz clock signal. The rising and falling edges of the clock signal occur every 5 nanoseconds. Signals 343, 344 can make a timing adjustment of 20 nanoseconds as four transitions / / two clock cycles.

[0090] Relatively fine adjustments to the timing of switch transitions in switch unit 300 and / or other switch units in the system may be made by switch unit 300 itself, by external circuitry (e.g., system controller 105 ( Figure 1 )) or determined by both the switch unit 300 and the external circuit system.

[0091] In embodiments where external circuitry is involved in determining fine adjustments, the communication interface 335 may also transmit a sensed information signal 337 to the external component, which represents the collector-to-emitter voltage V of the other power switches sensed during the switch transition. CE The communication interface 335 may also receive an adjustment information signal 338 from an external component that characterizes a relatively fine adjustment to be made to the timing of switch transitions in other switch cells. Thus, the sensing information signal 337 may include at least some of the information content of the SENSE_ON signal 342 and the SENSE_OFF signal 341, as well as a voltage V representing the collector to emitter voltage of the IGBT in the switch cell 300 during its transition. CEFurthermore, the adjustment information signal 338 may include at least some of the information content of the ADJ_ON signal 343 and the ADJ_OFF signal 344 , as well as comparable information characterizing relatively fine adjustments to be made to the timing of the switch transitions in the switch unit 300 .

[0092] In embodiments where switch cell 300 participates in determining fine adjustments, switch cell 300 includes timing adjustment determination circuitry 345. Timing adjustment determination circuitry 345 is circuitry configured to determine relatively fine adjustments to be made to the timing of switch transitions in the system's switch cells, including switch cell 300 as appropriate. For example, timing adjustment determination circuitry 345 may be implemented using a digital clock within an ASIC and may be configured by registers.

[0093] Whether the timing adjustment is determined by timing adjustment determination circuitry 345 or external circuitry, the timing adjustment may be designed to achieve a desired current distribution among the power switches of the system.

[0094] In some embodiments, the adjustments are designed to gradually approach the desired current distribution over multiple switching cycles. By way of example, Tables 1-3 illustrate an example set of timing adjustments designed to achieve a desired current distribution by ensuring that the collector-to-emitter voltage V CE Balanced current sharing is achieved by exceeding a single voltage threshold level at approximately the same time during the transition to the on-state. Comparable timing adjustments can be made for the transition to the off-state. Furthermore, comparable timing adjustments can be designed to ensure that the collector-to-emitter voltage V at some time after the transition has begun is approximately the same. CE is substantially the same to achieve balanced current sharing. In other embodiments, multiple voltage threshold levels or multiple times after the transition may be used.

[0095] Table 1 illustrates example data for a first switching cycle. The first switching cycle may be the first cycle after startup, after a system reset, etc. In this embodiment, there is no predefined timing adjustment for the first switching cycle, and the cumulative adjustment for all switching units is initially zero. This need not be the case, and in some embodiments, even the first cycle after startup or after a system reset may have a predefined adjustment.

[0096] In any case, the sensed collector-to-emitter voltage V CEExamples of times when the voltage threshold level is exceeded are set forth in the column labeled "crossing time." In some embodiments, the crossing time may be measured relative to the time when the system switching command 336 is received by the switch unit 110, 111, 112 via the channel 130. Figure 2A and Figure 2B In the case of a , the excess time will be measured from index A 205. Figure 2C and Figure 2D In the case of , the exceed time will be measured from index C 220. In other embodiments, the exceed time may be measured relative to the time when the system switching command 336 received by the master switch unit from the system controller indicates that the transition is to occur.

[0097] In Table 1, the unit of time is arbitrary, but in some embodiments may be in nanoseconds. As shown, the collector-to-emitter voltage V in different switch units CE There is some variation in the time when the voltage threshold level is exceeded. For example, although the average exceeding time is approximately 104 time units, the first slave switch unit exceeds the voltage threshold level earlier and the third slave switch unit exceeds the voltage threshold level later. The first slave switch unit will conduct more current than the third slave switch unit, and the current distribution may be relatively unbalanced.

[0098] As for the timing adjustment itself, the slowest power switch is in the third slave switch unit. The third slave switch unit can act as a reference switch unit, and the adjustments for the other switch units can be designed to ensure that the collector to emitter voltage V CE The voltage threshold level is exceeded at the same time as the reference. In addition, although the adjustments for the other switch units are designed to distribute the current more evenly, the adjustments are determined with the understanding that the desired current distribution may only be achieved gradually over multiple switching cycles. For example, the timing adjustment for the first slave switch unit is 10 units, even though the power switch of the first slave switch unit exceeds the voltage threshold level 30 units earlier than the power switch of the third slave switch unit.

[0099] The gradual multi-cycle approach to the desired current distribution can be implemented in a variety of different ways. For example, in some embodiments, the size of the adjustment allowed can be limited in range. In such a case, even if the size of the difference between the switching cells is large, multiple switching cycles will be required to approach the desired current distribution. As another embodiment, the size of the adjustment can be limited to a certain small fraction of the size of the difference between the switching cells. As yet another embodiment, a combination of these and other techniques can be used. In any case, the direction of the adjustment is designed to achieve the desired current distribution, i.e., to make the current distribution more uniform when the current sharing is to be balanced, or to achieve a desired uneven distribution when the current sharing is to be unbalanced.

[0100]

[0101] Table 1

[0102] Table 2 illustrates example data for the second switching cycle. In this illustrative embodiment, the second switching cycle immediately follows the first switching cycle, i.e., the timing adjustment is applied on a switching cycle-by-switching cycle basis. This need not be the case. For example, in other implementations, the timing adjustment may be made after a number of cycles have passed, or may be made only when there is a threshold level of difference between the exceeded times.

[0103] Returning to Table 2, the accumulated adjustments for all switching cells are those that are set after the first switching cycle. After applying those adjustments, the collector-to-emitter voltage V CE The time when the voltage threshold level is exceeded. As shown, there is no one-to-one correspondence between the timing adjustment implemented and the change in the exceed time. For example, the timing adjustment for the main switching unit after the first switching cycle is 10 units. However, the change in the exceed time is only 5 units (i.e., the exceed time goes from 100 units to 105 units). Such a difference can be caused by a variety of different reasons. For example, in the VCE sense line 135 ( Figure 1 ). Related devices may have different temperature / voltage / current related tolerances. The resolution of measurement and adjustment may be different. In addition, some portion of the excess time may be attributed to factors that have a one-to-one correspondence with the time when the switch transition begins, and other portions may be attributed to factors that do not have a one-to-one correspondence. For example, the transmission delay for a switch unit that is relatively far from the main switch unit can be compensated on a one-to-one basis by delaying the transition of a switch unit that is relatively closer to the main switch unit. On the other hand, the collector-to-emitter voltage V in different switch units is different from the collector-to-emitter voltage V in different switch units. CEThe difference in slope or shape may not be compensated on a one-to-one basis. In any case, the variation in the exceedance time for a given switch unit may be greater than the timing adjustment (as in the second and fourth slave switch units) or less than the timing adjustment (as in the master, first and fifth slave switch units).

[0104] As for the timing adjustment itself, the third slave switch unit is still the reference switch unit. However, the exceed time of the third slave switch unit has become faster, and both the second and fourth slave switch units exceed the voltage threshold level after the third slave switch unit. There may be several reasons for the earlier exceed time of the third slave switch unit, including, for example, temperature changes or noise that affect the third slave switch unit's reception of the system switching command.

[0105] In any case, the new adjustment is still determined with reference to the third slave switch unit. The second and fourth slave switch units both have negative timing adjustments, while the master switch unit and the first slave switch unit have positive timing adjustments. The collector-to-emitter voltage V CE The collector-to-emitter voltage V CE The voltage threshold is exceeded at the same time and no adjustment is applied.

[0106]

[0107] Table 2

[0108] Table 3 illustrates example data for the third switching cycle. The accumulated adjustments for all switch cells are those set after the second switching cycle. After those adjustments are applied, the sense collector to emitter voltage V CE The time when the voltage threshold level is exceeded. As shown, the collector-to-emitter voltage V CE The times for exceeding the voltage threshold level are almost identical, with only the exceeding time of the fourth slave switching unit deviating from the reference. A timing adjustment for the next switching cycle can also be determined.

[0109]

[0110] Table 3

[0111] Figure 4 1 is a swim lane diagram representing operations in a system in which the switching of different power switches is coordinated. The left swim lane represents operations performed by a main switch unit in such a system. For example, the operations in the left swim lane may be performed by switch units 110, 300 ( Figure 1 , Figure 3) is performed. The right lane represents operations performed by the slave switch units in such a system. For example, the operations in the right lane may be performed by the switch units 111, 112 ( Figure 1 ) is performed. In addition, the operation performed on the primary side of the switching unit is surrounded by a relatively thin line, and the operation performed on the secondary side of the switching unit is surrounded by a relatively thick line.

[0112] For purposes of illustration, it is assumed that all turn-on adjustments are determined by the main switch unit. However, as discussed above, this is not necessarily the case. In addition, it represents ongoing operations, rather than operations immediately after, for example, startup or reset. In the case of the timing adjustments discussed in Tables 1-3, Figure 4 The operations in may represent the second (Table 2) or any subsequent switching cycle.

[0113] At 402, the main switch unit receives a system on command. The system on command is a system switching command that instructs the IGBT switches in the system to be in the on state.

[0114] At 404, the master switch unit transmits a system on command to one or more slave switch units in the system. The system on command also loops back to the master switch unit. In one embodiment, the loop back can compensate for the propagation delay to one or more slave switch units.

[0115] In addition, the main switch unit applies its own timing adjustment (e.g., the accumulated timing adjustment in Table 2, Table 3) to the system conduction command. In the illustrated embodiment, the timing adjustment for the main switch unit is applied to the primary side of the main switch unit at 406, and the adjusted conduction command is transmitted to the secondary side of the main switch unit across the galvanic isolation barrier at 408. In other embodiments, the unadjusted conduction command is transmitted across the galvanic isolation barrier, and the timing adjustment for the main switch unit is applied at the secondary side. To ensure identification of this option, the application of the timing adjustment for the main switch unit is surrounded by a relatively thin dashed line, and the transmitted conduction command is represented as an "adjusted conduction command".

[0116] Continuing with the main switch unit, at 410, the secondary side of the main switch unit receives the adjusted on command and turns on the switch according to the adjusted on command - regardless of where the adjustment is applied. At 412, the collector-to-emitter voltage V CE The correlation of the time required to drop to the threshold voltage level or the collector-to-emitter voltage V at the defined time CE At 414, the measured time or value is transmitted across the isolation barrier from the secondary side to the primary side of the main switching unit.

[0117] At 416, the primary side of the master switching unit receives both measured times or values ​​from its own secondary side and one or more measured times or values ​​from the slave unit(s) in the system.

[0118] At 418, the master switching unit determines any new adjustments to be applied to the on command, and transmits those new adjustments to the slave unit(s) in the system at 420. In embodiments where the adjustments are applied at the secondary, any new adjustments for the master switching unit must be transmitted to the secondary side.

[0119] Turning to the slave unit(s), at 450 , the slave switching unit receives the system on command transmitted by the master switching unit.

[0120] In the illustrated embodiment, the timing adjustment for the slave switching cell is applied on the primary side of the slave switching cell at 452, and the adjusted on command is transmitted across the galvanic isolation barrier to the secondary side of the master switching cell at 454. As with the master switching cell, this need not be the case.

[0121] At 456, the adjusted on-command is received from the secondary side of the switch cell, and the switch is turned on according to the adjusted on-command, regardless of where the adjustment is applied. At 458, the collector-to-emitter voltage V CE The correlation of the time required to drop to the threshold voltage level or the collector to emitter voltage V at the defined time CE At 460, the measured time or value is transmitted across the isolation barrier from the secondary side to the primary side of the switching unit.

[0122] At 462, the primary side of the slave switching unit receives the measured time or value from the secondary side. At 464, the slave switching unit transmits the measured time or value to the master switching unit.

[0123] At 470 , the slave switching unit receives a new adjustment from the master switching unit to be applied to the on-command.

[0124] Figure 5 5 is a schematic representation of the structure of a bus 500 that can be used to implement a communication channel between a master switch unit 505 and one or more slave switch units 510 in a system in which the switching of different power switches is coordinated. For example, the bus structure 500 can be used to implement the communication channel 130 ( Figure 1 ).

[0125] The illustrated embodiment of the bus structure 500 includes a pair of system command lines 515 and a pair of data communication lines 520. The system command lines 515 provide a channel for the communication of system commands. The system command lines 515 are implemented as differential transmission lines and are terminated by terminal resistors 518. The terminal resistors 518 may include the inherent resistance of the components in the switch unit 510 (e.g., the input impedance of the (one or more) receivers in the switch unit 510) and a fixed or variable resistance coupled with the component resistance to define the terminal resistance 518 "seen" by the signal propagating on the system command lines 515. In some embodiments, the terminal resistance is a variable terminal resistance and is programmable based on the wave impedance of the cable used in the system command lines 515.

[0126] At least the master switch unit 505 includes a differential transmitter 525 coupled to the system command line 515 , and the slave switch unit(s) 510 each include a differential receiver 527 coupled to the system command line 515 .

[0127] Communication line 520 provides a time-division channel for the communication of data and commands. The data communicated may include the collector-to-emitter voltage V of the switch cell during the switching transition. CE The derived time or value, and the signal representing the relatively fine adjustment to be made to the timing of the switch transition. The instructions communicated may include initialization and reset commands, instructions to sense the collector to emitter voltage V CE A command for the time or value derived therefrom, as well as a command for setting the value of the terminating resistor 518 and the values ​​of the terminating resistors 522 , 524 terminating the communication line 520 , is transmitted on the communication line 520 .

[0128] The master switch unit 505 includes a differential transmitter 530 and a receiver 535 coupled to the communication line 520. The slave switch unit(s) 510 each include a differential receiver 532 and a receiver 537 coupled to the system command line 520.

[0129] As discussed above, in a system that coordinates the switching of different power switches, the number of slave switch units 510 may vary. Furthermore, in some applications, it would be desirable to make relatively fine adjustments to the timing of switching transitions in individual switches on a switching cycle-by-switching cycle basis.

[0130] In operation, the bus 500 may implement a high frequency communication channel between the master switch unit 505 and a variable number of slave switch units 510 to coordinate switching. For example, the master switch unit 505 may receive a command from the system controller indicating that switching is to be coordinated, for example, to achieve a desired balanced or unbalanced current sharing. In response, the master switch unit 505 may broadcast a command on the data communication line 520 that commands any slave switch unit 510 on the data communication line 520 to reset and respond with a signal identifying their presence. Arbitration between the slave units is not important at this time, but may be implemented here or during a subsequent exchange.

[0131] After receiving confirmation that at least one slave switch unit 510 exists, the master switch unit 505 can broadcast an initialization command on the communication line 520. The slave switch units 510 on the communication line 520 can respond to the initialization command using identification information. For example, in some embodiments, any slave switch units 510 that exist can arbitrate for time slots on the communication line 520 and respond using their corresponding MAC addresses. If necessary, the slave switch units 510 can be assigned short-form addresses and notified of their short-form addresses.

[0132] Once the slave switch unit 510 is identified, a frame-based communication protocol can be used to address the individual slave switch unit 510. Each frame may include, for example, the address of the addressed slave switch unit 510, the identification of the command being transmitted in the frame, and data related to the command. As needed, a start sequence, an error detection and correction sequence (e.g., a cyclic redundancy check block), information describing the size of the frame, and other information may also be included.

[0133] Among the commands that can be sent from the main switch unit 505 are:

[0134] - The slave switch unit 510 will start transmitting the collector-to-emitter voltage V CE signals (e.g., SENSE_OFF signal 341 and SENSE_ON signal 342 ( Figure 3 )) command, and

[0135] - A command to apply certain timing adjustments. For example, a timing adjustment command may include data characterizing the magnitude of those timing adjustments.

[0136] In addition, the commands that can be sent from the main switch unit 505 include commands to set the values ​​of the terminal resistors 518, 522, 524. In some embodiments, the commands to set the values ​​of the terminal resistors 518, 522, 524 are based on user input information about the system. For example, a user may be able to input information about the impedance of the (one or more) cables implementing the lines 515, 520. In some cases, measurements made on the lines 515, 520 can also be used - alone or in combination with user input - to set the values ​​of the terminal resistors.

[0137] In some embodiments, the measurements performed on the lines 515, 520 may include determining which of the slave switch units 510 is furthest from the master switch unit 505 in terms of propagation delay. After identifying the furthest switch unit 510, the furthest switch unit 510 may be commanded to set its termination resistance to reduce or eliminate signal reflections and distortion.

[0138] In some embodiments, a baseline of reflections may be measured first. For example, one or both of the differential transmitters 525, 530 in the main switch unit 505 may transmit (one or more) measurement signals. One or both of the receivers on the system command line 515 (not shown) in the receiver 535 and the main switch unit 505 may measure the reflections along the lines 515, 520 that occur due to each impedance mismatch. This comparison of the transmitted signal and the reflected signal provides a baseline measurement indicating the impedance mismatch in the absence of any adjustment to the terminal resistors 518, 522, 524.

[0139] Before or after measuring the baseline, each of the slave switch units 510 on lines 515, 520 may be addressed individually or sequentially with commands to set the values ​​of the termination resistors 518, 522, 524. The effects of those settings on the same reflected signal may be used to attribute the reflection to the respective slave switch unit 510.

[0140] In some embodiments, the master switch unit 505 can command each of the corresponding slave switch units 510 to short and open the switch unit's connections to the lines 515, 520. In the event of a short or open connection, the master switch unit 505 can measure reflections along the lines 515, 520 and attribute those reflections to the corresponding slave switch unit 510. The reflection that occurs the latest in time will be attributed to the slave switch unit 510 that is farthest from the master switch unit 505. For illustration, Figure 5 The slave switch unit 510 on the right in the schematic illustration (ie, the slave switch unit 10 including the terminal resistors 518 , 524 ) will be assumed to be the slave switch unit 510 farthest from the master switch unit 505 .

[0141] After identifying the slave switch unit 510 farthest from the master switch unit 505, a command to set the value of the terminal resistors 518, 524 can be sent to the slave switch unit 510. In some embodiments, an empirical process can be used to determine the appropriate values ​​of the terminal resistors 518, 524, in which the master switch unit 505 performs multiple transmissions and measures multiple reflections. For example, a range of impedances can be swept or the impedance can be gradually adjusted until only acceptable reflections exist.

[0142] In some embodiments, the terminal resistors 518, 524 may only be set to pre-assigned terminal values. For example, terminal values ​​that include common cable impedances (eg, 50Ω, 75Ω, 100Ω, 125Ω, and 150Ω) may be pre-assigned.

[0143] A variety of embodiments have been described. However, it will be appreciated that a variety of modifications may be made. For example, the communication channels may be implemented as wired and / or wireless connections. The communication paths established by these connections may be divided in time, frequency, phase, or other aspects. Even in high power switching applications, loss of switching commands may be avoided in a variety of ways. For example, optical techniques may be used to transmit signals. Therefore, other embodiments are within the scope of the appended claims.

[0144] The present invention is defined in the claims; however, it is to be understood that the invention may alternatively be defined according to the following examples.

[0145] Embodiment 1. A power switch system comprises: a plurality of power switch units, each power switch unit comprising a corresponding power switch; a communication system configured to transmit a system-wide switching command to the power switch unit along a communication channel; and a circuit system included in each of the power switch units, configured to delay the execution of the system-wide switching command by a delay time.

[0146] Embodiment 2. The power switch system according to embodiment 1, wherein the delay time is between 0 and 1000 nanoseconds.

[0147] Embodiment 3. The power switch system of Embodiment 1 or 2, wherein the delay time is a fraction less than one of an intrinsic rise time or a fall time of a control terminal of a corresponding power switch in the power switch system.

[0148] Embodiment 4. A power switching system according to any one of embodiments 1 to 3, wherein the power switching system includes a circuit system for determining the size of a delay time, which will be applied by at least some of the multiple power switching units to the execution of the system-wide switching command.

[0149] Embodiment 5. The power switching system of Embodiment 4, wherein the circuit system for determining the magnitude of the delay time is configured to determine the magnitude of the delay time on a switching cycle by switching cycle basis.

[0150] Embodiment 6. A power switching system according to embodiment 4, wherein: each of the power switching units includes a sensing circuit system configured to sense the voltage between main terminals; and the circuit system for determining the size of the delay time includes: a circuit system for comparing the following time: the time required for the voltage sensed at different power switching units to reach or exceed a threshold during a switching transition in response to a previous system-wide switching command, or a circuit system for comparing the following values: the value of the voltage sensed at different power switching units at a time defined with respect to a previous system-wide switching command.

[0151] Embodiment 7. A power switching system according to embodiment 6, wherein each of the plurality of power switching units comprises a synchronizable clock configured to generate a clock signal, and wherein each of the power switching units is configured to use the synchronized clock signal as a reference for the following times: the time required for a voltage sensed at different power switching units to reach or exceed a threshold, or the time defined by a previous system-wide switching command.

[0152] Embodiment 8. A power switching system according to embodiment 6, wherein the circuit system for determining the size of the delay time is configured to determine the delay time, which reduces the difference between the time required for the voltage sensed at different power switching units to reach or exceed the threshold, or reduces the difference between the values ​​of the voltage sensed at the time.

[0153] Embodiment 9. A power switching system according to any one of embodiments 1 to 8, wherein the system-wide switching command is a clock signal with different frequencies; and the delay time is represented in the communication between the power switching units as a period of one of the frequencies of the clock signal.

[0154] Embodiment 10 The power switching system of Embodiment 1, wherein a magnitude of a delay time for delaying execution of the system-wide switching command is different in each of the plurality of power switching units.

[0155] Embodiment 11. A power switch system, comprising: a communication bus; a master power switch unit and a plurality of slave power switch units coupled to the communication bus, wherein each of the master power switch unit and the slave power switch units comprises: a power switch; a sensing circuit system configured to sense a voltage between main terminals of the power switch; and a communication interface coupled to the communication bus, and wherein each of the slave power switch units comprises a control circuit system configured to transmit a signal including information representing the sensed voltage to the master power switch unit using the communication interface, and wherein the power switch system comprises a circuit system configured to: receive information representing a voltage sensed at the slave power switch unit, and compare the voltage sensed at the slave power switch unit with a voltage sensed between main terminals at the power switch of the master power switch unit to determine an adjustment to be applied to a switching transition by a first of the slave power switch units during a subsequent switching cycle, and further, wherein the master power switch unit comprises a circuit system for using the communication interface and transmitting a signal representing the adjustment to the first of the slave power switch units.

[0156] Embodiment 12. The power switch system of Embodiment 11, wherein the delay time is between 0 and 1000 nanoseconds.

[0157] Embodiment 13 The power switch system of Embodiment 11 or 12, wherein the delay time is a fraction less than one of an intrinsic rise time or a fall time of a control terminal of a corresponding power switch in the power switch system.

[0158] Embodiment 14. According to any one of Embodiments 11 to 13, the power switching system further includes a system controller, which is configured to provide a system-wide switching command, the system-wide switching command indicating the desired on-state or off-state of the master power switch unit and the multiple slave power switch units, and the adjustment will be applied to the system-wide switching command.

[0159] Embodiment 15. The power switching system of Embodiment 14, wherein the system controller includes the circuitry configured to receive information indicative of voltages sensed at the slave power switching units and compare the sensed voltages to determine the adjustment.

[0160] Embodiment 16 The power switch system of Embodiment 14, wherein the adjusting is configured to reduce a delay time between the system-wide switching command and execution of the system-wide switching command by at least one power switch.

[0161] Embodiment 17. A method, comprising: sensing voltage between main terminals of multiple power switches in a power switch system; determining one of the following: the time required for the sensed voltage to reach or exceed a threshold during a switch transition in response to a system-wide switching command, or the value of the sensed voltage at a time defined with respect to the system-wide switching command; for a first power switch among the power switches in the power switch system, determining an adjustment that will be applied to the execution of the system-wide switching command in a subsequent switching cycle; and applying, at a driver of the first power switch, the adjustment to the execution of the system-wide switching in the subsequent switching cycle.

[0162] Embodiment 18. The method of Embodiment 17, wherein the subsequent switching cycle is the next immediately subsequent switching cycle.

[0163] Embodiment 19 The method of Embodiment 17 or 18, wherein the adjustment is determined to unbalance currents carried by the power switches in the power switch system.

[0164] Embodiment 20 The method of any one of Embodiments 17 to 19, wherein the adjusting is configured to reduce a delay time between the system-wide switching command and execution of the system-wide switching command by at least one power switch.

[0165] Embodiment 21. The method of any one of embodiments 17 to 20, wherein the adjustment is between 0 and 1000 nanoseconds.

[0166] Embodiment 22 The method of any one of Embodiments 17 to 21, wherein the delay time is a fraction less than one of an intrinsic rise time or a fall time of a control terminal of a corresponding power switch in the power switch system.

[0167] Embodiment 23. A method according to any one of Embodiments 17 to 22, wherein the method further comprises: for a second power switch among the power switches in the power switch system, determining a second adjustment to be applied to the execution of the system-wide switching command in the subsequent switching cycle, wherein the first adjustment is different from the second adjustment; and at a driver of the second power switch, applying the adjustment to the execution of the system-wide switching in the subsequent switching cycle.

[0168] Embodiment 24. The method of any one of Embodiments 17 to 23, wherein the system-wide switching command is a clock signal having a different frequency; and the adjustment is expressed in terms of a period of one of the frequencies of the clock signal.

[0169] Embodiment 25. A method according to any one of embodiments 17 to 24, wherein the time required for the sensed voltage to reach or exceed the threshold or the time defined by the system-wide switching command is referenced to the following clock signal: the clock signal is synchronized with the clock signals of other power switches in the power switch system.

[0170] Embodiment 26. A power switch unit, comprising: a power switch; a sensing circuit system configured to sense a voltage between main terminals of the power switch; and a communication interface configured to be coupled to a communication bus; a circuit system, the circuit system being configured to: receive information representing voltages sensed at multiple other power switch units, and compare the voltages sensed at the other power switch units with the voltages sensed between the main terminals of the power switch to determine adjustments to be applied to switching transitions by the other power switch units during subsequent switching cycles; and a circuit system for using the communication interface and transmitting a signal representing the adjustment to the other power switch units.

Claims

1. A power switch system, comprising: A plurality of power switch units coupled in parallel, each of the power switch units comprising: The corresponding power switches, and sensing circuitry configured to sense a voltage between main terminals of a corresponding power switch; a communication system configured to transmit a system-wide switching command to the power switch unit along a communication channel; A circuit system for determining the size of a delay time to be applied by the plurality of power switch units to the execution of the system-wide switching command, wherein each of the delay times is customized for a corresponding power switch unit, and the circuit system for determining the size of the delay time comprises: Circuitry for comparing the time required for voltages sensed at different power switching units to reach or exceed a threshold during a switching transition in response to a previous system-wide switching command, or Circuitry for comparing values ​​of voltages sensed at different power switching units at times defined with respect to a previous system-wide switching command, and Circuitry is included in each of the power switch units, the circuitry being configured to delay execution of the system-wide switching command by a delay time customized for the power switch unit. 2 . The power switching system of claim 1 , wherein the circuitry for determining the magnitude of the delay time is configured to determine the magnitude of the delay time on a switching cycle by switching cycle basis.

3. The power switching system of claim 1 , wherein each of the plurality of power switching units comprises a synchronizable clock configured to generate a clock signal, and wherein each of the power switching units is configured to reference the following times to the synchronized clock signal: the time required for the voltage sensed at the different power switching units to reach or exceed the threshold, or The time limit relative to the previous system-wide switch command.

4. A power switching system according to claim 3, wherein the circuit system for determining the size of the delay time is configured to determine the delay time, which reduces the difference between the times required for the voltages sensed at different power switching units to reach or exceed the threshold, or reduces the difference between the values ​​of the voltages sensed at the times.

5. The power switch system according to claim 1, wherein: The system-wide switching command is a clock signal having a different frequency; and The delay time is expressed as a period of one of the frequencies of the clock signal in the communication between the power switch units. 6 . The power switching system of claim 1 , wherein a magnitude of a delay time that delays execution of the system-wide switching command is different in each of the plurality of power switching units.

7. The power switch system according to claim 1, wherein: The communication system includes a communication bus; The plurality of power switch units include a master power switch unit and a plurality of slave power switch units coupled to the communication bus, wherein each of the master power switch unit and the slave power switch unit includes: Power switch, sensing circuitry configured to sense a voltage between main terminals of the power switch, and a communication interface coupled to the communication bus, and Each of the slave power switch units includes: a control circuit system configured to transmit a signal including information representing the sensed voltage to the master power switch unit using the communication interface, and wherein the power switch system comprises: a circuit system configured to: receive information characterizing a voltage sensed at the slave power switch unit and compare the voltage sensed at the slave power switch unit with a voltage sensed between master terminals at the power switch of the master power switch unit to determine an adjustment to be applied to a switching transition by a first one of the slave power switch units during a subsequent switching cycle, wherein the adjustment is customized for the first one of the slave power switch units, and Further, the master power switch unit includes a circuit system for using the communication interface and transmitting a signal representing the adjustment to the first slave power switch unit among the slave power switch units.

8. The power switching system according to claim 7 further includes a system controller, which is configured to provide a system-wide switching command, the system-wide switching command indicating the desired on-state or off-state of the master power switching unit and the multiple slave power switching units, and the adjustment will be applied to the system-wide switching command. 9 . The power switching system of claim 8 , wherein the system controller includes the circuitry configured to receive information indicative of voltages sensed at the slave power switching units and compare the sensed voltages to determine the adjustment. 10 . The power switch system of claim 8 , wherein the adjusting is configured to reduce a delay time between the system-wide switching command and execution of the system-wide switching command by at least one power switch.

11. The power switch system of claim 1 , wherein: a) the adjustment is between 0 and 1000 nanoseconds; or b) the delay time is a fraction less than one of an inherent rise time or a fall time of a control terminal of a corresponding power switch in the power switch system; or c) Both a) and b).

12. A method comprising: sensing a voltage between main terminals of a plurality of power switches coupled in parallel in a power switching system; Sure: The time required for the sensed voltage to reach or exceed a threshold during a switching transition in response to a system-wide switching command, or a value of a voltage sensed at a time defined with respect to said system-wide switching command; determining, for a first one of the power switches in the power switch system, an adjustment to be applied to execution of the system-wide switching command in a subsequent switching cycle, wherein the adjustment is customized for the first one of the power switches, and The adjustment is applied, at a driver of the first power switch, to execution of the system-wide switching in the subsequent switching cycle.

13. The method according to claim 12, wherein: a) the subsequent switching cycle is the next immediately subsequent switching cycle; or b) the adjustment is determined to unbalance currents carried by the power switches in the power switching system; or c) Both a) and b).

14. The method of claim 12, wherein the adjusting is configured to reduce a delay time between the system-wide switching command and execution of the system-wide switching command by at least one power switch.

15. The method of claim 12, wherein: a) the adjustment is between 0 and 1000 nanoseconds; or b) the delay time is a fraction less than one of an inherent rise time or a fall time of a control terminal of a corresponding power switch in the power switch system; or c) Both a) and b).

16. The method according to claim 12, wherein the method further comprises: determining, for a second power switch of the power switches in the power switching system, a second adjustment to be applied to execution of the system-wide switching command in the subsequent switching cycle, wherein the first adjustment is different from the second adjustment; as well as The adjustment is applied at a driver of the second power switch to the execution of the system-wide switching in the subsequent switching cycle.

17. The method according to claim 12, wherein The system-wide switching command is a clock signal having a different frequency; and The adjustment is expressed in terms of a period of one of the frequencies of the clock signal.

18. The method of claim 12, wherein the time required for the sensed voltage to reach or exceed the threshold or the time defined by the system-wide switching command is referenced to a clock signal that is synchronized with clock signals of other power switches in the power switch system.

Images