Method for reducing packet loss rate of gigabit Ethernet network based on clock homologous design

By designing a clock homologous solution in the main control device, the problem of high packet loss rate of the SGMII interface between KD5886 and E2000D is solved, and the stability and efficiency of network data communication are achieved.

CN119766376AActive Publication Date: 2025-04-04BEIJING INST OF COMP TECH & APPL
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Patent Information

Application Number
CN202411688935.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-25
Publication Date
2025-04-04
Estimated Expiration
2044-11-25

AI Technical Summary

Technical Problem

The SGMII interface between KD5886 and E2000D will experience packet loss when pinging packets, and the network packet loss rate is as high as 50%, seriously affecting data integrity and the accuracy of data exchange.

Method used

By designing a clock homologous solution in the main control device, the clock input sources of the E2000D chip, the KD5886 chip and other load devices are designed as homologous clocks, ensuring that the clock frequency of the SGMII interface is consistent, thereby reducing the network packet loss rate.

Benefits of technology

Through the clock homologous design, the network packet loss rate of the SGMII interface is significantly reduced, the effective data transmission rate is improved, and the dual evasion strategy is adopted in the firmware layer and the application layer to reduce the packet loss rate to 0%.

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Abstract

The invention relates to a method for reducing the packet loss rate of a gigabit Ethernet network based on clock homology design, and belongs to the field of computer networks. Clock input sources of the E2000D chip, the KD5886 chip and other load equipment are designed to be homologous clocks, so that the network packet loss rate of an SGMII gigabit Ethernet interface between an E2000 series processor platform and other terminal processors is greatly reduced, and the transmission rate of effective data is greatly improved; and meanwhile, a dual-avoidance strategy is adopted in a firmware layer and an application layer, so that the packet loss rate of SGMII interface network communication between different processor platforms is reduced to 0%. The design adopted by the invention can realize 100% localization, has autonomous controllability and borrowability, can be suitable for all processor platforms of E2000 series, and greatly improves the stability of network data communication between the SGMII interface and other loads.
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