LED display screen control ECU circuit and display screen based on FPGA

Abstract

The present invention provides a circuit and display screen of an FPGA-based LED display screen control ECU, including: an SBC communication control circuit, an RPP anti-reverse connection circuit, a PMIC power management circuit, an MCU control chip, a DCDC load power supply circuit, an FPGA control chip, an FPD-LINK data receiving circuit, a DDR3 data cache circuit, a FLASH data configuration circuit, a Buffer data output buffer circuit, and an LVDS low-voltage differential data circuit; the SBC communication control circuit is connected to the vehicle body KL30; the RPP anti-reverse connection circuit obtains the system power supply through the vehicle body KL30 connection; the PMIC power management circuit converts the vehicle body KL30 into the power supply required by FPGA, FLASH, DDR3 and FPD-LINK; the MCU control chip receives the communication information from the SBC communication control circuit. The present invention can efficiently process the data volume of tens of thousands or even millions of LEDs, and realizes the effect of real-time display, which is of great significance for improving the interactive experience and visual effect of the vehicle-mounted display screen, and can display more complex and delicate images and video content.

Description

Technical Field

[0001] This invention relates to the technical field of automotive electronics, and more specifically, to a circuit and display screen for an FPGA-based LED display control ECU. Background Technology

[0002] With the continuous development of automotive technology and the improvement of intelligence, in-vehicle displays, as an important interface for interaction between vehicles and pedestrians, are facing increasingly higher requirements in terms of function and performance. Traditional car lights, relying on only one or more LEDs for simple flashing or flowing prompts, can no longer meet the needs of modern automobiles for personalized, visual, and pedestrian-understandable visual aids. Therefore, display control systems using miniLEDs as the light source have emerged, capable of adapting to different scenarios and displaying images or videos to provide richer interactive information.

[0003] However, when the load of LEDs reaches tens of thousands or even millions, efficiently processing and displaying this data becomes a significant technical challenge. Traditional control solutions often suffer from slow data processing speeds, high costs, and poor real-time performance, failing to meet the requirements of modern automotive display control systems.

[0004] Patent document CN112498227B discloses a vehicle dynamic lighting control system and a vehicle, which utilizes a single electronic controller module (ECU), at least one ground control module unit, and a communication part that realizes signal connection and transmission between the two parts.

[0005] To address these issues, several display control systems based on different technologies have emerged on the market. For example, some systems employ high-performance processors for data processing, which, while enabling high-speed data processing, are costly and not suitable for large-scale applications. Other systems use simple control chips, which, although less expensive, have limited data processing capabilities and cannot meet the real-time display requirements of tens of thousands or millions of LEDs.

[0006] Therefore, a new technical solution is needed to address the aforementioned technical problems. Summary of the Invention

[0007] In view of the deficiencies in the prior art, the purpose of this invention is to provide a circuit and display screen for an LED display control ECU based on FPGA.

[0008] The present invention provides a circuit for an LED display control ECU based on an FPGA, comprising: an SBC communication control circuit, an RPP reverse connection protection circuit, a PMIC power management circuit, an MCU control chip, a DCDC load power supply circuit, an FPGA control chip, an FPD-LINK data receiving circuit, a DDR3 data cache circuit, a FLASH data configuration circuit, a Buffer data output buffer circuit, and an LVDS low-voltage differential data circuit.

[0009] The SBC communication control circuit is connected to the vehicle body KL30; the RPP reverse connection protection circuit obtains system power through the vehicle body KL30; the PMIC power management circuit converts the power required by the vehicle body KL30 into the power required by the FPGA, FLASH, DDR3, and FPD-LINK; the MCU control chip receives communication information from the SBC communication control circuit; the DCDC load power supply circuit supplies power to the LED display screen through the MCU control chip; the FPGA control chip processes the animation data of the LED display screen; the FPD-LINK data receiving circuit receives image or video data from the vehicle body; the DDR3 data buffer circuit stores the data received by the FPD-LINK data receiving circuit for a short time; the FLASH data configuration circuit stores the configuration data of the FPGA control chip; the Buffer data output buffer circuit is used for short-distance control of the chip data bridge on the LED display screen by the FPGA control chip; the LVDS low-voltage differential data circuit is used for long-distance control of the FPGA data bridge on the LED display screen by the FPGA control chip; the various circuits cooperate with each other to perform real-time control of the LED display screen.

[0010] Preferably, the SBC communication control circuit is connected to the vehicle body KL30 to receive a wake-up signal and drive the RPP reverse connection protection circuit to open and supply power to the downstream stage. It is also connected to the vehicle body CAN to bridge the MCU network diagnostic function.

[0011] Preferably, the RPP reverse connection protection circuit obtains system power through connection with the vehicle body KL30, and does not conduct when KL30 is incorrectly connected in the reverse direction.

[0012] Preferably, the PMIC power management circuit converts KL30 into different voltage levels to supply the power required by the FPGA control chip, FLASH circuit, FPD-LINK circuit, and DDR3 circuit respectively.

[0013] Preferably, the MCU control chip receives CAN messages from the SBC communication control circuit, parses them, interacts with the vehicle body data, and simultaneously configures the internal data of the FPGA.

[0014] Preferably, the DC-DC load power supply circuit provides a two-channel power supply, converting the vehicle body power supply into the voltage required for the LED display system unit to operate normally, and diagnosing open and short circuits in the power supply.

[0015] Preferably, the FPGA control chip calculates and processes the real-time image or video data to be displayed.

[0016] Preferably, the FPD-LINK data receiving circuit receives image or video data from the vehicle body and parses the serial data into parallel data to supply the FPGA control chip.

[0017] Preferably, the buffer data output buffer circuit is used to reduce external interference in the case of short distance between the control system and the load LED display system. A data buffer chip is added to the FPGA output section for short-distance transmission. The short-distance transmission is that the FPGA in the ECU is directly connected to the load ZIF connector via a ZIF connector and a flexible flat cable, and then the communication of the control chip is directly controlled.

[0018] The LVDS low-voltage differential data circuit is used to reduce external interference in long-distance control systems and load LED display systems. A low-voltage differential circuit is added to the FPGA output section for long-distance data transmission. In this long-distance transmission, the FPGA in the ECU outputs low-voltage differential signal data and clock to the LVDS at the load end, and then transmits it to the FPGA chip at the load.

[0019] The present invention also provides a display screen, including the circuit of the above-described FPGA-based LED display screen control ECU.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. This invention can efficiently process data from tens of thousands or even millions of LEDs, achieving real-time display. It is of great significance for improving the interactive experience and visual effects of in-vehicle displays, and can display more complex and detailed images and video content.

[0022] 2. The FPGA data processing method of the present invention is not only highly efficient, but also lower in cost compared to other high-performance processors. While maintaining high performance, it also has a lower cost advantage, which is conducive to promoting the popularization and application of automotive display technology.

[0023] 3. The RPP reverse connection protection circuit design in this invention can effectively prevent circuit damage caused by reverse power connection, protect the safety of the entire circuit system, and the PMIC power management circuit also provides a stable and reliable power supply for each module, further improving the stability and reliability of the system. Attached Figure Description

[0024] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0025] Figure 1 This is a schematic diagram of the structure of the present invention;

[0026] Figure 2 This is a diagram illustrating the long-distance transmission of the present invention;

[0027] Figure 3 This is a diagram illustrating the short-distance transmission of the present invention. Detailed Implementation

[0028] The present invention will be described in detail below with reference to specific examples. The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0029] Example 1:

[0030] Reference Figure 1According to the present invention, a circuit for controlling an LED display ECU based on an FPGA includes: an SBC communication control circuit, an RPP reverse connection protection circuit, a PMIC power management circuit, an MCU control chip, a DC-DC load power supply circuit, an FPGA control chip, an FPD-LINK data receiving circuit, a DDR3 data buffer circuit, a FLASH data configuration circuit, a buffer data output buffer circuit, and an LVDS low-voltage differential data circuit; the SBC communication control circuit is connected to the vehicle body KL30; the RPP reverse connection protection circuit obtains system power through the vehicle body KL30; the PMIC power management circuit converts the power from the vehicle body KL30 into the power required by the FPGA, FLASH, DDR3, and FPD-LINK; the MCU control chip receives power from the SBC communication control circuit. The circuitry includes: communication information for the control circuit; the DC-DC load power supply circuit powering the LED display screen via the MCU control chip; the FPGA control chip processing data for the animation on the LED display screen; the FPD-LINK data receiving circuit receiving image or video data from the vehicle body; the DDR3 data cache circuit temporarily storing the data received by the FPD-LINK data receiving circuit; the FLASH data configuration circuit storing the configuration data of the FPGA control chip; the Buffer data output buffer circuit used by the FPGA control chip for short-distance control of the chip data bridge on the LED display screen; and the LVDS low-voltage differential data circuit used by the FPGA control chip for long-distance control of the FPGA data bridge on the LED display screen. All these circuits work together to provide real-time control of the LED display screen.

[0031] The SBC communication control circuit connects to the KL30 on the vehicle body, receiving wake-up signals and driving the RPP reverse connection protection circuit to power subsequent stages. It also connects to the vehicle body's CAN bus, bridging the MCU network diagnostic function. The RPP reverse connection protection circuit obtains system power through its connection to the KL30 and does not conduct when the KL30 is incorrectly connected in the reverse direction. The PMIC power management circuit converts the KL30 voltage to different levels, supplying power to the FPGA control chip, FLASH circuit, FPD-LINK circuit, and DDR3 circuit respectively. The MCU control chip receives CAN messages from the SBC communication control circuit, parses them, and interacts with the vehicle body data, while simultaneously configuring internal data for the FPGA. The DCDC load power supply circuit provides two channels of power, converting the vehicle body power to the voltage required for normal operation of the LED display system unit and diagnosing open and short circuits in the power supply. The FPGA control chip calculates and processes the real-time image or video data to be displayed. The FPD-LINK data receiving circuit receives image or video data from the vehicle body, parses the serial data into parallel data, and supplies it to the FPGA control chip. (Refer to...) Figure 2 and Figure 3The buffer data output buffer circuit is used to reduce external interference in short-distance situations between the control system and the load LED display system. A data buffer chip is added to the FPGA output section for short-distance transmission. In this case, the FPGA in the ECU is directly connected to the ZIF connector at the load end via a ZIF connector and then directly controls the communication of the chip. The LVDS low-voltage differential data circuit is used to reduce external interference in long-distance situations between the control system and the load LED display system. A low-voltage differential circuit is added to the FPGA output section for long-distance data transmission. In this case, the FPGA in the ECU outputs low-voltage differential signal data and clock to the LVDS at the load end, and then transmits the data to the FPGA chip at the load.

[0032] The present invention also provides a display screen, including the circuit of the above-described FPGA-based LED display screen control ECU.

[0033] Example 2:

[0034] This invention provides an ECU based on FPGA design for LED display control systems. It offers a low-cost ECU control scheme for real-time display when the load of LEDs reaches tens of thousands or millions of units.

[0035] The FPGA-based LED display control system design includes the following components: SBC communication control circuit, RPP reverse connection protection circuit, PMIC power management circuit, MCU control chip, DCDC load power supply circuit, FPGA control chip, FPD-LINK data receiving circuit, DDR3 data cache circuit, FLASH data configuration circuit, Buffer data output buffer circuit, and LVDS low-voltage differential data circuit.

[0036] The SBC communication control circuit connects to the KL30 on the vehicle body. When a wake-up signal arrives, it drives the RPP reverse connection protection circuit to open and supply power to the downstream stage. It also connects to the vehicle body's CAN bus, bridging the MCU network diagnostic function. The RPP reverse connection protection circuit obtains system power through its connection to the KL30 on the vehicle body and has the capability to de-conduct when the KL30 is incorrectly connected in the reverse direction, protecting the entire circuit system. The PMIC power management circuit converts the power from the KL30 into the power required by the FPGA, FLASH, DDR3, and FPD-LINK. The MCU control chip receives SBC communication information, performs network diagnostics for the entire vehicle, and configures the FPGA. The DCDC load power supply circuit supplies power to the LED display screen via MCU control. The FPGA control chip is responsible for processing animation data on the LED display screen. The FPD-LINK data receiving circuit receives image or video data from the vehicle body, parses serial data into parallel data, and sends it to the FPGA. The DDR3 data buffer circuit is responsible for short-term storage of FPD-LINK data. The FLASH data configuration circuit stores the PFGA configuration data. The buffer data output buffer circuit is used as a data bridge for the PFGA to directly control the chip data on the LED display screen over a short distance. LVDS low-voltage differential data circuitry is used as an FPGA data bridge for long-distance control of LED displays via FPGA.

[0037] The SBC communication control circuit is used to wake up and receive CAN signals or hard-wired signals from the vehicle body. It features a charge pump output to drive the reverse connection protection circuit, a power supply to the MCU control chip, and the ability to receive the vehicle body CAN signal, bridge it, and send it to the MCU control chip.

[0038] The RPP reverse connection protection circuit, designed to meet functional safety requirements and prevent reverse insertion of connectors, can use a single power NMOS or multiple power NMOS transistors connected in parallel depending on the current required. When the power supply is normally connected, the NMOS is turned on, supplying power to the subsequent drive modules. When the power supply is reversed, the unidirectional conduction characteristic of the PMOS or diode is utilized to prevent reverse connection; the NMOS is turned off, protecting the subsequent power-consuming modules.

[0039] The PMIC power management circuit is a dedicated power management chip that receives power from the vehicle body and converts it to 3.3V to power the FPGA control chip, FLASH circuit, and FPD-LINK circuit; to 2.5V to power the FPGA control chip; to 1.35V to power the FPGA control chip and DDR3 circuit; to 1.2V to power the FPGA control chip and FPD-LINK circuit; and to 1.1V to power the FPGA control chip.

[0040] The MCU control chip receives CAN messages from the SBC circuit, parses them, and interacts with the vehicle body data. It can also configure data within the FPGA.

[0041] The DC-DC load power supply circuit provides two channels of power, converting the vehicle body power supply into the voltage required for the LED display system unit to operate normally. It also has open and short circuit diagnostic features for the power supply, and can shut down the output in the event of a load system failure.

[0042] FPGA control chips calculate and process real-time image or video data to be displayed.

[0043] The FPD-LINK data receiving circuit is used to parse the serial data of images or videos of the vehicle body into the parallel data required by the FPGA.

[0044] The DDR3 data cache circuit can cache a portion of the data when a large amount of data is transmitted from the vehicle body for later use by the FPGA.

[0045] The FLASH data configuration circuit stores FPGA configuration data and is used as an external ROM for the FPGA.

[0046] In situations where the control system and the load LED display system are within a short distance, a data buffer chip is added to the FPGA output section to reduce external interference.

[0047] In situations where the control system and the load LED display system are located over long distances, a low-voltage differential circuit is added to the FPGA output section to reduce external interference.

[0048] A display control system using miniLEDs as the light source allows the displayed content of the miniLED light source array to accurately reflect the image data output by the FPGA. As an interactive interface between vehicles and pedestrians, the display screen offers a more sophisticated alternative to existing vehicle lights that rely solely on the simple blinking or flowing motions of one or more LEDs. This display technology can adapt to different scenarios, displaying images or videos to achieve personalized, visual, and pedestrian-understandable visual representations.

[0049] The control unit is the core of the entire display system. Its input interfaces are divided into three categories: KL30 connects to the vehicle battery, EXT_CAN connects to the vehicle's CAN bus, and KL30 connects to the controller internally via an SBC chip to achieve ultra-low power consumption. EXT_CAN interacts with the vehicle's BCM or domain controller via CAN messages, such as for ECU network management and diagnostics. FPD-link connects to the vehicle's HMI, receiving images or videos, parsing them internally, and transmitting them to the miniLED display system. The output interfaces are also divided into three categories: ULED powers the miniLED display system, FPGA controls the miniLED display to show corresponding patterns over short distances via a buffer chip, and FPGA controls the miniLED display to show corresponding patterns over long distances via an LVDS circuit.

[0050] The "Hello" icon is manually written on the vehicle's large screen. After real-time analysis and processing by the ECU's FPGA, the corresponding "Hello" is immediately displayed on the miniLED screen. The display is not limited to letters; it can be any image or play dynamic video footage. The miniLED screens use tens of thousands or even millions of LEDs.

[0051] This invention solves the problem of parsing data in the tens of thousands or millions of LEDs by using FPGA data processing, achieving a low-cost application effect for real-time display.

[0052] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.

[0053] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0054] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A circuit for controlling an ECU for an LED display screen based on FPGA, characterized in that: include: SBC communication control circuit, RPP anti-reverse connection circuit, PMIC power management circuit, MCU control chip, DCDC load power supply circuit, FPGA control chip, FPD-LINK data receiving circuit, DDR3 data cache circuit, FLASH data configuration circuit, Buffer data output buffer circuit and LVDS low voltage differential data circuit; The SBC communication control circuit is connected to the vehicle body KL30; the RPP anti-reverse connection circuit obtains system power through the vehicle body KL30 connection; the PMIC power management circuit converts the vehicle body KL30 into the power required by FPGA, FLASH, DDR3 and FPD-LINK; the MCU control chip receives communication information from the SBC communication control circuit; the DCDC load power supply circuit supplies power to the LED display screen through the MCU control chip; the FPGA control chip processes data for the LED display screen animation; the FPD-LINK data receiving circuit receives pictures or video data from the vehicle body; the DDR3 data cache circuit stores the data received by the FPD-LINK data receiving circuit for a short time; the FLASH data configuration circuit stores the configuration data of the FPGA control chip; the Buffer data output buffer circuit is used for the FPGA control chip to control the chip data bridge on the LED display screen over a short distance; the LVDS low-voltage differential data circuit is used for the FPGA control chip to control the FPGA data bridge on the LED display screen over a long distance; the various circuits cooperate with each other to control the LED display screen in real time.

2. The circuit of the FPGA-based LED display screen control ECU according to claim 1 is characterized in that: The SBC communication control circuit is connected to the vehicle body KL30, and is used to receive the wake-up signal and drive the RPP anti-reverse connection circuit to open to supply power to the subsequent stage, and is also connected to the vehicle body CAN to bridge the MCU network diagnostic function.

3. The circuit of the FPGA-based LED display screen control ECU according to claim 1 is characterized in that: The RPP reverse connection protection circuit obtains system power by connecting to the vehicle body KL30, and does not conduct when KL30 is incorrectly connected in the reverse direction.

4. The circuit of the FPGA-based LED display screen control ECU according to claim 1 is characterized in that: The PMIC power management circuit converts KL30 into different voltage levels to supply the power required by the FPGA control chip, FLASH circuit, FPD-LINK circuit, and DDR3 circuit respectively.

5. The circuit of the FPGA-based LED display screen control ECU according to claim 1 is characterized in that: The MCU control chip receives CAN messages from the SBC communication control circuit, parses them and interacts with the vehicle body data, and configures the internal data of the FPGA.

6. The circuit of the FPGA-based LED display screen control ECU according to claim 1 is characterized in that: The DCDC load power supply circuit provides two-channel power supply, converts the vehicle body end power supply into the voltage required for the normal operation of the LED display screen system unit, and diagnoses the open and short circuits of the power supply.

7. The circuit of the FPGA-based LED display screen control ECU according to claim 1 is characterized in that: The FPGA control chip calculates and processes the real-time image or video data to be displayed.

8. The circuit of the FPGA-based LED display screen control ECU according to claim 1 is characterized in that: The FPD-LINK data receiving circuit receives the picture or video data from the vehicle body, and parses the serial data into parallel data to supply to the FPGA control chip.

9. The circuit of the FPGA-based LED display screen control ECU according to claim 1 is characterized in that: The Buffer data output buffer circuit is used to reduce external interference when the control system and the load LED display system are at a short distance. A data buffer chip is added to the FPGA output part to perform short-distance transmission. The short-distance transmission is that the FPGA in the ECU is directly connected to the load end ZIF connector through the ZIF connector to connect the soft flat cable, and then directly control the communication of the chip. The LVDS low-voltage differential data circuit is used to reduce external interference when the control system and the load LED display system are long distance apart. A low-voltage differential circuit is added to the FPGA output part to perform long-distance data transmission. The long-distance transmission is that the FPGA in the ECU outputs low-voltage differential signal data and clock through LVDS, which are connected to the LVDS at the load end and then transmitted to the FPGA chip of the load.

10. A display screen, characterized in that: A circuit comprising an FPGA-based LED display screen control ECU as described in any one of claims 1-9.

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