Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and optimizes the design of a pixel circuit. The display panel comprises a pixel circuit, and the pixel circuit comprises a driving transistor which is an N-type transistor; the grid electrode of the first light-emitting control transistor and the grid electrode of the second light-emitting control transistor are electrically connected with the same light-emitting control line, the first pole of the first light-emitting control transistor is electrically connected with the first power line, and the second pole of the first light-emitting control transistor is electrically connected with the first pole of the driving transistor; the first electrode of the second light-emitting control transistor is electrically connected with the second electrode of the driving transistor, and the second electrode is electrically connected with the light-emitting element; a grid electrode of the first transistor is electrically connected with the first scanning line, a first pole is electrically connected with the first power line, and a second pole is electrically connected with the driving transistor.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic light emitting diodes (OLEDs) are a type of current-type light-emitting element that has been increasingly used in various display devices. The display panel of such display devices includes a pixel circuit and an OLED, and the pixel circuit provides a driving current to the OLED to drive it to emit light. However, the design of the existing pixel circuit needs to be further optimized. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device, wherein the circuit design of the pixel circuit is better.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including a pixel circuit, wherein the pixel circuit includes:

[0005] A driving transistor, wherein the driving transistor is an N-type transistor;

[0006] a first light emission control transistor and a second light emission control transistor, wherein a gate of the first light emission control transistor and a gate of the second light emission control transistor are electrically connected to the same light emission control line, a first electrode of the first light emission control transistor is electrically connected to a first power supply line, and a second electrode is electrically connected to a first electrode of the driving transistor, and a first electrode of the second light emission control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode is electrically connected to a light emitting element;

[0007] A first transistor, wherein a gate of the first transistor is electrically connected to the first scanning line, a first electrode is electrically connected to the first power line, and a second electrode is electrically connected to the driving transistor.

[0008] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0009] The technical solution provided by the embodiment of the present invention has the following beneficial effects:

[0010] In an embodiment of the present invention, the pixel circuit includes a first transistor, and the first transistor is connected between the first power line and the driving transistor. Before charging the driving transistor, the first transistor can be used to open the signal transmission path between the first power line and the driving transistor, so that the signal of the first power line is written into the driving transistor, and at least one node of the driving transistor is set to a specific initial potential. In this way, it is no longer necessary to rely on the first light-emitting control transistor to write the signal of the first power line into the driving transistor. The first light-emitting control transistor only assumes the function of light-emitting control. Therefore, the first light-emitting control transistor and the second light-emitting control transistor can be electrically connected to the same light-emitting control line.

[0011] The first light-emitting control transistor and the second light-emitting control transistor are connected to the same light-emitting control line, which means that only one set of light-emitting control signals can be used to synchronously control the two light-emitting control transistors in the pixel circuit, which can simplify the path and method of the light-emitting control signal and make dimming more convenient. For example, when the PWM (pulse width modulation) dimming method is adopted, the duty cycle of the pulse of the light-emitting control signal is used to finely adjust the brightness. If the two light-emitting control transistors are respectively connected to two different light-emitting control lines, it is necessary to generate dimming PWM signals separately for the two different light-emitting control lines, resulting in more complex control logic and increasing the difficulty of control. When two light-emitting control transistors are connected to one light-emitting control line, only one dimming PWM signal is needed to complete the dimming control, which greatly reduces the number of control signals and the complexity of adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0013] Figure 1 A schematic diagram of a structure of a pixel circuit provided by an embodiment of the present invention;

[0014] Figure 2 for Figure 1 A corresponding timing diagram;

[0015] Figure 3 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0016] Figure 4 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 5 for Figure 4 A corresponding timing diagram;

[0018] Figure 6 for Figure 4 Another corresponding timing diagram;

[0019] Figure 7 A timing diagram of a light emitting control line provided by an embodiment of the present invention;

[0020] Figure 8 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0021] Fig. 9 for Figure 4 Another corresponding timing diagram;

[0022] Fig.10 for Figure 4 Another corresponding timing diagram;

[0023] Fig.11 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0024] Fig.12 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0025] Fig.13 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0026] Fig.14 for Fig.13 A corresponding timing diagram;

[0027] Fig.15 for Fig.13 Another corresponding timing diagram;

[0028] Fig.16 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0029] Fig.17 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0030] Fig.18 for Fig.17 A corresponding timing diagram;

[0031] Fig.19 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0032] Fig. 20 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0033] Fig.21 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0034] Fig. 22 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0035] Fig.23 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0036] Fig.24 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0037] Fig.25 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0038] Fig.26 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0039] Fig. 27 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0040] Fig.28 for Fig. 27 A corresponding timing diagram;

[0041] Fig.29 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0042] Fig.30 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0043] Fig.31 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0044] Fig.32 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0045] Fig.33 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0049] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0050] The pixel circuit includes a driving transistor and a plurality of switching transistors, wherein the driving transistor is used to convert the driving current required by the light emitting element.

[0051] In conventional designs, the driving transistor and the switch transistor in the pixel circuit are both P-type transistors, for example, both are low temperature polycrystalline silicon (LTPS) transistors. However, the embodiment of the present invention proposes a new pixel circuit design, in which the driving transistor is an N-type transistor, for example, an indium gallium zinc oxide (Indium Gallium Zinc Oxide) transistor.

[0052] When the driving transistor is an N-type transistor, before charging the gate of the driving transistor, a signal of the first power line may be written into the driving transistor to place a node of the driving transistor at a specific initial potential.

[0053] In this regard, the embodiment of the present invention proposes a circuit design, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a structure of a pixel circuit provided by an embodiment of the present invention. The pixel circuit 1' includes a driving transistor T0', a threshold compensation transistor T1', a first light emission control transistor T2' and a second light emission control transistor T3'.

[0054] Among them, the gate of the driving transistor T0' is electrically connected to the first node N1', the first electrode is electrically connected to the second node N2', and the second electrode is electrically connected to the third node N3'; the threshold compensation transistor T1' is electrically connected between the second node N2' and the first node N1'; the first light-emitting control transistor T2' is electrically connected between the first power line PVDD' and the second node N2'; the second light-emitting control transistor T3' is electrically connected between the third node N3' and the light-emitting element 2'.

[0055] Based on the above structure, before charging the gate of the driving transistor T0', the first light emission control transistor T2' and the threshold compensation transistor T1' can be controlled to be turned on, thereby writing the signal of the first power line PVDD' into the second node N2' and the first node N1'.

[0056] However, in this implementation, before charging the gate of the driving transistor T0', it is necessary to use the first light-emitting control transistor T2' to construct a signal transmission path between the first power line PVDD' and the driving transistor T0'. Therefore, the first light-emitting control transistor T2' and the second light-emitting control transistor T3' have different conduction times, and they need to be connected to two different light-emitting control signal lines respectively: the gate of the first light-emitting control transistor T2' is electrically connected to the first light-emitting control line Emit1', and the gate of the second light-emitting control transistor T3' is electrically connected to the second light-emitting control line Emit2'. Figure 2 As shown, Figure 2 for Figure 1 A corresponding timing diagram, in the m1' period, the first light-emitting control line Emit1' provides an enable level to control the first light-emitting control transistor T2' to turn on, open the signal transmission path between the first power line PVDD' and the driving transistor T0', so that the first power signal can be written into the driving transistor T0', and the second light-emitting control line Emit2' provides a non-enable level to control the second light-emitting control transistor T3' to turn off, cutting off the current path between the driving transistor T0' and the light-emitting element 2'.

[0057] However, the above-mentioned structure of driving the two light-emitting control lines makes the dimming design of the light-emitting control signal more complicated, which is not conducive to achieving fine control of the light-emitting brightness.

[0058] In this regard, the embodiment of the present invention further proposes a technical solution:

[0059] An embodiment of the present invention provides a display panel, such as Figure 3 As shown, Figure 3 A schematic diagram of the structure of a display panel provided in an embodiment of the present invention, the display panel includes a pixel circuit 1.

[0060] like Figure 4 As shown, Figure 4 This is another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention. The pixel circuit 1 includes a driving transistor T0, a first light emitting control transistor T1, a second light emitting control transistor T2 and a first transistor T3.

[0061] The driving transistor T0 is an N-type transistor, for example, an IGZO transistor.

[0062] The gate of the first light emission control transistor T1 and the gate of the second light emission control transistor T2 are electrically connected to the same light emission control line Emit. The first electrode of the first light emission control transistor T1 is electrically connected to the first power line PVDD, and the second electrode is electrically connected to the first electrode of the driving transistor T0. The first electrode of the second light emission control transistor T2 is electrically connected to the second electrode of the driving transistor T0, and the second electrode is electrically connected to the light emitting element 2.

[0063] The first transistor T3 has a gate electrically connected to the first scan line S1 , a first electrode electrically connected to the first power line PVDD, and a second electrode electrically connected to the driving transistor T0 .

[0064] The pixel circuit includes a first transistor T3, which is connected between the first power line PVDD and the driving transistor T0. Before charging the driving transistor T0, the first transistor T3 can be used to open the signal transmission path between the first power line PVDD and the driving transistor T0, so that the signal of the first power line PVDD is written into the driving transistor T0, and at least one node of the driving transistor T0 is set to a specific initial potential. In this way, it is no longer necessary to rely on the first light-emitting control transistor T1 to write the signal of the first power line PVDD into the driving transistor T0. The first light-emitting control transistor T1 only assumes the function of light-emitting control. Therefore, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 can be electrically connected to the same light-emitting control line Emit.

[0065] The first light-emitting control transistor T1 and the second light-emitting control transistor T2 are connected to the same light-emitting control line Emit, which means that only one set of light-emitting control signals can be used to synchronously control the two light-emitting control transistors in the pixel circuit, which can simplify the path and method of the light-emitting control signal and make dimming more convenient. For example, when the PWM (pulse width modulation) dimming method is adopted, the duty cycle of the pulse of the light-emitting control signal is used to finely adjust the brightness. If the two light-emitting control transistors are respectively connected to two different light-emitting control lines, it is necessary to generate dimming PWM signals separately for the two different light-emitting control lines, resulting in more complex control logic and increasing the difficulty of control. When the two light-emitting control transistors are connected to one light-emitting control line, only one dimming PWM signal is needed to complete the dimming control, which greatly reduces the number of control signals and the complexity of adjustment.

[0066] In a possible implementation, Figure 5 and Figure 6 As shown, Figure 5 for Figure 4 A corresponding timing diagram, Figure 6 for Figure 4In another corresponding timing diagram, the driving cycle DC of the pixel circuit 1 includes at least one frame, and one frame includes a non-luminous phase T-ne and a luminous phase Te. More specifically, one frame may include at least one luminous cycle EC, and the luminous cycle EC includes a non-luminous phase T-ne and a luminous phase T-ne.

[0067] In the non-light-emitting stage T-ne, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned off, the second light-emitting control transistor T2 cuts off the current path between the driving transistor T0 and the light-emitting element 2, and the light-emitting element 2 does not emit light. In at least part of the light-emitting stage Te, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on, the second light-emitting control transistor T2 opens the current path between the driving transistor T0 and the light-emitting element 2, and the light-emitting element 2 emits light.

[0068] The frames in the driving cycle DC include a writing frame WF. When the first transistor T3 is provided, the first transistor T3 is turned on during a partial period of the non-light-emitting phase T-ne of the writing frame WF to write the signal of the first power line PVDD into the driving transistor T0.

[0069] Regarding the definition of "one frame", in one driving mode of the display panel, the display panel has a base frequency f and a first frequency f1, the first frequency f1 is less than the base frequency f, and the first frequency f1 is achieved by down-converting the base frequency f. For example, the base frequency f is 120Hz, and the first frequency f1 includes 60Hz, 40Hz, 30Hz, 20Hz, 10Hz, 1Hz, etc. One frame is the duration of a data refresh cycle under the base frequency f. For example, if the base frequency f is 120Hz, then one frame is 8.33ms.

[0070] See also Figure 5 , under the basic frequency f, the driving cycle DC of the pixel circuit 1 includes 1 frame, which is a writing frame WF, and the duration of the writing frame WF is 8.33 ms.

[0071] See also Figure 6 At the first frequency f1, the driving cycle DC of the pixel circuit 1 includes multiple frames, one of the multiple frames is a writing frame WF, and the remaining frames are holding frames HF. The duration of the writing frame WF and the holding frame HF are both 8.33 ms.

[0072] In the non-luminous phase T-ne of the writing frame WF, the first scanning line S1 provides an enable level to control the first transistor T3 to turn on, open the signal transmission path between the first power line PVDD and the driving transistor T0, so that the signal of the first power line PVDD is written into the driving transistor T0, and then at least one node of the driving transistor T0 is set to a specific initial potential. As mentioned above, under this design, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 can be driven by a set of light-emitting control signals, which helps to simplify the dimming control.

[0073] In a possible implementation, Figure 7 As shown, Figure 7 A timing diagram of the light-emitting control line provided in an embodiment of the present invention, the driving cycle DC of the pixel circuit 1 includes at least one frame, and one frame includes a non-light-emitting stage T-ne and a light-emitting stage Te. More specifically, one frame may include at least one light-emitting cycle EC, and the light-emitting cycle EC includes a non-light-emitting stage T-ne and a light-emitting stage T-ne.

[0074] In the non-light-emitting stage T-ne, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned off, and the second light-emitting control transistor T2 cuts off the current path between the driving transistor T0 and the light-emitting element 2, and the light-emitting element 2 does not emit light. In the light-emitting stage Te, the light-emitting control line Emit provides at least two pulses. Exemplarily, one frame includes three light-emitting cycles EC, and in the light-emitting stage Te, the light-emitting control line Emit provides 12 pulses.

[0075] PWM (Pulse Width Modulation) dimming uses the duty cycle of the pulses of the light-emitting control signal to finely adjust the brightness. As the number of pulses of the light-emitting control signal increases, the level of adjustable duty cycle increases. In the light-emitting stage Te, by controlling the light-emitting control line Emit to provide multiple pulses, a finer duty cycle adjustment can be achieved, so that the light-emitting time of the light-emitting element 2 can be more accurately controlled to achieve a more delicate brightness change.

[0076] In one possible implementation, see Figure 4 and Figure 8 , Figure 8 This is another structural schematic diagram of a pixel circuit provided in an embodiment of the present invention, wherein the driving transistor T0 includes at least one gate, wherein the at least one gate includes a first gate, wherein the first gate of the driving transistor T0 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.

[0077] In the embodiment of the present invention, the driving transistor T0 may be a single-gate transistor or a dual-gate transistor including a top gate and a bottom gate. When the driving transistor T0 is a single-gate transistor, its gate is understood to be the first gate; when the driving transistor T0 is a dual-gate transistor, its top gate is understood to be the first gate.

[0078] The pixel circuit 1 further includes a data writing transistor T4 and a second transistor T5. The gate of the data writing transistor T4 is electrically connected to the second scan line S2, and the first electrode is electrically connected to the data line Data. The gate of the second transistor T5 is electrically connected to the third scan line S3, and the second electrode is electrically connected to the first node N1. One of the second electrode of the data writing transistor T4 and the first electrode of the second transistor T5 is electrically connected to the second node N2, and the other is electrically connected to the third node N3.

[0079] That is, in one structure, see Figure 4 , the second electrode of the data writing transistor T4 is electrically connected to the third node N3, and the first electrode of the second transistor T5 is electrically connected to the second node N2. Alternatively, in another structure, see Figure 8 , a second electrode of the data writing transistor T4 is electrically connected to the second node N2, and a first electrode of the second transistor T5 is electrically connected to the third node N3.

[0080] The second electrode of the first transistor T3 is electrically connected to the second transistor T5.

[0081] The above scheme defines that the second electrode of the first transistor T3 is electrically connected to the driving transistor T0. When the second electrode of the first transistor T3 is also electrically connected to the second transistor T5, it means that the first transistor T3 is either connected to the first node N1, or to the second node N2 or the third node N3 to which the second electrode of the second transistor T5 is connected.

[0082] Under this structure, before charging the gate of the driving transistor T0, the first transistor T3 and the second transistor T5 can be controlled to be turned on, and then the signal of the first power line PVDD is written into the first node N1 and the second node N2, or written into the first node N1 and the third node N3, to reset at least two nodes of the driving transistor T0, so that the reset of the driving transistor T0 is more thorough.

[0083] Furthermore, if Fig. 9 and Fig.10 As shown, Fig. 9 for Figure 4 Another corresponding timing diagram is: Fig.10 for Figure 4 In another corresponding timing diagram, the driving cycle DC of the pixel circuit 1 includes a writing frame WF, and the writing frame WF includes a reset phase t1 and a data writing and compensation phase t2.

[0084] In the reset phase t1, the first transistor T3 and the second transistor T5 are turned on, and the signal of the first power line PVDD is written into the first node N1, and into the second node N2 or the third node N3 connected to the second transistor T5, so that the first node N1 and the second node N2 are reset, or the first node N1 and the third node N3 are reset using the first power signal.

[0085] It should be noted that, in the reset phase t1, the turn-on time of the first transistor T3 and the second transistor T4 may be the same or different. For example, see Fig. 9 , the first transistor T3 can be turned on earlier than the second transistor T4, that is, after the first power signal starts to be written into the first node N1, the second transistor T5 is controlled to be turned on to further write the first power signal of the first node N1 into the second node N2 or the third node N3.

[0086] In the data writing and compensation phase t2, the data writing transistor T4 and the second transistor T5 are turned on to write the signal of the data line Data into the first node N1 and perform threshold compensation on the driving transistor T0. That is, in the data writing and compensation phase t2, data writing and threshold compensation are performed synchronously.

[0087] In the above working process, the second transistor T5 is not only used as a threshold compensation in the data writing and compensation stage t2, but also used to reset the first electrode or the second electrode of the driving transistor T0 in the reset stage t1, so that the device state of the driving transistor T0 is configured to a more certain initial state before charging, which helps to improve the charging uniformity.

[0088] Further, see Fig.10 and Fig. 9 , a first intermediate stage t3 is also included between the reset stage t1 and the data writing and compensation stage t2.

[0089] In a possible implementation, combining Figure 4 and Fig.10 In the first intermediate stage t3, the first transistor T3 and the data writing transistor T4 are turned off, and the second transistor T5 is turned on, so that in this stage the second transistor T5 continuously writes the first power signal of the first node N1 into the second node N2 or the third node N3, thereby strengthening the resetting of the second node N2 or the third node N3.

[0090] Or, in another feasible embodiment, combined with Figure 4 and Fig. 9 In the first intermediate stage t3, the first transistor T3 and the second transistor T5 are turned off, and the data writing transistor T4 is turned on to write the signal of the data line Data into the second node N2 or the third node N3 connected to the data writing transistor T4.

[0091] During this stage, the data writing transistor T4 is turned on, and the signal of the data line Data is written into the second node N2 or the third node N3 to which it is connected, so that the data signal can be pre-written to prepare for the subsequent data writing and threshold compensation. Then, when the second transistor T5 is controlled to be turned on during the data writing and compensation stage t2, the data signal can be written into the first node N1 more quickly, so that the charging is more sufficient.

[0092] Regarding the aforementioned “the second electrode of the first transistor T3 is electrically connected to the second transistor T5”, in a feasible implementation manner, see Figure 4 and Fig. 9 , a second electrode of the first transistor T3 is electrically connected to the first node N1.

[0093] In this structure, in the reset phase t1 , the signal of the first power line PVDD is written into the first node N1 via the first transistor T3 , and then is written into the second node N2 or the third node N3 via the second transistor T5 .

[0094] Or, in another feasible implementation, as Fig.11 and Fig.12 As shown, Fig.11 Schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention. Fig.12 This is another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention, in which the second electrode of the first transistor T3 is electrically connected to the first electrode of the second transistor T5. That is, when the first electrode of the second transistor T5 is electrically connected to the second node N2, the second electrode of the first transistor T3 is electrically connected to the second node N2, and when the first electrode of the second transistor T5 is electrically connected to the third node N3, the second electrode of the first transistor T3 is electrically connected to the third node N3.

[0095] In this structure, in the reset phase t1 , the signal of the first power line PVDD is written into the second node N2 or the third node N3 via the second transistor T5 , and then is written into the first node N1 via the first transistor T3 .

[0096] In addition, the pixel circuit 1 may further include a second reset transistor T6 and a storage capacitor Cst. The first electrode of the second reset transistor T6 receives a reset signal, and the second electrode is electrically connected to the light emitting element 2, wherein the connection node between the second reset transistor T6, the second light emitting control transistor T2 and the light emitting element 2 is a fourth node N4. The storage capacitor Cst is electrically connected between the first node N1 and the fourth node N4.

[0097] Combine the following Figure 4 and 9 , taking the transistors in the pixel circuit 1 as N-type transistors as an example, the working process of the pixel circuit 1 is described as follows:

[0098] In the reset stage t1, the first scan line S1 provides a high level to control the first transistor T3 to turn on, the third scan line S3 provides a high level to control the second transistor T5 to turn on, and the signal of the first power line PVDD is written into the first node N1 and the second node N2; the fourth scan line S4 provides a high level to control the second reset transistor T6 to turn on, and the reset signal received by the second reset transistor T6 is written into the fourth node N4. N1 =V N2 =V PVDD , V N4 =V ref , V ref is the voltage of the reset signal received by the second reset transistor T6.

[0099] In the first intermediate stage t3, the second scan line S2 provides a high level to control the data writing transistor T4 to turn on, and write the signal of the data line Data into the second node N2 and the third node N3; the second reset transistor T6 is continuously turned on. N2 =V N3 =V Data , V N4 =V ref .

[0100] In the data writing and compensation stage t2, the data writing transistor T4 is turned on, the third scan line S3 provides a high level to control the second transistor T5 to turn on, write the signal of the data line Data into the first node N1, and perform threshold compensation on the driving transistor T0; the second reset transistor T6 is turned on. In this stage, V N1 =V Data +Vth, Vth is the threshold voltage of the driving transistor T0, V N4 =V ref .

[0101] In the light emitting stage Te, the light emitting control line Emit provides a high level and the first light emitting control transistor T1 and the second light emitting control transistor T2 are turned on, so that the driving current flows into the light emitting element 2. The driving current I flowing into the light emitting element 2 = k×(V gs -Vth) 2 .in, μ n is the migration rate of electrons in the driving transistor T0, C ox is the gate oxide capacitance per unit area of ​​the driving transistor T0, is the channel width-to-length ratio of the driving transistor T0, V gs is the gate-source voltage of the driving transistor T0, V gs =V N1 -V N3 =VData +Vth-V ref , and then we can get I = k × (V Data -V ref ) 2 .

[0102] In a possible implementation, Fig.13 As shown, Fig.13 This is another structural schematic diagram of a pixel circuit provided in an embodiment of the present invention, wherein the driving transistor T0 includes at least one gate, wherein the at least one gate includes a first gate, wherein the first gate of the driving transistor T0 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.

[0103] In the embodiment of the present invention, the driving transistor T0 may be a single-gate transistor or a dual-gate transistor including a top gate and a bottom gate. When the driving transistor T0 is a single-gate transistor, its gate is understood to be the first gate; when the driving transistor T0 is a dual-gate transistor, its top gate is understood to be the first gate.

[0104] The pixel circuit 1 further includes a data writing transistor T4 , a gate of the data writing transistor T4 being electrically connected to the second scanning line S2 , a first electrode being electrically connected to the data line Data, and a second electrode being electrically connected to the first node N1 .

[0105] The pixel circuit 1 further includes a control unit 3, which includes a first transistor T3 and a second transistor T5, wherein the gate of the second transistor T5 is electrically connected to the third scan line S3, and the first electrode and / or the second electrode is electrically connected to the driving transistor T0. The control unit 3 is used to write a constant voltage signal to the first node N1 and the second node N2.

[0106] Based on this structure, before charging, the control unit 3 can be used to write a constant voltage signal to the first node N1 and the second node N2, so that the device state of the driving transistor T0 is configured to be a more certain initial state. It can be understood that the control unit 3 includes a first transistor T3, so the constant voltage signal written to at least one of the first node N1 and the second node N2 is the first power signal provided by the first power line PVDD.

[0107] In one possible implementation, see Fig.13 The pixel circuit 1 further includes a first capacitor C1 and a second capacitor C2. The first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate is electrically connected to the third node N3. The first plate of the second capacitor C2 receives a constant voltage signal in at least a part of the time period, and the second plate is electrically connected to the third node N3.

[0108] When the first gate of the driving transistor T0 is charged, the potential of the first node N1 will change. When the potential of the first node N1 changes, based on the effects of the first capacitor C1 and the second capacitor C2, the potential of the third node N3 will also change accordingly, and the amount of change in the potential of the third node N3 will be related to the capacitance values ​​of the first capacitor C1 and the second capacitor C2, so that the driving current that finally flows into the light-emitting element 2 will also be related to the capacitance values ​​of the first capacitor C1 and the second capacitor C2, and the first capacitor C1 and the second capacitor C2 can be used to adjust the setting range of the data voltage.

[0109] Alternatively, in other optional embodiments of the present invention, the pixel circuit 1 may also include only the first capacitor C1, the first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate is electrically connected to the third node N3. When the potential of the first node N1 changes, based on the effect of the first capacitor C1, the potential of the third node N3 changes accordingly. At this time, the amount of change in the potential of the third node N3 is related to the capacitance value of the first capacitor C1.

[0110] Regarding the control unit 3, in a possible implementation manner, see Fig.13 The first transistor T3 is electrically connected to the second node N2. The first electrode of the second transistor T5 is electrically connected to the first reset line Ref1, and the second electrode is electrically connected to the first node N1.

[0111] Based on this structure, the control unit 3 writes the constant voltage signal to the first node N1 and the second node N2 specifically means: using the first transistor T3 to write the first power signal provided by the first power line PVDD to the second node N2, and using the second transistor T5 to write the first reset signal provided by the first reset line Ref1 to the first node N1. In this structure, the constant voltage signals written to the first node N1 and the second node N2 are different.

[0112] Furthermore, if Fig.14 As shown, Fig.14 for Fig.13 In a corresponding timing diagram, the driving cycle DC of the pixel circuit 1 includes a writing frame WF, and the writing frame WF includes a reset phase t1 ′, a threshold compensation phase t2 ′ and a data writing phase t3 ′.

[0113] In the reset phase t1 ′, the second transistor T5 is turned on, and the constant voltage signal of the first reset line Ref1 is written into the first node N1 to reset the first node N1 .

[0114] In the threshold compensation stage t2', the second transistor T5 is turned on, and the constant voltage signal of the first reset line Ref1 is written into the first node N1, and the first node N1 is reset. The first transistor T3 is turned on, and the constant voltage signal of the first power line PVDD is written into the second node N2, and the third node N3 captures the threshold voltage, and the driving transistor T0 is threshold compensated.

[0115] In the data writing phase t3 ′, the data writing transistor T4 is turned on to write the voltage of the data line Data into the first node N1 .

[0116] It should be noted that, in the reset phase t1', the first transistor T3 may also be turned on, and the turn-on time of the first transistor T3 may be earlier than, later than or equal to the turn-on time of the second transistor T5. Fig.15 As shown, Fig.15 for Fig.13 Corresponding to another timing diagram, in the reset phase t1', the first scan line S1 provides an enable level to control the first transistor T3 to be turned on, and the time when the first scan line S1 provides the enable level is earlier than the time when the third scan line S3 provides the enable level.

[0117] In the above structure, in the threshold compensation stage t2', the third node N3 captures the threshold voltage and performs threshold compensation on the driving transistor T0, and in the data line Data writing stage, the data signal is written into the first node N1. The threshold compensation and data writing under this design are performed step by step, which can ensure that the time for threshold compensation and data writing is more sufficient, so that charging and compensation are more sufficient.

[0118] In a possible implementation, Fig.16 As shown, Fig.16 Another structural schematic diagram of a display panel provided by an embodiment of the present invention, the display panel includes a plurality of circuit rows 4 arranged along a first direction x, the circuit rows include a plurality of pixel circuits 1 arranged along a second direction y, and the first direction x intersects the second direction y.

[0119] Combination Fig.15 and Fig.16 , the first scan line S1 connected to the i-th circuit row is electrically connected to the third scan line S3 connected to the ix-th circuit row, x≥1, exemplarily, x=1, 2, 3, 4, 5... Fig.16 Take x=2 as an example. In this structure, the time when the first scan line S1 corresponding to the same circuit row 4 provides the enable level is earlier than the time when the third scan line S3 provides the enable level.

[0120] Alternatively, the third scan line S3 connected to the ith circuit row is electrically connected to the first scan line S1 connected to the ixth circuit row. In this structure, the third scan line S3 corresponding to the same circuit row 4 provides an enable level earlier than the first scan line S1.

[0121] Taking the electrical connection of the first scan line S1 connected to the ith circuit row and the third scan line S3 connected to the ixth circuit row as an example, under this design, the first scan line S1 connected to the ith circuit row and the third scan line S3 connected to the ixth circuit row can be electrically connected to the same level of shift register, so that only one shift register can be configured for the first scan line S1 and the third scan line S3, simplifying the panel structure design. Alternatively, the first scan line S1 and the third scan line S3 can also be driven on both sides, that is, the first scan line S1 and the third scan line S3 are connected to a shift register on one side and a shift register on the other side. Compared with configuring different shift registers for the first scan line S1 and the third scan line S3, this bilateral drive will not increase the border width, and can also enhance the driving ability of the first scan signal and the third scan signal.

[0122] See also Fig.13 The pixel circuit 1 further includes a second reset transistor T6, a gate of the second reset transistor T6 is electrically connected to the fourth scan line S4, a first electrode receives a reset signal, and a second electrode is electrically connected to the fourth node N4.

[0123] Combine the following Fig.13 and Fig.14 Taking the case where all transistors in the pixel circuit 1 are N-type transistors and the first electrode of the second reset transistor T6 is electrically connected to the second reset line Ref2 as an example, the working process of the pixel circuit 1 is described:

[0124] In the reset phase t1', the third scan line S3 provides a high level to control the second transistor T5 to turn on, and write the first reset signal of the first reset line Ref1 into the first node N1; the fourth scan line S4 provides a high level to control the second reset transistor T6 to turn on, and write the second reset signal of the second reset line Ref2 into the fourth node N4, and at the same time couple downward to the third node N3. In this phase, V N1 =V ref1 , V N4 =V ref2 .

[0125] In the threshold compensation stage t2', the second transistor T5 and the second reset transistor T6 are continuously turned on; the first scan line S3 provides a high level to control the first transistor T3 to turn on, write the signal of the first power line PVDD into the second node, and the third node N3 captures the threshold voltage to perform threshold compensation on the driving transistor T0. In this stage, VN1 =V ref1 , V N2 =V PVDD , V N4 =V ref2 , V N3 =V ref1 -Vth.

[0126] In the data writing phase t3', the second scan line S2 provides a high level to control the data writing transistor T4 to turn on, and write the signal of the data line Data into the first node N1. N1 =V Data , the voltage of the first node N1 is V ref1 Change to V Data , under the action of the first capacitor C1 and the second capacitor C2, the potential of the third node N3 changes synchronously with the potential of the first node N1,

[0127] In the light emitting stage Te, the light emitting control line Emit provides a high level to control the first light emitting control transistor T1 and the second light emitting control transistor T2 to be turned on, so that the driving current flows into the light emitting element 2. The driving current I flowing into the light emitting element 2 in this stage is I=k×(V gs -Vth) 2 , Then we can conclude

[0128] Regarding the control unit 3, in another feasible implementation manner, as Fig.17 As shown, Fig.17 This is another structural diagram of a pixel circuit provided by an embodiment of the present invention, the first transistor T3 is electrically connected to the first node N1. The first electrode of the second transistor T5 is electrically connected to the first node N1, and the second electrode is electrically connected to the second node N2.

[0129] Based on this structure, the control unit 3 writes the constant voltage signal to the first node N1 and the second node N2 specifically means: using the first transistor T3 to write the first power signal provided by the first power line PVDD to the first node N1, and then using the second transistor T5 to further write the first power signal of the first node N1 to the second node N2. In this structure, the constant voltage signal written to the first node N1 and the second node N2 is the same.

[0130] Further, such as Fig.18 As shown, Fig.18 for Fig.17 In a corresponding timing diagram, the driving cycle DC of the pixel circuit 1 includes a writing frame WF, and the writing frame WF includes a reset phase t1 ′, a threshold compensation phase t2 ′ and a data writing phase t3 ′.

[0131] In the reset phase t1 ′, the first transistor T3 is turned on, the constant voltage signal of the first power line PVDD is written into the first node N1 , and the first node N1 is reset by the first reset signal.

[0132] In the threshold compensation stage t2', the first transistor T3 and the second transistor T5 are turned on, the constant voltage signal of the first power line PVDD is written into the first node N1 and the second node N2, the third node N3 captures the threshold voltage, and the threshold compensation is performed on the driving transistor T0.

[0133] In the data writing phase t3 ′, the data writing transistor T4 is turned on to write the signal of the data line Data into the first node N1 .

[0134] In the above structure, in the threshold compensation stage t2', the third node N3 captures the threshold voltage and performs threshold compensation on the driving transistor T0, and in the data line Data writing stage, the data signal is written into the first node N1. The threshold compensation and data writing under this design are performed step by step, which can ensure that the time for threshold compensation and data writing is more sufficient, so that charging and compensation are more sufficient.

[0135] In one possible implementation, see Fig.17 and Fig.19 , Fig.19 This is another structural schematic diagram of a pixel circuit provided in an embodiment of the present invention. The pixel circuit 1 also includes a first reset transistor T7, a gate of the first reset transistor T7 is electrically connected to the fourth scan line S4, a first electrode receives a reset signal at least when the first reset transistor T7 is turned on, and a second electrode is electrically connected to the third node N3 or the second node N2.

[0136] The first reset transistor T7 is set, and the reset signal received by the first reset transistor T7 can be written into the third node N3 or the second node N2, thereby resetting the third node N3 or the second node N2 before charging, and resetting the driving transistor T0 more fully, so that it is configured to a more certain initial state, which helps to improve charging uniformity.

[0137] Furthermore, combined with Fig.17 and Fig.18 , the driving cycle DC of the pixel circuit 1 includes a writing frame WF, and the writing frame WF includes a reset phase t1'. In the reset phase t1', the first transistor T3 is turned on, and the constant voltage signal of the first power line PVDD is written into the first node N1, and the first node N1 is reset; the first reset transistor T7 is turned on, and the reset signal it receives is written into the third node N3 or the second node N2 connected thereto, and the third node N3 or the second node N2 is reset.

[0138] See also Fig.17The pixel circuit 1 further includes a second reset transistor T6, a gate of the second reset transistor T6 is electrically connected to the fourth scan line S4, a first electrode receives a reset signal, and a second electrode is electrically connected to the fourth node N4.

[0139] Combine the following Fig.17 and Fig.18 Taking the case where all transistors in the pixel circuit 1 are N-type transistors and the first electrode of the second reset transistor T6 is electrically connected to the second reset line Ref2 as an example, the working process of the pixel circuit 1 is described:

[0140] In the reset phase t1', the first scan line S1 provides a high level to control the first transistor T3 to turn on, and write the signal of the first power line PVDD into the first node N1; the fourth scan line S4 provides a high level to control the first reset transistor T6 and the second reset transistor T6 to turn on, write the signal of the first reset line Ref1 into the third node N3, and write the signal of the second reset line Ref2 into the fourth node N4. In this phase, V N1 =V PVDD , V N3 =V ref1 , V N4 =V ref2 .

[0141] In the threshold compensation stage t2', the first transistor T3 is continuously turned on; the third scan line S3 provides a high level to control the second transistor T5 to turn on, and the third node N3 captures the threshold voltage to perform threshold compensation on the driving transistor T0. N1 =V N2 =V PVDD , V N3 =V PVDD -Vth.

[0142] In the data writing phase t3', the second scan line S2 provides a high level to control the data writing transistor T4 to turn on, and write the signal of the data line Data into the first node N1. In this phase, V N1 =V Data , the voltage of the first node N1 is V PVDD Change to V Data , under the action of the first capacitor C1 and the second capacitor C2, the potential of the third node N3 changes synchronously with the potential of the first node N1,

[0143] In the light emitting stage Te, the light emitting control line Emit provides a high level to control the first light emitting control transistor T1 and the second light emitting control transistor T2 to be turned on, so that the driving current flows into the light emitting element 2. The driving current I flowing into the light emitting element 2 in this stage is I=k×(V gs -Vth) 2 .in, Then we can conclude

[0144] In a feasible implementation, the first electrode of the first reset transistor T7 is electrically connected to a reset line for providing a reset signal. Fig.17 and Fig.19 , a first electrode of the first reset transistor T7 is electrically connected to the first reset line Ref1.

[0145] In this configuration, the first electrode of the first reset transistor T7 continuously receives a stable reset signal, and when the first reset transistor T7 is turned on, the second node N2 or the third node N3 can be reset better.

[0146] Furthermore, if Fig. 20 and Fig.21 As shown, Fig. 20 Schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention. Fig.21 This is another structural diagram of a pixel circuit provided by an embodiment of the present invention. The pixel circuit 1 further includes a second reset transistor T6 . The gate of the second reset transistor T6 is electrically connected to the fourth scan line, and the second electrode is electrically connected to the light emitting element 2 .

[0147] The first electrode of the second reset transistor T6 and the first electrode of the first reset transistor T7 are electrically connected to the same reset line. For example, the first reset transistor T7 and the second reset transistor T6 are both electrically connected to the first reset line Ref1.

[0148] In this configuration, only one reset line is required for the first reset transistor T7 and the second reset transistor T6, and the anode of the light emitting element 2 and the second node N2 or the third node N3 are reset using the same reset voltage, thereby saving the number of signal lines in the display panel.

[0149] Alternatively, see Fig.17 and Fig.18 The second reset transistor T6 and the first reset transistor T7 can also be electrically connected to different reset lines. The first reset transistor T7 is electrically connected to the first reset line Ref1, and the gate of the second reset transistor T6 is electrically connected to the second reset line Ref2, so that different reset voltages can be set for the light emitting element 2 and the driving transistor T0, and the reset of the light emitting element 2 and the driving transistor T0 is more flexible.

[0150] In a possible implementation, Fig. 22 and Fig.23 As shown, Fig. 22 Schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention. Fig.23This is another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention. The pixel circuit 1 further includes a second reset transistor T6 , a gate of the second reset transistor T6 is electrically connected to the fourth scan line S4 , a first electrode receives a reset signal, and a second electrode is electrically connected to the light emitting element 2 .

[0151] The first electrode of the first reset transistor T7 is electrically connected to the second electrode of the second reset transistor T6 , that is, the first electrode of the first reset transistor T7 is electrically connected to the fourth node N4 .

[0152] In the reset phase t1', the second reset transistor T6 is turned on, and the reset signal received by it is written into the fourth node N4, and then written into the second node N2 or the third node N3 via the first reset transistor T7, so that the second node N2 or the third node N3 can still be normally reset.

[0153] In a possible implementation, Fig.24 As shown, Fig.24 Another structural diagram of a pixel circuit provided by an embodiment of the present invention is shown in which the second plate of the second capacitor C2 is electrically connected to the first power line PVDD. Alternatively, the second plate of the second capacitor C2 receives a reset signal, for example, the second plate of the second capacitor C2 is electrically connected to the first reset line Ref1 to which the second transistor T5 is connected.

[0154] In this structure, the second electrode of the second capacitor C2 receives a stable constant voltage signal, and the second capacitor C2 can better act on the potential of the third node N3.

[0155] Or, in another possible implementation, see Fig.13 The pixel circuit 1 further includes a second reset transistor T6, a gate of the second reset transistor T6 is electrically connected to the fourth scan line S4, a first electrode receives a reset signal, and a second electrode is electrically connected to the light emitting element 2. The second plate of the second capacitor C2 is electrically connected to the second electrode of the second reset transistor T6, that is, the second plate of the second capacitor C2 is electrically connected to the fourth node N4.

[0156] In this structure, when the second reset transistor T6 is turned on, the reset signal it receives is written into the fourth node N4, so that the second plate of the second capacitor C2 can receive a stable constant voltage signal, and the second capacitor C2 can better act on the potential of the third node N3.

[0157] In a possible implementation, Fig.25 and Fig.26 As shown, Fig.25 Schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention. Fig.26In another structural diagram of a pixel circuit provided by an embodiment of the present invention, at least one gate of the driving transistor T0 further includes a second gate. That is, the driving transistor T0 is a double-gate transistor including a top gate and a bottom gate, wherein the top gate is the first gate and the bottom gate is the second gate.

[0158] See also Fig.25 The second gate is electrically connected to the first power line PVDD, or the second gate receives a reset signal, for example, the second gate is electrically connected to the first reset line Ref1 connected to the second transistor T5.

[0159] Alternatively, see Fig.26 The pixel circuit 1 further includes a second reset transistor T6, a gate of the second reset transistor T6 being electrically connected to the fourth scan line S4, a first electrode receiving a reset signal, and a second electrode being electrically connected to the light emitting element 2. The second gate is electrically connected to the second electrode of the second reset transistor T6, that is, the second gate is electrically connected to the fourth node N4.

[0160] The driving transistor T0 adopts a dual-gate transistor design, which helps to improve the stability and mobility of the driving transistor T0, and its device characteristics are better.

[0161] In an embodiment of the present invention, other transistors in the pixel circuit 1 except the driving transistor T0 may also be dual-gate transistors, that is, at least one of the first light-emitting control transistor T1, the second light-emitting control transistor T2, the first transistor T3, the data writing transistor T4, the second transistor T5 and the second reset transistor T6 is a single-gate transistor, and / or, at least one of the first light-emitting control transistor T1, the second light-emitting control transistor T2, the first transistor T3, the data writing transistor T4, the second transistor T5 and the second reset transistor T6 is a dual-gate transistor.

[0162] For example, see Fig. 27 The second transistor T5 can be designed as a double-gate transistor to reduce the leakage current of the first node N1, the data write transistor T4 can be designed as a double-gate transistor to reduce the leakage current of the third node N3, and the second reset transistor T6 can be designed as a double-gate transistor to reduce the leakage current of the fourth node N4.

[0163] When at least one of the first light-emitting control transistor T1, the second light-emitting control transistor T2, the first transistor T3, the data writing transistor T4, the second transistor T5 and the second reset transistor T6 is a dual-gate transistor, the connection method of the gate of these transistors described above is the top gate connection method, and the bottom gate can be electrically connected to the top gate, the first electrode or the second electrode of the transistor.

[0164] In a possible implementation, combining Figure 4 , Fig. 9 and Fig.10 , combined Figure 13 to Figure 15 , and combined Fig.17 and Fig.18 The pixel circuit 1 further includes a second reset transistor T6 , a gate of the second reset transistor T6 is electrically connected to the fourth scan line S4 , a first electrode is electrically connected to receive a reset signal, and a second electrode is electrically connected to the light emitting element 2 .

[0165] At the first frequency f1, the driving cycle DC of the pixel circuit 1 includes a writing frame WF and a holding frame HF. In the holding frame HF, the second reset transistor T6 is turned on at least once to write the reset signal received by it into the light emitting element 2. Specifically, the second reset transistor T6 is turned on at least once in the non-light emitting stage T-ne of the holding frame HF.

[0166] In the holding frame HF, the fourth scan line S4 provides an enable level to control the second reset transistor T6 to turn on, reset the fourth node N4, eliminate the influence of the anode residual charge, avoid interference with the current injection during the next light emission, and improve the light emission reliability.

[0167] It should be noted that the duration of the enable level provided by the fourth scan line S4 in the write frame WF and the hold frame HF may be equal or unequal. For example, the duration of the enable level provided by the fourth scan line S4 in the hold frame HF may be shorter than the duration of the enable level provided by the fourth scan line S4 in the write frame WF.

[0168] Furthermore, combined with Fig.17 and Fig.18 When the pixel circuit includes the first reset transistor T7, when maintaining the frame HF, the first reset transistor T7 can also be controlled to be turned on at least once, the third node N3 or the second node N2 is reset at least once, and the bias voltage of the driving transistor T0 is adjusted, thereby adjusting the bias state of the driving transistor T0, improving the brightness difference and afterimage of the first frame caused by the transistor hysteresis effect, and improving the flicker problem at low frequency.

[0169] In particular, when the first reset transistor T7 and the second reset transistor T6 are both electrically connected to the fourth scan line S4, in the hold frame HF, the fourth scan line S4 provides at least one enable level, which can simultaneously reset the fourth node N4, the third node N3 or the second node N2 at least once.

[0170] In a possible implementation, combining Figure 4 , Fig. 9 and Fig.10, under the first frequency f1, the driving cycle DC of the pixel circuit 1 includes a writing frame WF and a holding frame HF. In the holding frame HF, the data writing transistor T4 is turned on at least once to write the signal of the data line Data into the second node N2 or the third node N3 connected thereto. Specifically, the data writing transistor T4 is turned on at least once in the non-light emitting phase T-ne of the holding frame HF.

[0171] In the holding frame HF, the second scan line S2 provides an enable level to control the data writing transistor T4 to turn on, and writes the signal of the data line Data into the second node N2 or the third node N3 connected to it, so as to adjust the bias state of the driving transistor T0, thereby improving the brightness difference and afterimage of the first frame caused by the transistor hysteresis effect, and improving the flicker problem at low frequency.

[0172] It should be noted that the duration of the enable level provided by the second scanning line S2 in the writing frame WF and the holding frame HF may be equal or unequal. Fig. 9 , the duration of the enable level provided by the second scan line S2 in the hold frame HF is shorter than the duration of the enable level provided by the second scan line S2 in the write frame WF, or, see Fig.10 , the duration of the enable level provided by the second scan line S2 in the hold frame HF is equal to the duration of the enable level provided by the second scan line S2 in the write frame WF.

[0173] In addition, it should be noted that in the holding frame HF, when the fourth scan line S4 provides an enable level to control the second reset transistor T6 to also turn on, the duration of the enable level provided by the second scan line S2 and the duration of the enable level provided by the fourth scan line S4 can be equal or different. Fig. 9 , the duration of the enable level provided by the fourth scan line S4 may be greater than the duration of the enable level provided by the second scan line S2, so as to reset the anode of the light emitting element 2 for a longer time. In addition, in the hold frame HF, the enable level provided by the second scan line S2 and the enable level provided by the fourth scan line S4 may overlap or may not overlap. For example, see Fig. 9 , the enable level provided by the second scan line S2 does not overlap with the enable level provided by the fourth scan line S4.

[0174] In one possible implementation, see Figure 4 The pixel circuit 1 further includes a data writing transistor T4, a second transistor T5 and a second reset transistor T6.

[0175] The gate of the data writing transistor T4 is electrically connected to the second scan line S2, the first electrode is electrically connected to the data line Data, and the second electrode is electrically connected to the driving transistor T0. The second electrode of the data writing transistor T4 can be electrically connected to the first node N1, the second node N2 or the third node N3. These structures have been described in the above embodiments and will not be repeated here.

[0176] The gate of the second transistor T5 is electrically connected to the third scan line S3, and the first electrode and / or the second electrode is electrically connected to the driving transistor T0. The second transistor T5 may have its second electrode electrically connected to the first node N1, or may have its first electrode electrically connected to the first node N1, and its second electrode electrically connected to the second node N2 or the third node N3. These structures have been described in the above embodiments and will not be repeated here.

[0177] A first electrode of the second reset transistor T6 receives a reset signal, and a second electrode is electrically connected to the light emitting element 2 .

[0178] In one possible implementation, see Figure 4 , the first light emission control transistor T1 and the second light emission control transistor T2 are both N-type transistors, for example, both are IGZO transistors, which have a small leakage current, and the circuit characteristics of the pixel circuit 1 are better. At this time, the first light emission control transistor T1 and the second light emission control transistor T2 respond to the high level provided by the light emission control line Emit to be turned on and the low level to be turned off.

[0179] Further, see Figure 4 The first transistor T3 , the data writing transistor T4 , the second transistor T5 , and the second reset transistor T6 are all N-type transistors, for example, all IGZO transistors.

[0180] In this design, all transistors in the pixel circuit 1 are N-type transistors, the film layer design of the transistors is consistent, and the panel uniformity is better. Moreover, this type of transistor has a small leakage current, which can effectively improve the leakage problem of the driving transistor T0 and stabilize the node voltage of the driving transistor T0.

[0181] Or, in another feasible implementation, as Fig. 27 and Fig.28 As shown, Fig. 27 Schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention. Fig.28 for Fig. 27In a corresponding timing diagram, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are both P-type transistors, for example, both are LTPS transistors. The first light-emitting control transistor T1 and the second light-emitting control transistor T2 under this structure have higher electron mobility, and the transistor response speed is faster. At this time, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 respond to the low level provided by the light-emitting control line Emit to turn on and the high level to turn off.

[0182] Furthermore, if Fig.29 As shown, Fig.29 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention, the first light-emitting control transistor T1 includes two first sub-transistors T01 connected in series, and the gates of the two first sub-transistors T01 are electrically connected. The second light-emitting control transistor T2 includes two second sub-transistors T02 connected in series, and the gates of the two second sub-transistors T02 are electrically connected.

[0183] When the first light emission control transistor T1 and the second light emission control transistor T2 are designed as P-type transistors, making the two light emission control transistors each include two sub-transistors connected in series can help reduce the leakage current of the two light emission control transistors and optimize the circuit characteristics of the pixel circuit 1.

[0184] In a possible implementation, Fig.30 As shown, Fig.30 This is another structural diagram of a pixel circuit provided by an embodiment of the present invention, the type of the second reset transistor T6 is opposite to the type of the first light emission control transistor T1 and the second light emission control transistor T2. The gate of the second reset transistor T6 is electrically connected to the light emission control signal line.

[0185] That is, when the first emission control transistor T1 and the second emission control transistor T2 are N-type transistors, the second reset transistor T6 is a P-type transistor. When the first emission control transistor T1 and the second emission control transistor T2 are P-type transistors, the second reset transistor T6 is an N-type transistor.

[0186] When the type of the second reset transistor T6 is opposite to that of the two light-emitting control transistors, the second reset transistor T6 can be connected to the light-emitting control line Emit. In the non-light-emitting stage T-ne, the light-emitting control line Emit controls the two light-emitting control transistors to be turned off, and controls the second reset transistor T6 to be turned on, so that the anode of the light-emitting element 2 can be continuously reset. In the light-emitting stage Te, the light-emitting control line Emit controls the two light-emitting control transistors to be turned on, and the second reset transistor T6 is turned off, so as to avoid the second reset transistor T6 from affecting the anode potential of the light-emitting element 2.

[0187] With such configuration, under the premise of ensuring the normal operation of the pixel circuit 1 , there is no need to configure an additional scanning line for the second reset transistor T6 , thereby reducing the number of signal lines in the panel.

[0188] In one possible implementation, see Fig.30 The second transistor T5 is an N-type transistor, such as an IGZO transistor. The second transistor T5 is electrically connected to the driving transistor T0. Designing it as an N-type transistor can reduce the influence of leakage on the node voltage of the driving transistor T0.

[0189] Further, see Figure 4 and Fig.32 At least one of the data writing transistor T4 and the first transistor T3 is an N-type transistor, and / or at least one of the data writing transistor T4 and the first transistor T3 is a P-type transistor.

[0190] When the data writing transistor T4 and / or the first transistor T3 are P-type transistors, the data writing transistor T4 and / or the first transistor T3 have a higher electron mobility and a faster transistor response speed. At this time, the data writing transistor T4 is turned on in response to a low level provided by the second scan line S2 and is turned off in response to a high level, and / or the first transistor T3 is turned on in response to a low level provided by the first scan line S1 and is turned off in response to a high level.

[0191] When the data writing transistor T4 and / or the first transistor T3 are N-type transistors, the leakage current of the data writing transistor T4 and / or the first transistor T3 is small, which can reduce the influence of the leakage on the node potential of the driving transistor T0. At this time, the data writing transistor T4 is turned on and the low level is turned off in response to the high level passed by the second scanning line S2, and / or the first transistor T3 is turned on and the low level is turned off in response to the high level provided by the first scanning line S1.

[0192] In a possible implementation, Fig.31 As shown, Fig.31 This is another structural diagram of a display panel provided by an embodiment of the present invention, in which the gate of the second reset transistor T6 is electrically connected to the fourth scan line S4.

[0193] The display panel further includes a first shift register 01 , a second shift register 02 , a third shift register 03 , a fourth shift register 04 , a fifth shift register 05 and a sixth shift register 06 .

[0194] Among them, the first shift register 01 is electrically connected to the first scan line S1, the second shift register 02 and the third shift register 03 are both electrically connected to the second scan line S2, the fourth shift register 04 is electrically connected to the third scan line S3, the fifth shift register 05 is electrically connected to the fourth scan line, and the sixth shift register 06 is electrically connected to the light emitting control line Emit.

[0195] The display panel further includes a display area AA. The second shift register 02 and the third shift register 03 are respectively located at two opposite sides of the display area AA, two of the first shift register 01, the fourth shift register 04, the fifth shift register 05 and the sixth shift register 06 are located at one side of the display area AA, and the other two are located at the other side of the display area AA.

[0196] The second scan line S2 controls data writing, and its signal stability has a greater impact on brightness. Therefore, the second shift register 02 and the third shift register 03 can be used to perform bilateral driving on the second scan line S2 to improve the driving capability of the second scan signal. On this basis, two of the first shift register 01, the fourth shift register 04, the fifth shift register 05 and the sixth shift register 06 are located on one side of the display area AA with the second shift register 02, and the other two of the fourth shift register 04, the fifth shift register 05 and the sixth shift register 06 are located on the other side of the display area AA with the third shift register 03, so that the number of shift registers set on both sides of the display area AA is equal, which helps to optimize the left and right frame design of the display panel.

[0197] Furthermore, if Fig.32 As shown, Fig.32 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. The display panel may further include a seventh shift register 07 , an eighth shift register 08 , a ninth shift register 09 and a tenth shift register 010 .

[0198] The seventh shift register 07 is electrically connected to the light emitting control line Emit, and the seventh shift register 07 and the sixth shift register 06 are respectively located at two opposite sides of the display area AA.

[0199] The eighth shift register 08 is electrically connected to the first scan line S1 . The eighth shift register 08 and the first shift register 01 are respectively located at two opposite sides of the display area AA.

[0200] The ninth shift register 09 is electrically connected to the third scan line S3 . The ninth shift register 09 and the fourth shift register 04 are respectively located at two opposite sides of the display area AA.

[0201] The tenth shift register 010 is electrically connected to the fourth scan line S4 . The tenth shift register 010 and the fifth shift register 05 are respectively located at two opposite sides of the display area AA.

[0202] In the above structure, the first scan line S1, the third scan line S3, the fourth scan line S4 and the light-emitting control line Emit are all driven on both sides, and the driving capabilities of these signals are improved. On this basis, the number of shift registers set on both sides of the display area AA is equal, which helps to optimize the design of the left and right borders of the display panel. This design is more suitable for large-size display panels, which have sufficient left and right border space to accommodate more shift registers.

[0203] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.33 As shown, Fig.33 1 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. Of course, Fig.33 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0204] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0205] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: A pixel circuit is included, wherein the pixel circuit includes: A driving transistor, wherein the driving transistor is an N-type transistor; a first light emission control transistor and a second light emission control transistor, wherein a gate of the first light emission control transistor and a gate of the second light emission control transistor are electrically connected to the same light emission control line, a first electrode of the first light emission control transistor is electrically connected to a first power supply line, and a second electrode is electrically connected to a first electrode of the driving transistor, and a first electrode of the second light emission control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode is electrically connected to a light emitting element; A first transistor, wherein a gate of the first transistor is electrically connected to the first scanning line, a first electrode is electrically connected to the first power line, and a second electrode is electrically connected to the driving transistor.

2. The display panel according to claim 1, characterized in that: The driving cycle of the pixel circuit includes at least one frame, and one frame includes a non-light-emitting phase and a light-emitting phase; in the non-light-emitting phase, the first light-emitting control transistor and the second light-emitting control transistor are turned off, and in at least a part of the light-emitting phase, the first light-emitting control transistor and the second light-emitting control transistor are turned on; The frame in the driving cycle includes a writing frame. During a partial time period of the non-light-emitting phase of the writing frame, the first transistor is turned on to write a signal of the first power line into the driving transistor.

3. The display panel according to claim 1, characterized in that: The driving cycle of the pixel circuit includes at least one frame, and one frame includes a non-luminous phase and a luminous phase; in the non-luminous phase, the first luminous control transistor and the second luminous control transistor are turned off, and in the luminous phase, the luminous control line provides at least two pulses.

4. The display panel according to claim 1, characterized in that: The driving transistor includes at least one gate, the at least one gate includes a first gate, the first gate of the driving transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node; The pixel circuit further includes a data writing transistor and a second transistor; wherein a gate of the data writing transistor is electrically connected to the second scanning line, and a first electrode is electrically connected to the data line; a gate of the second transistor is electrically connected to the third scanning line, and a second electrode is electrically connected to the first node; one of the second electrode of the data writing transistor and the first electrode of the second transistor is electrically connected to the second node, and the other is electrically connected to the third node; The second electrode of the first transistor is electrically connected to the second transistor.

5. The display panel according to claim 4, characterized in that: The driving cycle of the pixel circuit includes a writing frame, and the writing frame includes a reset phase and a data writing and compensation phase; In the reset phase, the first transistor and the second transistor are turned on, and the signal of the first power line is written into the first node, and into the second node or the third node connected to the second transistor; In the data writing and compensation phase, the data writing transistor and the second transistor are turned on, the signal of the data line is written into the first node, and threshold compensation is performed on the driving transistor.

6. The display panel according to claim 5, characterized in that: A first intermediate stage is also included between the reset stage and the data writing and compensation stage; In the first intermediate stage, the first transistor and the data writing transistor are turned off, and the second transistor is turned on.

7. The display panel according to claim 5, characterized in that: A first intermediate stage is also included between the reset stage and the data writing and compensation stage; In the first intermediate stage, the first transistor and the second transistor are turned off, the data writing transistor is turned on, and the signal of the data line is written into the second node or the third node connected to the data writing transistor.

8. The display panel according to claim 4, characterized in that: A second electrode of the first transistor is electrically connected to the first node.

9. The display panel according to claim 4, characterized in that: The second electrode of the first transistor is electrically connected to the first electrode of the second transistor.

10. The display panel according to claim 1, characterized in that: The driving transistor includes at least one gate, the at least one gate includes a first gate, the first gate of the driving transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node; The pixel circuit further includes a data writing transistor, wherein a gate of the data writing transistor is electrically connected to the second scanning line, a first electrode is electrically connected to the data line, and a second electrode is electrically connected to the first node; The pixel circuit further includes a control unit, the control unit includes the first transistor and the second transistor, the gate of the second transistor is electrically connected to the third scan line, and the first electrode and / or the second electrode is electrically connected to the driving transistor; The control unit is used to write a constant voltage signal to the first node and the second node.

11. The display panel according to claim 10, characterized in that: The pixel circuit also includes a first capacitor and a second capacitor; wherein the first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the third node, and the first plate of the second capacitor receives a constant voltage signal in at least part of the time period, and the second plate is electrically connected to the third node.

12. The display panel according to claim 10, characterized in that: The first transistor is electrically connected to the second node, and a first electrode of the second transistor is electrically connected to a first reset line, and a second electrode of the second transistor is electrically connected to the first node.

13. The display panel according to claim 12, characterized in that: The driving cycle of the pixel circuit includes a writing frame, and the writing frame includes a reset phase, a threshold compensation phase and a data writing phase; In the reset phase, the second transistor is turned on to write the constant voltage signal of the first reset line into the first node; In the threshold compensation stage, the second transistor is turned on, the constant voltage signal of the first reset line is written into the first node, the first transistor is turned on, the constant voltage signal of the first power line is written into the second node, and the threshold compensation is performed on the driving transistor; In the data writing phase, the data writing transistor is turned on to write the voltage of the data line into the first node.

14. The display panel according to claim 12, characterized in that: The display panel includes a plurality of circuit rows arranged along a first direction, the circuit rows include a plurality of pixel circuits arranged along a second direction, and the first direction intersects the second direction; The third scan line connected to the i-th circuit row is electrically connected to the first scan line connected to the ix-th circuit row, x≥1; Alternatively, the first scan line connected to the ith circuit row is electrically connected to the third scan line connected to the ixth circuit row.

15. The display panel according to claim 10, characterized in that: The first transistor is electrically connected to the first node, and the second transistor has a first electrode electrically connected to the first node and a second electrode electrically connected to the second node.

16. The display panel according to claim 15, characterized in that: The driving cycle of the pixel circuit includes a writing frame, and the writing frame includes a reset phase, a threshold compensation phase and a data writing phase; In the reset phase, the first transistor is turned on to write the constant voltage signal of the first power line into the first node; In the threshold compensation stage, the first transistor and the second transistor are turned on, and the constant voltage signal of the first power line is written into the first node and the second node to perform threshold compensation on the driving transistor; In the data writing phase, the data writing transistor is turned on to write the signal of the data line into the first node.

17. The display panel according to claim 15, characterized in that: The pixel circuit further includes a first reset transistor, a gate of the first reset transistor being electrically connected to the fourth scan line, a first electrode receiving a reset signal at least when the first reset transistor is turned on, and a second electrode being electrically connected to the third node or the second node.

18. The display panel according to claim 17, characterized in that: The driving cycle of the pixel circuit includes a writing frame, and the writing frame includes a reset phase; In the reset phase, the first transistor is turned on to write the constant voltage signal of the first power line into the first node, and the first reset transistor is turned on to write the reset signal it receives into the third node or the second node to which it is connected.

19. The display panel according to claim 17, characterized in that: A first electrode of the first reset transistor is electrically connected to a reset line for providing the reset signal.

20. The display panel according to claim 19, characterized in that: The pixel circuit further includes a second reset transistor, wherein a gate of the second reset transistor is electrically connected to the fourth scan line, and a second electrode of the second reset transistor is electrically connected to the light emitting element; The first electrode of the second reset transistor and the first electrode of the first reset transistor are electrically connected to the same reset line.

21. The display panel according to claim 17, characterized in that: The pixel circuit further includes a second reset transistor, wherein a gate of the second reset transistor is electrically connected to the fourth scan line, a first electrode receives a reset signal, and a second electrode is electrically connected to the light emitting element; The first electrode of the first reset transistor is electrically connected to the second electrode of the second reset transistor.

22. The display panel according to claim 11, characterized in that: The second plate of the second capacitor is electrically connected to the first power line, or the second plate of the second capacitor receives a reset signal.

23. The display panel according to claim 11, characterized in that: The pixel circuit further includes a second reset transistor, wherein a gate of the second reset transistor is electrically connected to the fourth scan line, a first electrode receives a reset signal, and a second electrode is electrically connected to the light emitting element; The second plate of the second capacitor is electrically connected to the second electrode of the second reset transistor.

24. The display panel according to claim 1, characterized in that: The at least one gate of the driving transistor further includes a second gate; wherein, The second gate is electrically connected to the first power line; Alternatively, the second gate receives a reset signal; Alternatively, the pixel circuit further includes a second reset transistor, a gate of the second reset transistor being electrically connected to the fourth scan line, a first electrode receiving a reset signal, and a second electrode being electrically connected to the light emitting element; and the second gate being electrically connected to a second electrode of the second reset transistor.

25. The display panel according to claim 1, characterized in that: The pixel circuit further includes a second reset transistor, wherein a gate of the second reset transistor is electrically connected to the fourth scan line, a first electrode is electrically connected to receive a reset signal, and a second electrode is electrically connected to the light emitting element; At the first frequency, the driving cycle of the pixel circuit includes a writing frame and a holding frame. In the holding frame, the second reset transistor is turned on at least once to write the reset signal received by the second reset transistor into the light emitting element.

26. The display panel according to claim 4, characterized in that: At the first frequency, the driving cycle of the pixel circuit includes a writing frame and a holding frame. In the holding frame, the data writing transistor is turned on at least once to write the signal of the data line into the second node or the third node connected thereto.

27. The display panel according to claim 1, characterized in that: The pixel circuit further comprises: a data writing transistor, wherein a gate of the data writing transistor is electrically connected to the second scanning line, a first electrode is electrically connected to the data line, and a second electrode is electrically connected to the driving transistor; a second transistor, wherein a gate of the second transistor is electrically connected to the third scan line, and a first electrode and / or a second electrode of the second transistor is electrically connected to the driving transistor; A second reset transistor, wherein a first electrode of the second reset transistor receives a reset signal and a second electrode is electrically connected to the light emitting element.

28. The display panel according to claim 27, characterized in that: The first light emission control transistor and the second light emission control transistor are both N-type transistors.

29. The display panel according to claim 28, characterized in that: The first transistor, the data writing transistor, the second transistor and the second reset transistor are all N-type transistors.

30. The display panel according to claim 27, characterized in that: The first light emission control transistor and the second light emission control transistor are both P-type transistors.

31. The display panel according to claim 30, characterized in that: The first light emission control transistor includes two first sub-transistors connected in series, and the gates of the two first sub-transistors are electrically connected; The second light emission control transistor includes two second sub-transistors connected in series, and the gates of the two second sub-transistors are electrically connected.

32. The display panel according to claim 28 or 30, characterized in that: The type of the second reset transistor is opposite to that of the first light emission control transistor and the second light emission control transistor, and a gate of the second reset transistor is electrically connected to the light emission control signal line.

33. The display panel according to claim 28 or 30, characterized in that: The second transistor is an N-type transistor; At least one of the data writing transistor and the first transistor is an N-type transistor, and / or at least one of the data writing transistor and the first transistor is a P-type transistor.

34. The display panel according to claim 27, characterized in that: The gate of the second reset transistor is electrically connected to the fourth scan line; The display panel further includes: a first shift register electrically connected to the first scan line; The second shift register and the third shift register are both electrically connected to the second scan line; a fourth shift register electrically connected to the third scan line; a fifth shift register electrically connected to the fourth scan line; a sixth shift register, electrically connected to the light emitting control line; Wherein, the display panel also includes a display area, the second shift register and the third shift register are respectively located on opposite sides of the display area, two of the first shift register, the fourth shift register, the fifth shift register and the sixth shift register are located on one side of the display area, and the other two are located on the other side of the display area.

35. The display panel according to claim 34, characterized in that: The display panel further includes: a seventh shift register, electrically connected to the light-emitting control line, and located on two opposite sides of the display area with the sixth shift register; an eighth shift register, electrically connected to the first scan line, and located on two opposite sides of the display area with the first shift register; a ninth shift register, electrically connected to the third scan line, and located on two opposite sides of the display area with the fourth shift register; The tenth shift register is electrically connected to the fourth scan line and is located on two opposite sides of the display area with the fifth shift register.

36. A display device, characterized in that: Comprising the display panel as described in any one of claims 1 to 35.

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