Display device

Abstract

The invention relates to a display device. The display device includes: at least one pixel configured to receive a voltage of an initialization power source supplied to an anode electrode of a light emitting element of the at least one pixel when an enable scan signal is supplied to a scan line; and a scan driver. The scan driver is configured to supply the enable scan signal to the scan line. The enable scan signals supplied to the scan lines by the scan driver have the same width during an active region of a frame regardless of an image refresh rate, and the enable scan signals are not the same width during a blanking region of the frame regardless of the image refresh rate. The width of the enable scan signal supplied to the scan line is changed by the scan driver corresponding to the image refresh rate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0136139, filed on October 12, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to a display device and a method of driving the display device. Background Art

[0004] As information technology advances, the importance of display devices as a connection medium between users and information increases. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

[0005] Recent display devices provide users with images that change at a high frame rate using a high-speed driving function, and provide users with images that change at a low frame rate using a low-speed driving function. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device and a method of driving the display device, which can provide images with similar brightness when the display device is driven at a high frequency and a low frequency.

[0007] According to an embodiment of the present disclosure, a display device is provided, the display device comprising at least one pixel configured to receive a voltage of an initialization power source supplied to an anode electrode of a light-emitting element of the at least one pixel when an enable scan signal is supplied to a scan line; and a scan driver. The scan driver is configured to supply the enable scan signal to the scan line. The enable scan signal supplied to the scan line by the scan driver has the same width during an effective area of ​​a frame regardless of an image refresh rate, and during a blanking area of ​​the frame, the width of the enable scan signal supplied to the scan line is changed by the scan driver corresponding to the image refresh rate.

[0008] In an embodiment, the at least one pixel includes a driving transistor configured to control an amount of current supplied to the light emitting element. When the enable scan signal is supplied, a bias voltage is supplied to the driving transistor.

[0009] In an embodiment, when the display device is driven at a first image refresh rate, the enable scan signal supplied by the scan driver has a first width in the blanking area of ​​the frame, and when the display device is driven at a second image refresh rate lower than the first image refresh rate, the enable scan signal supplied by the scan driver has the first width and the second width in the blanking area of ​​the frame.

[0010] In an embodiment, the first image refresh rate is a driving frequency of about 10 Hz or higher, and the second image refresh rate is a driving frequency of about 1 Hz.

[0011] In an embodiment, the second width is different from the first width.

[0012] In an embodiment, when the display device is driven at the second image refresh rate, the blanking area of ​​the frame includes a first period and a second period. The scan driver supplies the enable scan signal having the first width during the first period, and supplies the enable scan signal having the second width during the second period.

[0013] In an embodiment, the first period is a period having the same time as the blanking area of ​​the frame of the first image refresh rate, and the second period is a period after the first period.

[0014] In an embodiment, the enable scan signal supplied by the scan driver has the first width and then has the second width during the second period.

[0015] In an embodiment, when the display device is driven at a first image refresh rate, the enable scan signal supplied by the scan driver has a first width in the blanking region of the frame. When the display device is driven at a second image refresh rate lower than the first image refresh rate, the enable scan signal supplied by the scan driver has the first width and the second width in the blanking region of the frame. When the display device is driven at a third image refresh rate lower than the second image refresh rate, the enable scan signal supplied by the scan driver has the first width, the second width, and the third width in the blanking region of the frame.

[0016] In an embodiment, the first width, the second width and the third width are different widths.

[0017] In an embodiment, the blanking area of ​​the frame of the second image refresh rate includes a first period and a second period. The scan driver supplies the enable scan signal having the first width during the first period, and supplies the enable scan signal having the second width during the second period.

[0018] In an embodiment, the first period is a period having the same time as the blanking area of ​​the frame of the first image refresh rate, and the second period is a period after the first period.

[0019] In an embodiment, the blanking area of ​​the frame of the third image refresh rate includes a first period, a second period, and a third period. The scan driver supplies the enable scan signal having the first width during the first period, supplies the enable scan signal having the second width during the second period, and supplies the enable scan signal having the third width during the third period.

[0020] In an embodiment, the first period and the second period correspond to periods having the same time as the blanking area of ​​the frame of the second image refresh rate, and the third period is a period after the second period.

[0021] In an embodiment, the display device further comprises a timing controller configured to control the scan driver. The timing controller comprises: an oscillator configured to generate a clock signal; a frequency determiner configured to determine the image refresh rate using the clock signal and determine the length of the blanking area of ​​the frame included in the image refresh rate; and a start signal supplier configured to supply a start signal corresponding to the image refresh rate determined by the frequency determiner and the length of the blanking area of ​​the frame to the scan driver.

[0022] In an embodiment, the start signal supplier supplies the start signal so that the width of the enable scan signal changes corresponding to the blanking area of ​​the frame.

[0023] According to an embodiment of the present disclosure, a method for driving a display device is provided. The method includes: when the display device is driven at a first image refresh rate, supplying an enable scan signal having a first width during a blanking region; and when the display device is driven at a second image refresh rate lower than the first image refresh rate, supplying the enable scan signal having the first width and having a second width during the blanking region. The first width is different from the second width.

[0024] In an embodiment, the first image refresh rate is a driving frequency of about 10 Hz or higher, and the second image refresh rate is a driving frequency of about 1 Hz.

[0025] In an embodiment, the blanking region of the second image refresh rate includes a first period and a second period, wherein the enable scan signal having the first width is supplied during the first period, and the enable scan signal having the second width is supplied during the second period.

[0026] In an embodiment, the first period is a period having the same time as the blanking area of ​​the first image refresh rate, and the second period is a period after the first period. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings in which the embodiments are shown.

[0028] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 It is shown Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0030] Figure 3 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0031] Figure 4 is shown in Figure 2. Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0032] Figure 5 is shown driving during the self-scan period Figure 3 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0033] Figure 6 is a diagram illustrating an embodiment of an emission control signal and a first scan signal supplied in an active region and a blanking region.

[0034] Figure 7 is a diagram illustrating a method of tuning a display device.

[0035] Figure 8 It is shown Figure 7 An embodiment of operation S708 is shown in FIG.

[0036] Fig. 9 and Fig.10 is a diagram showing an embodiment of a first scanning signal supplied in a blanking area corresponding to an image refresh rate.

[0037] Fig.11 It is shown Figure 1 An embodiment of a timing controller is shown in FIG.

[0038] Fig.12 It is shown Fig.11 A diagram of an embodiment of a start signal provider is shown in FIG.

[0039] Fig.13 is a diagram showing an embodiment of a first scanning signal supplied in a blanking area corresponding to an image refresh rate. DETAILED DESCRIPTION

[0040] Embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0041] In this article, when two or more elements or values ​​are described as being substantially the same or approximately equal to each other, it should be understood that these elements or values ​​are identical to each other, these elements or values ​​are equal to each other within the measurement error, or if they are not equal in measurement, as will be understood by those of ordinary skill in the art, then close enough in value to be functionally equal to each other. For example, considering the measurement in discussion and the error (for example, the limitation of the measurement system) associated with the measurement of a specific amount, the term "approximately" used in this article includes the stated value, and is expressed in the range of acceptable deviations for a specific value as determined by those of ordinary skill in the art. For example, "approximately" can be expressed in one or more standard deviations as understood by those of ordinary skill in the art. In addition, it should be understood that although a parameter can be described as having "approximately" a specific value herein, according to an embodiment, the parameter can be completely the specific value, or approximately the specific value within the measurement error range understood by those of ordinary skill in the art. Other usages of these terms and similar terms describing the relationship between components should be interpreted in a similar manner.

[0042] Some embodiments related to functional blocks, units and / or modules are described in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed by using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, the units and / or modules are programmed and controlled by using software to perform the various functions discussed in the present disclosure, and can be selectively driven by firmware and / or software. In addition, each block, each unit and / or each module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions of blocks, units and / or modules and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions of blocks, units and / or modules. In some embodiments, without departing from the scope of the present disclosure, blocks, units and / or modules can be physically divided into two or more separate blocks, two or more separate units and / or two or more separate modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically divided into more complex blocks, more complex units and / or more complex modules without departing from the scope of the present disclosure.

[0043] The term "connection" between two components may include electrical connection and physical connection, but the present disclosure is not necessarily limited thereto. For example, the term "connection" used based on a circuit diagram may represent an electrical connection, and the term "connection" used based on a cross-sectional view and a plan view may represent a physical connection.

[0044] It will be understood that although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element.

[0045] The present disclosure is not limited to the embodiments disclosed below, and can be implemented in various forms. Each embodiment disclosed below can be implemented independently or combined with at least one other embodiment before being implemented.

[0046] It will be understood that when a component is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, it can be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or there can be intervening components. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there can also be one or more intervening components. Other words used to describe relationships between components should be interpreted in a similar manner.

[0047] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 An embodiment of a scan driver and an emission driver is shown in FIG.

[0048] Reference Figure 1 , the display device 100 according to an embodiment of the present disclosure may include a pixel unit 110 (or a panel / display panel), a timing controller 120, a scan driver 130, a data driver 140, an emission driver 150, and a power supply 160. The timing controller 120 may also be referred to as a timing controller circuit, the scan driver 130 may also be referred to as a scan driver circuit, the data driver 140 may also be referred to as a data driver circuit, the emission driver 150 may also be referred to as an emission driver circuit, and the power supply 160 may also be referred to as a power supply circuit.

[0049] The display device 100 may display images at various image refresh rates (e.g., driving frequency or screen refresh rate) according to driving conditions. The image refresh rate indicates the frequency at which a data signal is written to a driving transistor of a pixel PX. For example, the image refresh rate may also be referred to as a screen scan rate or a screen refresh rate, and may indicate the frequency at which a display screen is reproduced within one second.

[0050] In an embodiment, the output frequency of the data driver 140 with respect to one horizontal line (for example, pixels PX connected to the same scan line may be classified as one horizontal line (or pixel row)) and / or the output frequency of the second scan driver 134 outputting the second scan signal (or write scan signal) may be determined corresponding to the image refresh rate. For example, the image refresh rate for driving a moving image may be a frequency of about 60 Hz or higher (for example, about 120 Hz or about 240 Hz, etc.).

[0051] For example, the display device 100 can display images corresponding to various image refresh rates from about 1 Hz to about 240 Hz. However, this is merely illustrative, and the display device 100 can also display images at an image refresh rate of, for example, about 240 Hz or higher (e.g., about 480 Hz).

[0052] The pixel unit 110 may include pixels PX, which are connected to first scan lines SL11, SL12, ... and SL1n (collectively referred to as SL1), second scan lines SL21, SL22, ... and SL2n (collectively referred to as SL2), third scan lines SL31, SL32, ... and SL3n (collectively referred to as SL3), fourth scan lines SL41, SL42, ... and SL4n (collectively referred to as SL4), data lines DL1, DL2, ... and DLm, emission control lines EL1, EL2, ... and ELo (collectively referred to as EL), and power lines PL1, PL2, PL3, PL4 and PL5 (wherein each of n, m and o is an integer of 2 or greater).

[0053] In the example, also refer to Figure 3 , the pixel PXij located on the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk and the j-th data line DLj (where i is a positive integer of n or less, j is a positive integer of m or less, and k is a positive integer of o or less). Here, k is a number equal to or less than i. In the example, when each of the emission control lines EL1 to ELo is connected to the pixel PX located in one horizontal line, k may be a number equal to i. In the example, when each of the emission control lines EL1 to ELo is connected to the pixel PX located in at least two horizontal lines, k may be a number less than i.

[0054] When the second enabling scan signal is supplied to the second scan lines SL21 to SL2n, the pixel PX may be selected in units of horizontal lines. The pixel PX selected by the second enabling scan signal may be supplied with a data signal from a data line (any one of the data lines DL1 to DLm) connected thereto. The pixel PX supplied with the data signal may generate light having a predetermined brightness corresponding to a voltage of the data signal.

[0055] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. At least one scan start signal and a clock signal for driving the scan driver 130 may be included in the scan driving signal SCS. The scan driver 130 may generate a first enable scan signal, a second enable scan signal, a third enable scan signal, and a fourth enable scan signal while shifting the scan start signal corresponding to the clock signal.

[0056] For this reason, Figure 2As shown in FIG. 1 , the scan driver 130 may include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138. Depending on the selected design, at least some of the scan drivers 132, 134, 136, and 138 may be integrated into one driving circuit or one module, etc.

[0057] The first scan driver 132 may receive the first scan start signal FLM1 and generate a first enabling scan signal while shifting the first scan start signal FLM1 corresponding to the clock signal The first scan driver 132 may sequentially supply the first enabling scan signal to the first scan lines SL11 to SL1n.

[0058] In an embodiment, the first scan driver 132 may supply the first enable scan signal during the display scan period and the self-scan period of one frame. For example, the first scan driver 132 may perform one scan (e.g., supply at least one first enable scan signal) during the display scan period, and perform at least one scan according to the image refresh rate during the self-scan period. When the image refresh rate decreases (e.g., when the frame length becomes longer), the number of times the operation of supplying the first enable scan signal to each of the first scan lines SL11 to SL1n by the first scan driver 132 is repeated in one frame period may increase.

[0059] The second scan driver 134 may receive the second scan start signal FLM2 and generate a second enable scan signal while shifting the second scan start signal FLM2 in response to the clock signal. The second scan driver 134 may sequentially supply the second enable scan signal to the second scan lines SL21 to SL2n. In an embodiment, the second scan driver 134 may supply the second enable scan signal during a display scan period of one frame.

[0060] The third scan driver 136 may receive the third scan start signal FLM3 and generate a third enable scan signal while shifting the third scan start signal FLM3 in response to the clock signal. The third scan driver 136 may sequentially supply the third enable scan signal to the third scan lines SL31 to SL3n. In an embodiment, the third scan driver 136 may supply the third enable scan signal during a display period of one frame.

[0061] The fourth scan driver 138 may receive the fourth scan start signal FLM4 and generate a fourth enabling scan signal while shifting the fourth scan start signal FLM4 in response to the clock signal. The fourth scan driver 138 may sequentially supply the fourth enabling scan signal to the fourth scan lines SL41 to SL4n. In an embodiment, the fourth scan driver 138 may supply the fourth enabling scan signal during a display period of one frame.

[0062] The first enabling scan signal, the second enabling scan signal, the third enabling scan signal, and the fourth enabling scan signal may be set to a gate-on voltage so that a transistor included in the pixel PX may be turned on.

[0063] In the example, the supply Figure 3 Each of the first enable scan signal GB and the second enable scan signal GW of the P-type transistor shown in FIG. 1 can be set to a low level voltage. Figure 3 Each of the third enabling scan signal GC and the fourth enabling scan signal GI of the N-type transistor shown in can be set to a high level voltage.

[0064] exist Figure 2 , it is shown that the first scan driver 132, the second scan driver 134, the third scan driver 136 and the fourth scan driver 138 are connected to the first scan line SL1, the second scan line SL2, the third scan line SL3 and the fourth scan line SL4, respectively. However, the embodiments of the present disclosure are not limited thereto. For example, in an embodiment, at least two scan lines (e.g., at least two of the scan lines SL1, SL2, SL3 and SL4) among the first scan line SL1, the second scan line SL2, the third scan line SL3 and the fourth scan line SL4 may be driven by one scan driver.

[0065] The data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal for driving the data driver 140. The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. In an example, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 140 may supply the data signal in units of one horizontal period.

[0066] The emission driver 150 may receive an emission driving signal ECS from the timing controller 120. An emission start signal and a clock signal for driving the emission driver 150 may be included in the emission driving signal ECS. The emission driver 150 may generate an emission disable control signal EM while shifting the emission start signal corresponding to the clock signal.

[0067] like Figure 2As shown in , the emission driver 150 may receive the emission start signal EFLM and generate the disable emission control signal EM while shifting the emission start signal EFLM corresponding to the clock signal. The emission driver 150 may sequentially supply the disable emission control signal EM to the emission control lines EL1 to ELo. The disable emission control signal EM may be set to a gate-off voltage so that the transistor included in the pixel PX may be turned off. In an example, the gate-off voltage supplied to the pixel PX may be turned off. Figure 3 The disable emission control signal EM of the P-type transistor shown in can be set to a high level voltage.

[0068] In an embodiment, the emission driver 150 may supply the disabling emission control signal EM during the display scanning period and the self-scanning period of one frame. For example, the emission driver 150 may perform one scan during the display scanning period and perform at least one scan according to the image refresh rate during the self-scanning period. When the image refresh rate is reduced (for example, when the frame length becomes longer), the number of times the operation of supplying the disabling emission control signal EM to each of the emission control lines EL1 to ELo by the emission driver 150 is repeated in one frame period may increase.

[0069] The timing controller 120 may receive input data Din and a control signal CS from a host system via an interface. In an example, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. Various signals including a clock signal may be included in the control signal CS.

[0070] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0071] The timing controller 120 may rearrange the input data Din to fit the specification of the display device 100. In addition, the timing controller 120 may generate output data Dout by correcting the input data Din, and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din corresponding to an optical measurement result measured in a process.

[0072] The power supply 160 may generate various power sources for driving the display device 100. In an example, the power supply 160 may generate a first driving power source VDD, a second driving power source VSS, a first initialization power source Vint1, a second initialization power source Vint2, and a bias power source Vbias.

[0073] The first driving power source VDD may be a power source that supplies a driving current to the pixel PX. The second driving power source VSS may be a power source that is supplied with a driving current from the pixel PX. During a period in which the pixel PX is set to be in an emission state, the first driving power source VDD may be set to a voltage higher than a voltage of the second driving power source VSS.

[0074] The first initialization power source Vint1 may be a power source for initializing the gate electrode of the driving transistor included in each of the pixels PX. The first initialization power source Vint1 may be set to a voltage lower than the voltage of the data signal. The second initialization power source Vint2 may be a power source for initializing the first electrode (or anode electrode) of the light emitting element LD included in each of the pixels PX. The second initialization power source Vint2 may be set to a voltage that turns off the light emitting element LD. The bias power source Vbias may be a power source for applying a conduction bias voltage to the driving transistor included in each of the pixels PX.

[0075] A first driving power source VDD generated by the power supply 160 may be supplied to the first power line PL1, a second driving power source VSS generated by the power supply 160 may be supplied to the second power line PL2, a first initialization power source Vint1 generated by the power supply 160 may be supplied to the third power line PL3, a second initialization power source Vint2 generated by the power supply 160 may be supplied to the fourth power line PL4, and a bias power source Vbias generated by the power supply 160 may be supplied to the fifth power line PL5. The first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, and the fifth power line PL5 may be commonly connected to the pixel PX, but the embodiments of the present disclosure are not limited thereto.

[0076] In an embodiment, the first power line PL1 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the fourth power line PL4 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the fifth power line PL5 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. That is, in an embodiment of the present disclosure, the pixel PX may be connected to any one of the multiple power lines of the first power line PL1, any one of the multiple power lines of the second power line PL2, any one of the multiple power lines of the third power line PL3, any one of the multiple power lines of the fourth power line PL4, and any one of the multiple power lines of the fifth power line PL5.

[0077] In an embodiment of the present disclosure, the display device 100 may include a flat display device, a curved display device in which a portion of the pixel unit 110 is bent, a flexible display device in which a portion of the pixel unit 110 is folded or bent, and a stretchable display device in which a portion of the pixel unit 110 is expanded or contracted.

[0078] In an embodiment of the present disclosure, the display device 100 is a device that displays a moving image or a still image, and may include a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, and an ultra mobile computer (UMPC). In an embodiment of the present disclosure, the display device 100 may include an electronic device such as a television, a notebook computer, a monitor, a billboard, and an Internet of Things (IoT) device.

[0079] Figure 3 is a diagram showing a pixel according to an embodiment of the present disclosure. Figure 3 , pixels located in the i-th horizontal line and the j-th vertical line are shown.

[0080] Reference Figure 3, the pixel PXij according to an embodiment of the present disclosure may be connected to corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELk, and DLj. The signal lines SL1i, SL2i, SL3i, SL4i, ELk, and DLj may include an i-th first scan line SL1i, an i-th second scan line SL2i, an i-th third scan line SL3i, an i-th fourth scan line SL4i, a k-th emission control line ELk, and a j-th data line DLj. For example, the pixel PXij may be connected to an i-th first scan line SL1i (also referred to as the first scan line SL1i), an i-th second scan line SL2i (also referred to as the second scan line SL2i), an i-th third scan line SL3i (third scan line SL3i), an i-th fourth scan line SL4i (fourth scan line SL4i), a k-th emission control line ELk (also referred to as the emission control line ELk), and a j-th data line DLj (also referred to as the data line DLj). In an embodiment, the pixel PXij may also be connected to a first power line PL1 , a second power line PL2 , a third power line PL3 , a fourth power line PL4 , and a fifth power line PL5 .

[0081] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit that controls the amount of current supplied to the light emitting element LD.

[0082] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. In an example, the first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the seventh transistor M7, the third node N3, the first transistor M1, the second node N2, and the sixth transistor M6, and the second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0083] The light emitting element LD may be selected as an organic light emitting diode. In addition, the light emitting element LD may be selected as an inorganic light emitting diode, such as a micro light emitting diode (LED) or a quantum dot light emitting diode. In addition, the light emitting element LD may be an element composed of a combination of an organic material and an inorganic material. Figure 3 , it is shown that the pixel PXij includes a single light emitting element LD. However, the embodiments of the present disclosure are not limited thereto. For example, in an embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected in series, in parallel, or in series / parallel to each other.

[0084] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a storage capacitor Cst.

[0085] A first electrode of the first transistor M1 (or the driving transistor) may be connected to the second node N2, and a second electrode of the first transistor M1 may be connected to the third node N3. In addition, a gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current supplied from the first power line PL1 to the second power line PL2 via the light emitting element LD in response to a voltage of the first node N1.

[0086] The second transistor M2 may be connected between the data line DLj and the second node N2. In addition, the gate electrode of the second transistor M2 may be electrically connected to the second scan line SL2i. When the second enable scan signal GW is supplied to the second scan line SL2i, the second transistor M2 may be turned on to electrically connect the data line DLj and the second node N2 to each other.

[0087] A first electrode of the third transistor M3 may be connected to the first node N1, and a second electrode of the third transistor M3 may be electrically connected to the third power line PL3. In addition, a gate electrode of the third transistor M3 may be electrically connected to the fourth scan line SL4i. When the fourth enable scan signal GI is supplied to the fourth scan line SL4i, the third transistor M3 may be turned on to supply the voltage of the first initialization power source Vint1 to the first node N1.

[0088] The fourth transistor M4 may be connected between the first node N1 and the third node N3. In addition, the gate electrode of the fourth transistor M4 may be electrically connected to the third scan line SL3i. When the third enable scan signal GC is supplied to the third scan line SL3i, the fourth transistor M4 may be turned on to electrically connect the first node N1 and the third node N3 to each other. That is, when the fourth transistor M4 is turned on, the first transistor M1 may be connected in a diode form.

[0089] The first electrode of the fifth transistor M5 may be electrically connected to the first electrode of the light emitting element LD, and the second electrode of the fifth transistor M5 may be electrically connected to the fourth power line PL4. In addition, the gate electrode of the fifth transistor M5 may be electrically connected to the first scan line SL1i. When the first enable scan signal GB is supplied to the first scan line SL1i, the fifth transistor M5 may be turned on to supply the voltage of the second initialization power source Vint2 to the first electrode of the light emitting element LD.

[0090] When the voltage of the second initialization power source Vint2 is supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD can be discharged. As the residual voltage charged in the parasitic capacitor of the light emitting element LD is discharged (or removed), unexpected tiny light emission can be prevented or reduced. Therefore, the black performance capability of the pixel PXij can be improved.

[0091] A first electrode of the sixth transistor M6 may be electrically connected to the first power line PL1, and a second electrode of the sixth transistor M6 may be connected to the second node N2. In addition, a gate electrode of the sixth transistor M6 may be electrically connected to the emission control line ELk. When the disable emission control signal EM is supplied to the emission control line ELk, the sixth transistor M6 may be turned off, and when the enable emission control signal EM is supplied to the emission control line ELk, the sixth transistor M6 may be turned on.

[0092] The seventh transistor M7 may be connected between the third node N3 and the first electrode of the light emitting element LD. In addition, the gate electrode of the seventh transistor M7 may be electrically connected to the emission control line ELk. When the disable emission control signal EM is supplied to the emission control line ELk, the seventh transistor M7 may be turned off, and when the enable emission control signal EM is supplied to the emission control line ELk, the seventh transistor M7 may be turned on.

[0093] A first electrode of the eighth transistor M8 (or the bias transistor) may be electrically connected to the fifth power line PL5, and a second electrode of the eighth transistor M8 may be connected to the second node N2. In addition, a gate electrode of the eighth transistor M8 may be electrically connected to the first scan line SL1i. When the first enable scan signal GB is supplied to the first scan line SL1i, the eighth transistor M8 may be turned on to electrically connect the fifth power line PL5 and the second node N2 to each other.

[0094] The storage capacitor Cst may be connected between the first power line PL1 and the first node N1. The storage capacitor Cst may store a voltage applied to the first node N1.

[0095] In an embodiment, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 can be implemented with polycrystalline silicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 may include a polycrystalline silicon semiconductor layer formed as an active layer (channel) via a low temperature polycrystalline silicon (LTPS) process. In addition, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 may be implemented with a P-type transistor (e.g., a PMOS transistor). Therefore, the gate-on voltage when the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned on can have a logic low level. Since polycrystalline silicon semiconductor transistors provide a high response speed, polycrystalline silicon semiconductor transistors can be applied to switching elements operated with fast switching.

[0096] In an embodiment, the third transistor M3 and the fourth transistor M4 may be formed with oxide semiconductor transistors. For example, the third transistor M3 and the fourth transistor M4 may be implemented with N-type oxide semiconductor transistors (e.g., NMOS transistors) and include an oxide semiconductor layer as an active layer. Therefore, the gate-on voltage when the third transistor M3 and the fourth transistor M4 are turned on may have a logic high level.

[0097] The oxide semiconductor transistor can be formed via a low temperature process and has a charge mobility lower than that of a polysilicon semiconductor transistor. That is, the oxide semiconductor transistor has excellent cut-off current characteristics. Therefore, when the third transistor M3 and the fourth transistor M4 are implemented with oxide semiconductor transistors, the leakage current from the first node N1 according to the low frequency drive can be minimized or reduced, and thus, the display quality can be improved.

[0098] Figure 4 is shown in Figure 2. Figure 3 The display scanning period may be included in the effective area of ​​the frame.

[0099] Reference Figure 3 and Figure 4 The display scanning period DSP may include a first period P1, a second period P2, a third period P3, a fourth period P4 and a fifth period P5. The first period P1 to the fourth period P4 may be set as non-emission periods, and the fifth period P5 may be set as an emission period.

[0100] During the first period P1 to the fourth period P4, the disabling emission control signal EM may be supplied to the emission control line ELk. When the disabling emission control signal EM is supplied to the emission control line ELk, the sixth transistor M6 and the seventh transistor M7 may be turned off. When the sixth transistor M6 and the seventh transistor M7 are turned off, the electrical connection between the first power line PL1 and the light emitting element LD may be blocked, and therefore, the light emitting element LD may be set to be in a non-emission state.

[0101] During the first period P1, the first enabling scan signal GB may be supplied to the first scan line SL1i, and the third enabling scan signal GC may be supplied to the third scan line SL3i. When the third enabling scan signal GC is supplied, the fourth transistor M4 may be turned on, and thus, the first transistor M1 may be connected in a diode form. When the first enabling scan signal GB is supplied, the fifth transistor M5 and the eighth transistor M8 may be turned on.

[0102] When the fifth transistor M5 is turned on, the voltage of the second initialization power source Vint2 can be supplied to the first electrode of the light emitting element LD, and thus, the light emitting element LD can be initialized. When the eighth transistor M8 is turned on, the voltage of the bias power source Vbias can be supplied to the second node N2. Since the fourth transistor M4 is set to be in a conducting state, the voltage of the bias power source Vbias can be supplied to the first node N1 via the second node N2 and the third node N3. The voltage difference between the second node N2 and the third node N3 can be reduced to the threshold voltage level of the first transistor M1. In the example, the first transistor M1 can be set to be in a cut-off bias state.

[0103] During the second period P2, the fourth enabling scan signal GI may be supplied to the fourth scan line SL4i. When the fourth enabling scan signal GI is supplied to the fourth scan line SL4i, the third transistor M3 may be turned on. When the third transistor M3 is turned on, the voltage of the first initialization power source Vint1 of the third power line PL3 may be supplied to the first node N1.

[0104] During the third period P3, the third enabling scan signal GC may be supplied to the third scan line SL3i, and thus, the fourth transistor M4 may be turned on. When the fourth transistor M4 is turned on, the first transistor M1 may be diode-connected.

[0105] In the write period P_W overlapping with the third period P3, the second enable scan signal GW may be supplied to the second scan line SL2i. When the second enable scan signal GW is supplied to the second scan line SL2i, the second transistor M2 may be turned on. When the second transistor M2 is turned on, the data signal from the data line DLj may be supplied to the second node N2. Since the first transistor M1 is maintained in the form of a diode connection by the turned-on fourth transistor M4, the first node N1 may have a voltage obtained by compensating the threshold voltage of the first transistor M1 in the data signal.

[0106] During the fourth period P4, the first enable scan signal GB may be supplied to the first scan line SL1i. When the first enable scan signal GB is supplied to the first scan line SL1i, the fifth transistor M5 and the eighth transistor M8 may be turned on. When the fifth transistor M5 is turned on, the voltage of the second initialization power source Vint2 may be supplied to the first electrode of the light emitting element LD, and thus, the light emitting element LD may be initialized. When the eighth transistor M8 is turned on, the voltage of the bias power source Vbias may be supplied to the second node N2. When the voltage of the bias power source Vbias is supplied to the second node N2, the first transistor M1 may be set to be in a conduction bias state.

[0107] In the fifth period P5, the emission control signal EM (or the low-level emission control signal) can be supplied to the emission control line ELk, so that the sixth transistor M6 and the seventh transistor M7 are turned on. When the sixth transistor M6 and the seventh transistor M7 are turned on, a current flow path from the first power line PL1 to the second power line PL2 via the sixth transistor M6, the first transistor M1, the seventh transistor M7 and the light emitting element LD can be formed. According to the operation of the first transistor M1, a driving current corresponding to the voltage of the first node N1 can flow through the light emitting element LD, and the light emitting element LD can emit light with a brightness corresponding to the driving current.

[0108] Figure 5 is shown driving during the self-scan period Figure 3 The self-scanning period SSP is a period in which light is emitted while maintaining the voltage of the previously supplied data signal, and may be a period in which an image is redisplayed without changing any frame. In an embodiment, one frame may include one display scanning period DSP (see Figure 4 ) and at least one self-scanning period SSP. At least one self-scanning period SSP may be continuously arranged after the display scanning period DSP. The self-scanning period SSP may be included in a blanking area of ​​the frame.

[0109] Compared with the display scanning period DSP, in the self scanning period SSP, the threshold voltage compensation operation and the data writing operation can be omitted, and the first transistor M1 (see Figure 3 ) an operation of applying a bias voltage (and an operation of initializing the light emitting element LD) and a light emitting operation. The self-scanning period SSP may be set to have a length approximately equal to or similar to the length of the display scanning period DSP. The self-scanning period SSP may include a first period P1', a second period P2', a third period P3', a fourth period P4', and a fifth period P5'.

[0110] Reference Figure 3 and Figure 5 , in the first period P1' to the fourth period P4', the disabling emission control signal EM may be supplied to the emission control line ELk. When the disabling emission control signal EM is supplied to the emission control line ELk, the sixth transistor M6 and the seventh transistor M7 may be turned off, and thus, the light emitting element LD may be set to be in a non-emission state.

[0111] In an embodiment, in the first period P1' to the fourth period P4', the second enabling scan signal GW, the third enabling scan signal GC and the fourth enabling scan signal GI are not supplied (or the disabling scan signals GW, GC and GI are supplied). Therefore, in the first period P1' to the fourth period P4', the second transistor M2, the third transistor M3 and the fourth transistor M4 can be set to be in a cut-off state.

[0112] In the first to fourth periods P1' to P4', the first enabling scan signal GB may be supplied to the first scan line SL1i. When the first enabling scan signal GB is supplied to the first scan line SL1i, the fifth transistor M5 and the eighth transistor M8 may be turned on.

[0113] When the fifth transistor M5 is turned on, the voltage of the second initialization power source Vint2 can be supplied to the first electrode of the light emitting element LD, and thus, the light emitting element LD can be initialized. When the eighth transistor M8 is turned on, the voltage of the bias power source Vbias can be supplied to the second node N2. When the voltage of the bias power source Vbias is supplied to the second node N2, the first transistor M1 can be set to be in a conduction bias state.

[0114] Since one frame includes a display scanning period DSP and a self-scanning period SSP, the display device 100 (see Figure 1 ) can be driven at various driving frequencies (various frame frequencies).

[0115] Figure 6is a diagram illustrating an embodiment of an emission control signal and a first scan signal (also referred to as a first enable scan signal) supplied in an active region and a blanking region.

[0116] Reference Figure 6 During the effective area (e.g., display scanning period), the emission disable control signal EM may be supplied once, and the first enable scanning signal GB may be supplied twice. In addition, during the blanking area (e.g., self-scanning period), the emission disable control signal EM may be supplied three times, and the first enable scanning signal GB may be supplied once.

[0117] When it is assumed that the first enable scan signal GB supplied in the effective area constitutes one cycle period, during one frame period, the first enable scan signal GB can be supplied for two cycles, and the disable emission control signal EM can be supplied for four cycles. In the example, regardless of the image refresh rate, the disable emission control signal EM can be supplied at a frequency of about 480 Hz, and the first enable scan signal GB can be supplied at a frequency of about 240 Hz. As the length of the blanking area becomes longer (for example, the image refresh rate becomes lower), the number of times the disable emission control signal EM and the first enable scan signal GB are supplied can increase.

[0118] exist Figure 6 In the embodiment, the supply of the disable emission control signal EM and the first enable scan signal GB is merely illustrative, and the embodiments of the present disclosure are not limited thereto. In an example, the disable emission control signal EM and the first enable scan signal GB may be supplied to have the same cycle period during one frame period.

[0119] Displayed on the display device 100 (see Figure 1 ) will maintain similar brightness regardless of the imager refresh rate. However, as shown in Table 1, brightness differences may occur corresponding to changes in image refresh rate.

[0120] Table 1

[0121] sample 10Hz 1Hz #1 0.28％ 5.18％ #2 0.31％ 3.26％ #3 0.31％ 6.56％ #4 0.11％ 6.45％ #5 0.06％ 1.75％ #6 0.55％ 0.55％ #7 0.29％ 0.92％ #8 0.22％ 0.89％ #9 0.11％ 1.49％ #10 0.34％ 0.00％

[0122] In Table 1, #1 to #10 represent different display panels. In Table 1, 10Hz and 1Hz represent that each display panel is driven at an image refresh rate of about 10Hz and about 1Hz. In Table 1, each portion indicated by a percentage (%) represents a brightness difference obtained by comparing with when each display panel is driven at an image refresh rate of about 120Hz. Referring to Table 1, when each display panel (or display device 100) is driven at about 10Hz, the display panel has a brightness difference of about 0.28%, about 0.31%, about 0.31%, about 0.11%, about 0.06%, about 0.55%, about 0.29%, about 0.22%, about 0.11%, and about 0.34% compared to when the display panel is driven at about 120Hz. That is, when the display panel is driven at about 10Hz, the display panel has a brightness difference of about 0.5% or less compared to when the display panel is driven at about 120Hz. The brightness difference caused by the change in image refresh rate may not be recognized by the user, and thus, high display quality may be maintained.

[0123] On the other hand, when each display panel is driven at about 1 Hz, the display panel has a brightness difference of about 5.18%, about 3.26%, about 6.56%, about 6.45%, about 1.75%, about 0.55%, about 1.92%, about 0.89%, about 1.49%, and about 0.00% compared to when the display panel is driven at about 120 Hz. That is, when the display panel is driven at about 1 Hz, a brightness difference of about 3% or more occurs in some display panels compared to when the display panel is driven at about 120 Hz. The brightness difference caused by the change in image refresh rate (e.g., a change from about 120 Hz to about 1 Hz) may be recognized by the user, and therefore, the display quality may be deteriorated.

[0124] In the embodiments of the present disclosure, Figure 2 The scan driver 130 (or the first scan driver 132) shown in the figure can change the width of the first enable scan signal GB supplied in the blanking area (or supplied in the self-scanning period) corresponding to the image refresh rate, so that the brightness difference caused by the change of the image refresh rate is minimized or reduced. In the example, when the width of the first enable scan signal GB is controlled corresponding to the image refresh rate of about 1 Hz, the brightness difference caused by the change of the image refresh rate can be minimized.

[0125] The scan driver 130 (or the first scan driver 132 ) may supply the first enable scan signal GB having a certain width regardless of an image refresh rate during an active region.

[0126] Figure 71 is a diagram showing a method of tuning a display device. Multiple-time programming (MTP) can be performed for each display device 100 (see Figure 1 )set up Figure 7 Tuning shown in .

[0127] Reference Figure 7 , first, the voltage of the second driving power source VSS of the display device 100 may be set (operation S702). After the voltage of the second driving power source VSS is set in operation S702, the voltage Vblack of the black data signal may be set (operation S704). The voltage Vblack of the black data signal may be set for each display device 100 by considering the channel dispersion of the display device 100. After the voltage Vblack of the black data signal is set in operation S704, the brightness of the display device 100 may be set (or tuned) (operation S706). In an example, in operation S706, a gamma voltage corresponding to the data signal may be set.

[0128] After setting the brightness of the display device 100 in operation S706, the width of the first enabling scan signal GB corresponding to about 1 Hz may be set (operation S708). In an example, in operation S708, when the display device 100 is driven at about 1 Hz, the width of the first enabling scan signal GB supplied in the blanking area (or self-scanning period) may be set. In operation S708, the width of the first enabling scan signal GB corresponding to about 1 Hz may be set so that the brightness difference is minimized or reduced corresponding to the change in the image refresh rate. The width of the first enabling scan signal GB set in operation S708 may be stored in an integrated circuit (IC) (operation S710). The IC may include Figure 1 The timing controller 120 shown in FIG.

[0129] After the width of the first enable scan signal GB is stored in the IC, the voltage of the display device 100 may be set (operation S712). In an example, the voltage of each of the first initialization power source Vint1, the second initialization power source Vint2, and the bias power source Vbias may be set in operation S712 (see Figure 3 ).

[0130] Figure 8 It is shown Figure 7 An embodiment of operation S708 is shown in FIG.

[0131] Reference Figure 8First, the width of the standard first enabling scan signal GB may be loaded (operation S7081). The width of the standard first enabling scan signal GB may be predetermined. In an example, the width of the standard first enabling scan signal GB may have a settable minimum width (eg, length or area, etc.).

[0132] After the width of the standard first enabling scan signal GB is loaded in operation S7081, the width of the first enabling scan signal GB may be changed (operation S7082). In an example, in operation S7082, the width of the first enabling scan signal GB may be changed to a width wider than that of the standard first enabling scan signal GB.

[0133] After the width of the first enable scan signal GB is changed, it is possible to measure when the display device 100 (see Figure 1 ) is driven at about 120 Hz and the brightness of the display device 100 when the display device 100 is driven at about 1 Hz (operations S7083 and S7084). Then, it may be determined whether the brightness (or brightness difference) of the display device 100 between the brightness when the display device 100 is driven at about 120 Hz and the brightness when the display device 100 is driven at about 1 Hz is a threshold value or less (operation S7085).

[0134] In operation S7085, a threshold value may be predetermined. In an example, the threshold value may be set to about 1% or less. When the brightness difference is equal to or less than the threshold value in operation S7085, the width of the change of the first enable scan signal GB may be confirmed (operation S7086). Figure 7 As shown, the width of the first enabling scan signal GB confirmed in operation S7086 may be stored in the IC. When the brightness difference exceeds the threshold value in operation S7085, the width of the first enabling scan signal GB may be controlled while repeating operations S7082 to S7085.

[0135] Fig. 9 and Fig.10 is a diagram showing an embodiment of a first scanning signal supplied in a blanking area corresponding to an image refresh rate. Fig. 9 and 10 In the display, "data" indicated in the active area (or display scanning period) can indicate that a data signal is supplied. The active area can have the same period regardless of the image refresh rate. Fig. 9 and Fig.10 , it is shown that when the display device 100 is driven at about 120 Hz (see Figure 1 ), no blanking area is included. However, the embodiments of the present disclosure are not limited thereto.

[0136] Reference Fig. 9, when the display device 100 is driven at an image refresh rate of about 10 Hz (or the first image refresh rate) (or when the display device 100 is driven at an image refresh rate of about 10 Hz or higher), Figure 2 The scan driver 130 (or the first scan driver 132) shown in the figure can supply the first enable scan signal GB having the first width W1 during the blanking area (or the self-scanning period). In addition, when the display device 100 is driven at an image refresh rate (or the second image refresh rate) of about 1 Hz, the scan driver 130 can supply the first enable scan signal GB having the first width W1 and the first enable scan signal GB having the second width W2 during the blanking area. The second width W2 can be set to a width different from the width of the first width W1. Fig. 9 and 10 , it is shown that the second width W2 is wider than the first width W1. However, the embodiments of the present disclosure are not limited thereto. For example, in an embodiment, the second width W2 may be set to a width narrower than the first width W1.

[0137] When the display device 100 is driven at an image refresh rate of about 1 Hz, the blanking area may include a first period P11 and a second period P12. The first period P11 may be a period having the same time as the blanking area of ​​the image refresh rate of about 10 Hz. During the first period P11, the scan driver 130 may supply a first enable scan signal GB having a first width W1. The second period P12 may be a period after the first period P11. During the second period P12, the scan driver 130 may supply a first enable scan signal GB having a second width W2.

[0138] When the display device 100 is driven at an image refresh rate of about 1 Hz, the first enable scan signal GB having the second width W2 may be set such that a brightness difference is minimized or reduced compared to another image refresh rate (eg, an image refresh rate of about 10 Hz or higher).

[0139] like Fig.10 As shown in , at least one first enabling scan signal GB having a first width W1 may be supplied during the second period P12a. In an example, at least one first enabling scan signal GB having a first width W1 may be supplied at a boundary portion between the first period P11 and the second period P12a.

[0140] Table 2 below shows the brightness difference corresponding to changes in image refresh rate.

[0141] Table 2

[0142]

[0143] In Table 2, #1 to #10 represent different display panels. In Table 2, 10 Hz and 1 Hz represent that each display panel is driven at an image refresh rate of approximately 10 Hz and approximately 1 Hz. In Table 2, each portion indicated by a percentage (%) represents a brightness difference obtained by comparing with when each display panel is driven at an image refresh rate of approximately 120 Hz. In Table 2, a horizontal period (H) located to the left of 10 Hz represents a supply period of a first enable scan signal GB having a first width W1, which is supplied when the display device 10 is driven at an image refresh rate of approximately 10 Hz or higher. In Table 2, a horizontal period (H) located to the left of 1 Hz represents a supply period of a first enable scan signal GB having a second width W2, which is supplied when the display device 10 is driven at an image refresh rate of approximately 1 Hz.

[0144] Referring to Table 2, in an embodiment of the present disclosure, when each display panel (or display device 100) is driven at about 1 Hz, the display panel has a brightness difference of about 0.88%, about 0.48%, about 0.66%, about 0.00%, about 0.51%, about 0.47%, about 0.11%, about 0.22%, about 0.39%, and about 0.00%, compared to when the display panel is driven at about 120 Hz. That is, in an embodiment of the present disclosure, although the display panel is driven at an image refresh rate of about 1 Hz, the display panel has a brightness difference of about 1% or less compared to an image refresh rate of about 120 Hz, and therefore, the brightness difference caused by the change in the image refresh rate can be prevented from being recognized by the user.

[0145] Fig.11 It is shown Figure 1 An embodiment of a timing controller is shown in FIG. Fig.12 It is shown Fig.11 A diagram of an embodiment of a start signal provider is shown in FIG. Fig.11 In the figure, some components may be omitted for ease of explanation.

[0146] Reference Fig.11 , the timing controller 120 according to an embodiment of the present disclosure may include a frequency determiner 122, a start signal supplier 124, and an oscillator 126. The frequency determiner 122 may also be referred to as a frequency determiner circuit, the start signal supplier 124 may also be referred to as a start signal supplier circuit, and the oscillator 126 may also be referred to as an oscillator circuit.

[0147] The oscillator 126 may generate a predetermined clock signal CLK. The oscillator 126 may be an internal oscillator of the timing controller 120 .

[0148] The frequency determiner 122 may determine the image refresh rate. In an example, the frequency determiner 122 may determine the image refresh rate corresponding to a control signal supplied from an external host. In an example, the frequency determiner 122 may determine the image refresh rate by counting the clock signal CLK. In addition, the frequency determiner 122 may determine the length of the blanking region by counting the clock signal CLK. In an example, the frequency determiner 122 may determine the image refresh rate by counting the clock signal CLK. Fig. 9 The first period P11 and the second period P12 are shown in FIG.

[0149] The frequency determiner 122 that determines the length of the blanking region may supply a width control signal WCS corresponding to the length of the blanking region to the start signal supplier 124. The start signal supplier 124 supplied with the width control signal WCS may supply Figure 2 The scan driver 130 (or the first scan driver 132 ) shown in FIG. 1 supplies a start signal FLM11 or FLM12 .

[0150] In an embodiment, when the length of the blanking region is included in Fig. 9 In the first period P11 shown in FIG. 1 , the start signal supplier 124 may supply the first start signal FLM11. The first start signal FLM11 may correspond to the first width W1. In an embodiment, when the length of the blanking area is included in Fig. 9 In the second period P12 shown in FIG. 1 , the start signal supplier 124 may supply the second start signal FLM12. The second start signal FLM12 may correspond to the second width W2.

[0151] For this reason, Fig.12 As shown in FIG. 1 , the start signal supplier 124 may include a first start signal supplier 1241 and a second start signal supplier 1242. The first start signal supplier 1241 may supply the first start signal FLM11 to the scan driver 130 corresponding to the width control signal WCS. The second start signal supplier 1242 may supply the second start signal FLM12 to the scan driver 130 corresponding to the width control signal WCS.

[0152] Fig.13 is a diagram showing an embodiment of a first scanning signal supplied in a blanking area corresponding to an image refresh rate. Fig.13 In the display, "data" indicated in the active area (or display scanning period) can indicate that a data signal is supplied. The active area can have the same period regardless of the image refresh rate. Fig.13 , it is shown that when the display device 100 is driven at about 120 Hz (see Figure 1 ), no blanking area is included. However, the embodiments of the present disclosure are not limited thereto.

[0153] Reference Fig.13 When the display device 100 is driven at an image refresh rate of about 80 Hz, the scan driver 130 (see Figure 2 ) may supply a first scan signal GB having a first width W11 during the blanking area.

[0154] In an embodiment, when the display device 100 is driven at an image refresh rate of about 60 Hz, the scan driver 130 may supply a first scan signal GB having a first width W11 and a first scan signal GB having a second width W12 during a blanking region. In an example, the scan driver 130 may supply a first scan signal GB having a first width W11 during a first period P21 of the blanking region, and supply a first scan signal GB having a second width W12 during a second period P22 of the blanking region. The second width W12 may be set to a width different from that of the first width W11. The first period P21 may be a period having the same time as a blanking region of an image refresh rate of about 80 Hz. The second period P22 may be a period after the first period P21.

[0155] In an embodiment, when the display device 100 is driven at an image refresh rate of about 24 Hz, the scan driver 130 may supply a first scan signal GB having a first width W11, a first scan signal GB having a second width W12, and a first scan signal GB having a third width W13 during a blanking region. In an example, the scan driver 130 may supply a first scan signal GB having a first width W11 during a first period P21 of the blanking region, a first scan signal GB having a second width W12 during a second period P22 of the blanking region, and a first scan signal GB having a third width W13 during a third period P23 of the blanking region. The first period P21 and the second period P22 may correspond to a period having the same time as a blanking region of an image refresh rate of about 60 Hz. The third period P23 may be a period after the second period P22. In addition, the third width W13 may be set to a width different from the first width W11 and the second width W12.

[0156] In an embodiment, when the display device 100 is driven at an image refresh rate of about 10 Hz, the scan driver 130 may supply a first scan signal GB having a first width W11, a first scan signal GB having a second width W12, a first scan signal GB having a third width W13, and a first scan signal GB having a fourth width W14 during a blanking region. In an example, the scan driver 130 may supply a first scan signal GB having a first width W11 during a first period P21 of the blanking region, a first scan signal GB having a second width W12 during a second period P22 of the blanking region, a first scan signal GB having a third width W13 during a third period P23 of the blanking region, and a first scan signal GB having a fourth width W14 during a fourth period P24 of the blanking region. The first period P21 to the third period P23 may correspond to a period having the same time as the blanking region of an image refresh rate of about 24 Hz. The fourth period P24 may be a period after the third period P23. In addition, the fourth width W14 may be set to a width different from the first width W11 , the second width W12 , and the third width W13 .

[0157] In an embodiment, when the display device 100 is driven at an image refresh rate of about 1 Hz, the scan driver 130 may supply a first scan signal GB having a first width W11, a first scan signal GB having a second width W12, a first scan signal GB having a third width W13, a first scan signal GB having a fourth width W14, and a first scan signal GB having a fifth width W15 during the blanking region. In an example, the scan driver 130 may supply the first scan signal GB having the first width W11 during a first period P21 of the blanking region, the first scan signal GB having the second width W12 during a second period P22 of the blanking region, the first scan signal GB having the third width W13 during a third period P23 of the blanking region, the first scan signal GB having the fourth width W14 during a fourth period P24 of the blanking region, and the first scan signal GB having the fifth width W15 during a fifth period P25 of the blanking region. The first period P21 to the fourth period P24 may correspond to periods having the same time as the blanking region of the image refresh rate of about 10 Hz. The fifth period P25 may be a period after the fourth period P24. In addition, the fifth width W15 may be set to a width different from the first width W11, the second width W12, the third width W13, and the fourth width W14.

[0158] In this disclosure Fig.13In the embodiment shown in , the first scanning signal GB having different widths is supplied corresponding to the image refresh rate (eg, the length of the blanking area), and thus, when the image refresh rate changes, the brightness difference can be minimized or reduced.

[0159] In the display device and the method of driving the display device according to the embodiment of the present disclosure, the width of the scan signal is changed corresponding to the image refresh rate, and thus, the display quality can be improved.

[0160] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display device, wherein: The display device comprises: at least one pixel configured to receive a voltage of an initialization power source supplied to an anode electrode of a light emitting element of the at least one pixel when an enable scan signal is supplied to the scan line; and a scan driver configured to supply the enable scan signal to the scan line, wherein the enable scan signal supplied by the scan driver to the scan line has the same width during an effective region of a frame regardless of an image refresh rate, and During a blanking region of the frame, the width of the enable scan signal supplied to the scan line is changed by the scan driver corresponding to the image refresh rate.

2. The display device according to claim 1, wherein: The at least one pixel includes a driving transistor configured to control an amount of current supplied to the light emitting element, and When the enable scan signal is supplied, a bias voltage is supplied to the driving transistor.

3. The display device according to claim 1, wherein: When the display device is driven at a first image refresh rate, the enable scan signal supplied by the scan driver has a first width in the blanking area of ​​the frame, and when the display device is driven at a second image refresh rate lower than the first image refresh rate, the enable scan signal supplied by the scan driver has the first width and the second width in the blanking area of ​​the frame.

4. The display device according to claim 3, wherein: The first image refresh rate is a driving frequency of 10 Hz or higher, and the second image refresh rate is a driving frequency of 1 Hz.

5. The display device according to claim 3, wherein: The second width is different from the first width.

6. The display device according to claim 3, wherein: When the display device is driven at the second image refresh rate, the blanking region of the frame includes a first period and a second period, and The scan driver supplies the enable scan signal having the first width during the first period, and supplies the enable scan signal having the second width during the second period.

7. The display device according to claim 6, wherein: The first cycle is a cycle having the same time as the blanking area of ​​the frame of the first image refresh rate, and the second cycle is a cycle after the first cycle.

8. The display device according to claim 6, wherein: The enable scan signal supplied by the scan driver has the first width and then has the second width during the second period.

9. The display device according to claim 1, wherein: When the display device is driven at a first image refresh rate, the enable scan signal supplied by the scan driver has a first width in the blanking area of ​​the frame; When the display device is driven at a second image refresh rate lower than the first image refresh rate, the enable scan signal supplied by the scan driver has the first width and the second width in the blanking area of ​​the frame; and When the display device is driven at a third image refresh rate lower than the second image refresh rate, the enable scan signal supplied by the scan driver has the first width, the second width, and a third width in the blanking area of ​​the frame.

10. The display device according to claim 9, wherein: The first width, the second width, and the third width are different widths.

11. The display device according to claim 9, wherein: The blanking area of ​​the frame of the second image refresh rate includes a first period and a second period, and The scan driver supplies the enable scan signal having the first width during the first period, and supplies the enable scan signal having the second width during the second period.

12. The display device according to claim 11, wherein: The first cycle is a cycle having the same time as the blanking area of ​​the frame of the first image refresh rate, and the second cycle is a cycle after the first cycle.

13. The display device according to claim 9, wherein: The blanking area of ​​the frame of the third image refresh rate includes a first period, a second period and a third period, and The scan driver supplies the enable scan signal having the first width during the first period, supplies the enable scan signal having the second width during the second period, and supplies the enable scan signal having the third width during the third period.

14. The display device according to claim 13, wherein: The first cycle and the second cycle correspond to a cycle having the same time as the blanking area of ​​the frame of the second image refresh rate, and the third cycle is a cycle after the second cycle.

15. The display device according to claim 1, wherein: The display device further includes: A timing controller configured to control the scan driver, Wherein, the timing controller comprises: an oscillator configured to generate a clock signal; a frequency determiner configured to determine the image refresh rate using the clock signal, and determine a length of the blanking region of the frame included in the image refresh rate; and A start signal supplier is configured to supply a start signal corresponding to the image refresh rate determined by the frequency determiner and the length of the blanking area of ​​the frame to the scan driver.

16. The display device according to claim 15, wherein: The start signal supplier supplies the start signal so that the width of the enable scan signal changes corresponding to the blanking area of ​​the frame.

Images