Display device

Abstract

A display device includes a display panel, a scan driver, and a timing controller. The display panel includes pixels connected to scan lines and initialization lines. The scan driver includes a first stage configured to supply an enable scan signal to the scan line during an active period of one frame and a second stage configured to supply an enable initialization signal to the initialization line during the active period and a blank period of the one frame. The timing controller is configured to supply a scan clock signal and an initialization clock signal to the scan driver. When an enable initialization signal is supplied to two of the initialization lines in an overlapping manner during an active period of a current frame, enable scan signals having different widths are supplied to corresponding areas of the display panel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Korean Patent Application No. 10-2023-0136665, filed on October 13, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a method of driving the display device. Background Art

[0004] The display device serves as a connection medium between a user and information. Examples of the display device include a liquid crystal display device and an organic light emitting display device.

[0005] Such a display device can display images with various contents. For example, the display device can display various types of images such as still images, web pages, and images of movies or electronic games. In the case of displaying still images on the display device, frequent frame conversion is not required. On the other hand, in the case of displaying images of movies or electronic games on the display device, frequent frame conversion is required.

[0006] However, when frequent frame switching is required, a large amount of power may be consumed. In addition, the display device may need to be refreshed using various refresh rates. However, due to the use of these different refresh rates, visibility may be reduced. Summary of the invention

[0007] At least one embodiment of the present disclosure relates to a display device and a method of driving the display device to display images at various refresh rates so that visibility can be improved.

[0008] An embodiment of the present disclosure provides a display device, which includes: a display panel; a scan driver; and a timing controller. The display panel includes pixels connected to a scan line and an initialization line. The scan driver includes a first stage configured to supply an enable scan signal to the scan line during an effective period of a frame and a second stage configured to supply an enable initialization signal to the initialization line during an effective period and a blank period of a frame. The timing controller is configured to supply a scan clock signal and an initialization clock signal to the scan driver. When the enable initialization signal is supplied to two of the initialization lines in an overlapping manner during the effective period of the current frame, enable scan signals with different widths are supplied to corresponding areas of the display panel.

[0009] In an embodiment, in the effective period of the current frame, the area of ​​the display panel may include: a first area where pixels to which an enable initialization signal is supplied during the blank period of the previous frame are located; a second area where pixels to which an enable initialization signal corresponding to the blank period of the previous frame is supplied are located; and a third area other than the first area and the second area.

[0010] In an embodiment, during the effective period of the current frame, the scan driver may supply an enable scan signal having a first width to a scan line located in the first area, may supply an enable scan signal having a second width different from the first width to a scan line located in the second area, and may supply an enable scan signal having a third width different from the first width and the second width to a scan line located in the third area.

[0011] In an embodiment, the first width may be greater than the second width, and the second width may be greater than the third width.

[0012] In an embodiment, the timing controller may include: a driver configured to receive a first data enable signal and operate in response to the first data enable signal; a first logic circuit configured to determine the length of a blank period using the first data enable signal; a second logic circuit configured to determine a first region and a second region based on the length of the blank period determined by the first logic circuit; a scan clock generator configured to receive a second data enable signal output from the driver and generate scan clock signals corresponding to the first region, the second region, and the third region, respectively; and an output circuit configured to output the scan clock signal.

[0013] In an embodiment, the second data enable signal may be the first data enable signal delayed by a preset time.

[0014] In an embodiment, the second logic circuit may include: a third logic circuit configured to determine the first area based on the length of the blank period determined by the first logic circuit; and a fourth logic circuit configured to determine the second area based on the length of the blank period determined by the first logic circuit.

[0015] In an embodiment, the scan clock generator may include: a first lookup table configured to store duty cycle information corresponding to the number of scan lines included in the first area; a first scan clock generator connected to the first lookup table and configured to generate a first clock signal, the first clock signal having a conduction segment with a first width corresponding to the number of scan lines included in the first area; a second lookup table configured to store duty cycle information corresponding to the number of scan lines included in the second area; a second scan clock generator connected to the second lookup table and configured to generate a second clock signal, the second clock signal having a conduction segment with a second width corresponding to the number of scan lines included in the second area; and a third scan clock generator configured to generate a third clock signal having a conduction segment with a third width.

[0016] In an embodiment, the first lookup table may store duty cycle information having a first width having different values ​​corresponding to the number of scan lines included in the first area. The second lookup table may store duty cycle information having a second width having different values ​​corresponding to the number of scan lines included in the second area.

[0017] In an embodiment, the output circuit can supply the first clock signal as a scan clock signal to the first stage connected to the scan line located in the first area, can supply the second clock signal as a scan clock signal to the first stage connected to the scan line located in the second area, and can supply the third clock signal as a scan clock signal to the first stage connected to the scan line located in the third area.

[0018] In an embodiment, during the effective period of the current frame, when the enable initialization signal corresponding to the blank period of the previous frame is not supplied, the scan driver may supply the enable scan signal having the same width to the scan lines.

[0019] In an embodiment, the scan driver may supply enable initialization signals having different widths to corresponding regions of the display panel.

[0020] An embodiment of the present disclosure provides a display device, which includes: a display panel; a scan driver; and a timing controller. The display panel includes pixels connected to a scan line and an initialization line. The scan driver includes a first stage configured to supply an enable scan signal to the scan line during an effective period of a frame and a second stage configured to supply an enable initialization signal to the initialization line during an effective period and a blank period of a frame. The timing controller is configured to supply a scan clock signal and an initialization clock signal to the scan driver. When the enable initialization signal is supplied to two of the initialization lines in an overlapping manner during the effective period of the current frame, enable initialization signals with different widths are supplied to corresponding areas of the display panel.

[0021] In an embodiment, in the effective period of the current frame, the area of ​​the display panel may include: a first area where pixels to which an enable initialization signal is supplied during the blank period of the previous frame are located; a second area where pixels to which an enable initialization signal corresponding to the blank period of the previous frame is supplied are located; and a third area other than the first area and the second area.

[0022] In an embodiment, during the effective period of the current frame, the scan driver may supply an enable initialization signal having a first width to the initialization line located in the first area, may supply an enable initialization signal having a second width different from the first width to the initialization line located in the second area, and may supply an enable initialization signal having a third width different from the first width and the second width to the initialization line located in the third area.

[0023] In an embodiment, the first width may be smaller than the second width, and the second width may be smaller than the third width.

[0024] In an embodiment, the timing controller may include: a driver configured to receive a first data enable signal and operate based on the first data enable signal; a first logic circuit configured to determine the length of a blank period using the first data enable signal; a second logic circuit configured to determine a first region and a second region based on the length of the blank period determined by the first logic circuit; an initialization clock generator configured to receive a second data enable signal output from the driver and generate initialization clock signals corresponding to the first region, the second region, and the third region, respectively; and an output circuit configured to output the initialization clock signal.

[0025] In an embodiment, the initialization clock generator may include: a first lookup table configured to store duty cycle information corresponding to the number of initialization lines included in the first region; a first initialization clock generator connected to the first lookup table and configured to generate a first clock signal, the first clock signal having a conduction segment with a first width corresponding to the number of initialization lines included in the first region; a second lookup table configured to store duty cycle information corresponding to the number of initialization lines included in the second region; a second initialization clock generator connected to the second lookup table and configured to generate a second clock signal, the second clock signal having a conduction segment with a second width corresponding to the number of initialization lines included in the second region; and a third initialization clock generator configured to generate a third clock signal having a conduction segment with a third width.

[0026] In an embodiment, the output circuit may supply the first clock signal as an initialization clock signal to the second stage connected to the initialization line located in the first region, may supply the second clock signal as an initialization clock signal to the second stage connected to the initialization line located in the second region, and may supply the third clock signal as an initialization clock signal to the second stage connected to the initialization line located in the third region.

[0027] An embodiment of the present disclosure provides a display device, comprising: a display panel; and a scan driver. The display panel includes pixels connected to first to n-th scan lines (where n is a natural number greater than 0) and first to n-th initialization lines. The scan driver is configured to supply an enable scan signal to the scan line and an enable initialization signal to the initialization line during a first mode, and to supply an enable initialization signal to the initialization line during a second mode. When the period in which the i-th pixel row (where i is a natural number greater than 0) of the display panel operates in the first mode overlaps with the period in which the i+a-th pixel row (where a is a natural number greater than 0) of the display panel operates in the second mode, a scan signal having a first width may be supplied to the i-th scan line in the scan line, and a scan signal having a second width different from the first width may be supplied to the i+a-th scan line in the scan line.

[0028] In an embodiment, a scan signal having a third width different from the first width and the second width is supplied to the i+a+bth scan line located on the i+a+bth pixel row (where b is a natural number greater than 0) among the scan lines operating only in the first mode.

[0029] In an embodiment, the first width is greater than the second width, and the second width is greater than the third width.

[0030] In an embodiment, an initialization signal having a fourth width is supplied to an i-th initialization line among the initialization lines, and an initialization signal having a fifth width different from the fourth width is supplied to an i+a-th initialization line among the initialization lines.

[0031] In an embodiment, an initialization signal having a sixth width different from the fourth width and the fifth width may be supplied to the i+a+bth initialization line located on the i+a+bth pixel row (where b is a natural number greater than 0) among the initialization lines operating only in the first mode.

[0032] In an embodiment, the fourth width may be smaller than the fifth width, and the fifth width may be smaller than the sixth width.

[0033] Embodiments of the present disclosure may provide a method for driving a display device including a pixel, the pixel being included in a display panel and connected to a scan line and an initialization line. The method may include supplying an enable scan signal to the scan line during an effective period of a frame, and supplying an enable initialization signal to the initialization line during an effective period and a blank period of a frame. When an enable initialization signal corresponding to a blank period of a previous frame is supplied during an effective period of a current frame, an enable scan signal having a different width is supplied to a corresponding area of ​​the display panel.

[0034] In an embodiment, the areas of the display panel may include: a first area where pixels to which an enable initialization signal is supplied during a blank period of a previous frame are located; a second area where pixels to which an enable initialization signal corresponding to the blank period of the previous frame is supplied are located; and a third area other than the first area and the second area.

[0035] In an embodiment, the method may further include: supplying an enable scan signal having a first width to a scan line located in the first area; supplying an enable scan signal having a second width different from the first width to a scan line located in the second area; and supplying an enable scan signal having a third width different from the first width and the second width to a scan line located in the third area.

[0036] In an embodiment, the first width may be greater than the second width, and the second width may be greater than the third width.

[0037] In an embodiment, the enable initialization signal may have different widths for respective areas of the display panel corresponding to the effective period of the current frame.

[0038] In an embodiment, the method may further include: supplying an enable initialization signal having a first width to an initialization line located in the first region; supplying an enable initialization signal having a second width different from the first width to an initialization line located in the second region; and supplying an enable initialization signal having a third width different from the first width and the second width to an initialization line located in the third region.

[0039] In an embodiment, the first width may be smaller than the second width, and the second width may be smaller than the third width. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0041] Figure 2 It is a graphic Figure 1 A circuit diagram of an embodiment of a pixel is shown in FIG.

[0042] Figure 3It is a graphic driver Figure 2 A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0043] Figure 4 is a diagram illustrating an example of a blank period corresponding to a refresh rate.

[0044] Figure 5A and Figure 5B is a diagram illustrating an embodiment of an initialization period included in one frame period corresponding to a refresh rate.

[0045] Figure 6 is a diagram illustrating an example of a driving waveform supplied during an effective period of one frame.

[0046] Figure 7 is a diagram illustrating an example of a driving waveform supplied during an initialization period of one frame.

[0047] Figure 8 is a diagram illustrating stages included in a scan driver according to a comparative example.

[0048] Fig. 9 The diagram is provided by Figure 8 Graph of the drive waveform supplied by the stage illustrated in FIG.

[0049] Fig.10 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0050] Fig.11 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0051] Fig.12 The diagram is provided by Fig.10 and Fig.11 Graph of the drive waveform supplied by the stage illustrated in FIG.

[0052] Fig.13A and Fig. 13B It is a detailed diagram Fig.12 FIG. 1 is a diagram of the period between the second frame and the third frame shown in FIG.

[0053] Fig.14 It is a graphic Fig.12 FIG. 1 is a diagram of the period between the second frame and the third frame shown in FIG.

[0054] Fig.15 It is a graphic with Fig.13A The image of the third frame and Fig.14 A graph of the brightness of the pixel components corresponding to the image of the second frame.

[0055] Fig.16 It is a graphic Figure 1 An embodiment of a timing controller is shown in FIG.

[0056] Fig.17 and Fig.18 is a diagram illustrating a process of supplying a scan signal according to an embodiment of the present disclosure.

[0057] Fig.19 It is a graphic Figure 1 An embodiment of a timing controller is shown in FIG.

[0058] Fig. 20 and Fig.21 is a diagram illustrating a process of supplying an initialization signal according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can implement the present invention. The present disclosure may be implemented in various forms and is not limited to the embodiments to be described herein below.

[0060] Reference should be made to the accompanying drawings, in which like reference numerals are used throughout the different drawings to denote like components. Therefore, the aforementioned reference numerals may be used in other drawings.

[0061] In addition, the expression "same" may mean "substantially the same." In other words, the expression "same" may include a range that can be tolerated by those skilled in the art. Other expressions may also be expressions from which the term "substantially" is omitted.

[0062] Some embodiments are described in conjunction with functional blocks, units and / or modules in the accompanying drawings. It will be appreciated by those skilled in the art that such blocks, units and / or modules can be physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. These can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. For blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software to perform various functions discussed herein, and can be optionally driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or by a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform different functions. In addition, in some embodiments, blocks, units and / or modules can be physically divided into two or more separate blocks, units and / or modules that interact with each other, without departing from the scope of the inventive concept. In some embodiments, blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules, without departing from the scope of the inventive concept.

[0063] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0064] However, the present disclosure is not limited to the following embodiments and may be modified into various forms. Each embodiment to be described below may be implemented alone or combined with at least another embodiment to form various combinations of embodiments.

[0065] Figure 1 is a diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0066] refer to Figure 1 , a display device 100 according to an embodiment of the present disclosure may include a pixel component 110 (or a display panel), a data driver 120 (eg, a driver circuit), a scan driver 130 (eg, a driver circuit), and a timing controller 140 (eg, a controller circuit).

[0067] The pixel part 110 may include pixels PX arranged to be connected to scan lines SL1, SL2, . . . , SLn (where n is a natural number greater than 0) and data lines DL1, DL2, . . . , DLm (where m is a natural number greater than 0).

[0068] The data lines DL1 to DLm may be disposed to extend in a first direction DR1. The first direction DR1 may be, for example, a direction in which the upper and lower sides of the pixel part 110 are connected to each other. Alternatively, the first direction DR1 may be a direction in which the left and right sides of the pixel part 110 are connected to each other, or may indicate other directions.

[0069] The scan lines SL1 to SLn may be disposed to extend in a second direction DR2. The second direction DR2 may be a direction perpendicular to the first direction DR1. The second direction DR2 may be, for example, a direction in which the left and right sides of the pixel component 110 are connected to each other. Alternatively, the second direction DR2 may be a direction in which the upper and lower sides of the pixel component 110 are connected to each other, or may indicate other directions.

[0070] The pixels PX may be disposed in the pixel part 110 to be electrically connected to the data lines DL1 to DLm and the scan lines SL1 to SLn. Here, the pixels PX may be sub-pixels. For example, the pixels PX may be disposed in various ways.

[0071] When the scan signal is supplied to the scan lines SL1 to SLn, the pixels PX may be selected in units of horizontal lines (e.g., the pixels PX connected to the same scan line may be grouped into one horizontal line (or pixel row)). Each of the pixels PX selected by the scan signal may receive a data signal from a corresponding data line (any one of DL1 to DLm) connected thereto. The pixel PX receiving the data signal may generate light having a specific brightness corresponding to the voltage of the data signal.

[0072] The data driver 120 may receive the output data Dout and the data driving signal DCS from the timing controller 140. The data driver 120 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 120 may generate an analog data signal based on the grayscale value of the output data Dout. The data driver 120 may supply the data signal in units of one horizontal period. The data driving signal DCS may include a data enable signal required to drive the data driver 120.

[0073] The data enable signal may include an active period in which a plurality of pulses are supplied and a blank period in which a constant voltage (eg, a low voltage) is maintained. The data driver 120 may supply data signals to the data lines DL1 to DLm in synchronization with pulses of the data enable signal during the active period.

[0074] The scan driver 130 may receive a scan driving signal SCS from the timing controller 140. The scan driving signal SCS may include start signals FLM1 and FLM2 and clock signals S1_CK and S2_CK.

[0075] In an embodiment, Figure 2 As shown in , each of the scan lines SL1 to SLn (e.g., scan line SLi) may include a scan line SCL (e.g., i-th scan line SCLi) and an initialization line SNL (e.g., i-th initialization line SNLi). The scan driver 130 may sequentially supply scan signals to the scan lines (e.g., SCLi) in response to a first start signal FLM1 and a scan clock signal S1_CK. The scan driver 130 may sequentially supply initialization signals to the initialization lines (e.g., SNLi) in response to a second start signal FLM2 and an initialization clock signal S2_CK.

[0076] For the above purpose, the scan driver 130 may include a first scan driver (not shown) configured to drive the scan line (e.g., SCLi) and a second scan driver (not shown) configured to drive the initialization line (e.g., SNLi). The first scan driver and the second scan driver may be formed as a single scan driver 130, such as Figure 1As shown in , or may be formed as separate drivers. For example, the first scan driver and the second scan driver may be disposed to be spaced apart from each other with the pixel part 110 interposed therebetween.

[0077] In an embodiment, the scan driver 130 may be provided as a separate integrated circuit (IC) in the display device 100. In an embodiment, the scan driver 130 together with the pixel PX may be formed during a process of forming the pixel part 110. For example, the scan driver 130 may be formed in the pixel part 110 in an oxide semiconductor thin film transistor gate driver circuit (OSG) type or an amorphous silicon thin film transistor gate driver circuit (ASG) type.

[0078] The timing controller 140 may receive input data Din and a control signal CS from an external device (e.g., an application processor). The timing controller 140 may rearrange or modify the input data Din to match the specifications of the display device 100. In addition, the timing controller 140 may correct the input data Din to generate output data Dout, and supply the output data Dout to the data driver 120. In an embodiment, the timing controller 140 may correct the input data Din in response to an optical measurement result obtained in a manufacturing process.

[0079] The timing controller 140 may generate a data driving signal DCS and a scan driving signal SCS using the control signal CS. The data driving signal DCS may be supplied to the data driver 120. The scan driving signal SCS may be supplied to the scan driver 130.

[0080] For example, the data driver 120, the scan driver 130, and the timing controller 140 may each be provided as an integrated circuit (IC) in the display device 100. For example, two or more components (eg, the data driver 120 and the timing controller 140) may be included in one integrated circuit (IC).

[0081] In an embodiment of the present disclosure, the display device 100 may include a flat display device, a curved display device in which a portion of the pixel component 110 is bent, a flexible display device in which a portion can be folded or bent, and a stretchable display device in which a portion can be stretched.

[0082] In an embodiment of the present disclosure, the display device 100 may be a device configured to display a video or a still image, and may include portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (tablet PC), a smart watch, a watch phone, a mobile communication terminal, an electronic note, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC). In an embodiment of the present disclosure, the display device 100 may include electronic devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IoT) device.

[0083] Figure 2 It is a graphic Figure 1 A circuit diagram of an embodiment of a pixel PX is shown in FIG. Figure 2 In the figure, for convenience of explanation, reference is made to a pixel PXij located on the i-th horizontal line and the j-th vertical line (i and j are natural numbers greater than 0).

[0084] refer to Figure 2 , a pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit configured to control an amount of current to be supplied to the light emitting element LD.

[0085] The light emitting element LD may include a first electrode (or anode electrode) electrically connected to the first power line PL1 via the second node N2 and the first transistor M1 and a second electrode (or cathode electrode) electrically connected to the second power line PL2. The light emitting element LD may generate light having a specific brightness corresponding to the amount of current supplied from the first transistor M1.

[0086] Here, the first driving power VDD may be supplied to the first power line PL1. The second driving power VSS may be supplied to the second power line PL2. During a period in which the pixel PXij emits light, the first driving power VDD has a high voltage value compared to the second driving power VSS.

[0087] An organic light emitting diode may be selected as the light emitting element LD. In addition, an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode may be selected as the light emitting element LD. The light emitting element LD may be an element formed by a combination of an organic material and an inorganic material. Figure 2 The pixel PX is shown to include a single light emitting element LD, but the pixel PX in the embodiment may include a plurality of light emitting elements. The plurality of light emitting elements may be connected in series, in parallel, or in series and parallel.

[0088] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst.

[0089] A first electrode of the first transistor M1 may be connected to the first power line PL1, and a second electrode of the first transistor M1 may be connected (e.g., electrically connected) to the second node N2. A gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control an amount of current flowing from the first power line PL1 to the second power line PL2 via the light emitting element LD in response to a voltage of the first node N1.

[0090] The second transistor M2 may be connected between the jth data line DLj and the first node N1. The gate electrode of the second transistor M2 may be electrically connected to the i-th scan line SCLi. When the scan signal SC is supplied to the i-th scan line SCLi, the second transistor M2 may be turned on to electrically connect the j-th data line DLj to the first node N1. If the second transistor M2 is turned on, the data signal Vdata may be supplied from the j-th data line DLj to the first node N1.

[0091] The scan signal SC may have a gate-on voltage (e.g., an enable level or a first logic level) or a gate-off voltage (e.g., a disable level or a second logic level). Hereinafter, the term "enable scan signal SC" may indicate that the gate-on voltage is supplied to the scan line (e.g., SCLi). The term "disable scan signal SC" may indicate that the gate-off voltage is supplied to the scan line (e.g., SCLi).

[0092] The third transistor M3 may be connected between the second node N2 and the third power line PL3. The gate electrode of the third transistor M3 may be electrically connected to the i-th initialization line SNLi. When the enable initialization signal IS is supplied to the i-th initialization line SNLi, the third transistor M3 may be turned on to electrically connect the second node N2 to the third power line PL3. If the third transistor M3 is turned on, the voltage of the reference power Vref may be supplied from the third power line PL3 to the second node N2.

[0093] The reference power Vref may be supplied to the third power line PL3. The voltage of the reference power Vref may be set to turn off the light emitting element LD when supplied to the second node N2. The voltage difference between the reference power Vref and the second driving power VSS may be less than the threshold voltage of the light emitting element LD to turn off the light emitting element LD. For example, the voltage of the reference power Vref may be set to a voltage that is the same as or close to the voltage of the second driving power VSS.

[0094] The initialization signal IS may have a gate-on voltage (e.g., an enable level) or a gate-off voltage (e.g., a disable level). Hereinafter, the term "enabling the initialization signal IS" may indicate that the gate-on voltage is supplied to the initialization line (e.g., SNLi). The term "disabling the initialization signal IS" may indicate that the gate-off voltage is supplied to the initialization line (e.g., SNLi).

[0095] Despite Figure 2 In the embodiment, each of the first to third transistors M1 to M3 is illustrated as an N-type transistor, but the embodiments of the present disclosure are not limited thereto. For example, at least one of the first to third transistors M1 to M3 may be implemented as a P-type transistor.

[0096] The storage capacitor Cst may be connected between the first node N1 and the second node N2. The storage capacitor Cst may store a voltage corresponding to the data signal Vdata. For example, the storage capacitor Cst may store a voltage corresponding to a voltage difference between the data signal Vdata supplied to the first node N1 and the reference power Vref supplied to the second node N2.

[0097] Figure 3 It is a graphic driver Figure 2 A waveform diagram of an embodiment of the method for a pixel PXij is shown in FIG.

[0098] refer to Figure 3 , one frame period may include a data writing period WP, ​​an emission period EP, and an initialization period IP. Here, the initialization period IP may be omitted or additionally included corresponding to the length (or refresh rate) of one frame period.

[0099] During the data writing period WP, ​​a data signal Vdata corresponding to an image of a corresponding frame may be written to the pixel PXij. During the data writing period WP, ​​an enable scan signal SC may be supplied to the i-th scan line SCLi, and an enable initialization signal IS may be supplied to the i-th initialization line SNLi to write data to the pixel PXij. Here, the enable scan signal SC supplied to the i-th scan line SCLi and the enable initialization signal IS supplied to the i-th initialization line SNLi may overlap each other.

[0100] If the enable scan signal SC is supplied to the i-th scan line SCLi, the second transistor M2 is turned on. If the second transistor M2 is turned on, the data signal Vdata may be supplied from the data line DLj to the first node N1. For example, the second transistor M2 may be turned on by a pulse of the scan signal SC.

[0101] If the enable initialization signal IS is supplied to the i-th initialization line SNLi, the third transistor M3 is turned on. For example, the third transistor M3 may be turned on by a pulse of the initialization signal IS. If the third transistor M3 is turned on, the voltage of the reference power Vref may be supplied to the second node N2. If the voltage of the reference power Vref is supplied to the second node N2, the light emitting element LD may be set to a non-emission state.

[0102] During the data write period WP, ​​a voltage corresponding to the voltage difference between the data signal Vdata and the reference power Vref may be stored in the storage capacitor Cst. Here, since the reference power Vref is maintained at a constant voltage, the voltage to be stored in the storage capacitor Cst may be determined by the voltage of the data signal Vdata.

[0103] During the emission period EP, the disabling scan signal SC may be supplied to the i-th scan line SCLi, and the disabling initialization signal IS may be supplied to the i-th initialization line SNLi. If the disabling scan signal SC is supplied to the i-th scan line SCLi, the second transistor M2 may be turned off. For example, the second transistor M2 may be turned off by the low-level scan signal SC. If the disabling initialization signal IS is supplied to the i-th initialization line SNLi, the third transistor M3 may be turned off. For example, the third transistor M3 may be turned off by the low-level initialization signal IS.

[0104] Here, the first transistor M1 can control the amount of current flowing from the first power line PL1 to the second power line PL2 via the light emitting element LD in response to the voltage of the first node N1 (i.e., the voltage stored in the storage capacitor Cst). As a result, during the emission period EP, the light emitting element LD can generate light with a certain brightness.

[0105] During the initialization period IP, the pixel PXij may be set to a non-emission state. During the initialization period IP, an enable initialization signal IS may be supplied to the i-th initialization line SNLi to set the pixel PXij to a non-emission state.

[0106] If the enable initialization signal IS is supplied to the i-th initialization line SNLi, the third transistor M3 is turned on. For example, the third transistor M3 may be turned on by a pulse of the initialization signal IS. If the third transistor M3 is turned on, the voltage of the reference power Vref may be supplied to the second node N2. If the voltage of the reference power Vref is supplied to the second node N2, the light emitting element LD may be set to a non-emission state.

[0107] During the emission period EP after the initialization period IP, the disable initialization signal IS is supplied to the i-th initialization line SNLi. As a result, the third transistor M3 can be turned off. For example, the third transistor M3 can be turned off by the low-level initialization signal IS. Here, the first transistor M1 can control the amount of current flowing from the first power line PL1 to the second power line PL2 via the light emitting element LD in response to the voltage of the first node N1 (i.e., the voltage stored in the storage capacitor Cst). As a result, during the emission period EP, the light emitting element LD can generate light with a specific brightness.

[0108] Figure 4 is a diagram illustrating an example of a blank period corresponding to a refresh rate. Figure 5A and Figure 5B is a diagram illustrating an embodiment of an initialization period IP corresponding to a refresh rate included in one frame period.

[0109] refer to Figure 4 In the embodiment, the length of the effective period included in one frame period is set to the same value regardless of the refresh rate (or driving frequency). In the present embodiment, the length of the blank period included in one frame period is set to different values ​​or adjusted according to the refresh rate.

[0110] For example, the effective period at a refresh rate of 120 Hz and the effective period at a refresh rate of 60 Hz may be set to the same length (or width, time). The effective period may refer to a period during which the data signal Vdata is supplied during one frame period. The data writing period WP may be included in the effective period.

[0111] For example, the blank period at a refresh rate of 120 Hz and the blank period at a refresh rate of 60 Hz are set to different lengths (or widths, times). For example, the blank period when the refresh rate is 120 Hz can be shorter than the blank period when the refresh rate is 60 Hz. The initialization period IP can be included in the blank period.

[0112] For example, Figure 5A As shown in , corresponding to a refresh rate of 120 Hz, an initialization period IP can be included in the blank period. Figure 5B As shown in , corresponding to a refresh rate of 60 Hz, three initialization periods IP may be included in the blank period (here, Figure 5A In this case the refresh rate can be set to Figure 5B twice the refresh rate in the case of ).

[0113] In the embodiments of the present disclosure, Figure 5A and Figure 5BAs shown in , the number of initialization periods IP included in one frame period can be set to different values ​​according to the length of the blank period. For example, as the length of the blank period increases, the number of initialization periods IP included in one frame period can increase.

[0114] As a result, regardless of the refresh rate (or regardless of the length of the blank period), the pixel PX can be turned off in cycles, thereby improving the visibility of the display device 100.

[0115] Figure 6 is a diagram illustrating an example of a driving waveform supplied during an effective period of one frame.

[0116] refer to Figure 6 , an effective period of one frame may include a data writing period WP. During the data writing period WP, ​​a scan signal SC may be sequentially supplied to scan lines SCL1, ..., SCLi, ..., and SCLn, and an initialization signal IS may be sequentially supplied to initialization lines SNL1, ..., SNLi, ..., and SNLn.

[0117] The scan driver 130 may generate a scan signal SC using a scan clock signal S1_CK, and may generate an initialization signal IS using an initialization clock signal S2_CK.

[0118] The scan clock signal S1_CK may include a plurality of clock signals. The scan driver 130 may sequentially supply the scan signal SC to the scan lines SCL1 to SCLn while shifting the first start signal FLM1 using the scan clock signal S1_CK.

[0119] The initialization clock signal S2_CK may include a plurality of clock signals. The scan driver 130 may sequentially supply the initialization signal IS to the initialization lines SNL1 to SNLn while shifting the second start signal FLM2 using the initialization clock signal S2_CK.

[0120] Figure 7 is a diagram illustrating an example of a driving waveform supplied during an initialization period of one frame.

[0121] refer to Figure 7 , a blank period of one frame may include an initialization period IP. During the initialization period IP, an initialization signal IS may be sequentially supplied to the initialization lines SNL1, . . . , SNLi, . . . , and SNLn.

[0122] The scan driver 130 may generate the initialization signal IS using the initialization clock signal S2_CK. The initialization clock signal S2_CK may include a plurality of clock signals. The scan driver 130 may sequentially supply the initialization signal IS to the initialization lines SNL1 to SNLn while shifting the second start signal FLM2 using the initialization clock signal S2_CK.

[0123] During the initialization period IP (or blank period), the disabled scan signal SC may be supplied to the scan lines SCL1 to SCLn. For example, the scan signal SC may be set to a disabled state. For example, during the initialization period IP, the scan lines SCL1 to SCLn may maintain a constant voltage (e.g., a low voltage). In response to this, during the blank period, the scan clock signal S1_CK may maintain a constant voltage (e.g., a low voltage). Accordingly, power consumption may be reduced.

[0124] Figure 8 is a diagram illustrating stages included in a scan driver according to a comparative example. Figure 8 In the figure, for the convenience of explanation, only one scanning clock signal S1_CK and one initialization clock signal S2_CK are shown. Figure 8 In the figure, for the convenience of explanation, three stages ST1, ST2 and ST3 are shown.

[0125] refer to Figure 8 Each of the stages ST1, ST2 and ST3 includes a first input terminal CR-, a second input terminal CR+, a third input terminal CLK1, a fourth input terminal CLK2, a reset input terminal RESET, a first output terminal S1, a second output terminal S2 and a carry output terminal CR.

[0126] The first input terminal CR- may receive a carry signal (or a start signal FLM) from a previous stage. In response to this, the scan driver according to the comparative example further includes a plurality of first dummy stages. The first dummy stages may be located in a stage before the first stage ST1.

[0127] The second input terminal CR+ may receive a carry signal from a subsequent stage. In response to this, the scan driver according to the comparative example further includes a plurality of second dummy stages. The second dummy stages may be located in a stage after the last stage.

[0128] The third input terminal CLK1 may receive the scan clock signal S1_CK. The stages ST1 to ST3 having received the scan clock signal S1_CK may sequentially output enable scan signals SC1, SC2, and SC3 through the corresponding first output terminals S1.

[0129] The fourth input terminal CLK2 may receive the initialization clock signal S2_CK. The stages ST1 to ST3 having received the initialization clock signal S2_CK may sequentially output enable initialization signals IS1, IS2, and IS3 through the corresponding second output terminals S2.

[0130] The reset input terminal RESET may be supplied with the start signal FLM. When the start signal FLM is supplied to the reset input terminal RESET, the stages ST1 to ST3 may be initialized.

[0131] The first output terminal S1 may output a scan signal SC. The second output terminal S2 may output an initialization signal IS. The carry output terminal CR may output a carry signal to a stage of a preceding set and a stage of a succeeding set.

[0132] Fig. 9 The diagram is provided by Figure 8 Graph of the drive waveform supplied by the stage illustrated in FIG.

[0133] refer to Fig. 9 During the effective period (or data writing period WP) of the first frame 1F, the scan signal SC is sequentially supplied to the scan lines SCL1 to SCLn, and the initialization signal IS is sequentially supplied to the initialization lines SNL1 to SNLn. Here, the voltage corresponding to the data signal may be stored in the pixel PX. During the effective period of the first frame 1F, each of the scan clock signal S1_CK and the initialization clock signal S2_CK is supplied in the form of a pulse.

[0134] The blank period of the first frame 1F may include an emission period EP and an initialization period IP.

[0135] During the emission period EP, each of the pixels PX may generate light having brightness corresponding to the data signal stored during the data writing period WP. During the emission period EP, each of the scan clock signal S1_CK and the initialization clock signal S2_CK maintains a constant voltage (eg, a low voltage).

[0136] During the initialization period IP, the initialization signal IS may be sequentially supplied to the initialization lines SNL1 to SNLn. Therefore, the pixels PX may be sequentially set to a non-emission state. During the initialization period IP, the scan clock signal S1_CK maintains a constant voltage (eg, a low voltage), and the initialization clock signal S2_CK is supplied in the form of a pulse.

[0137] During the initialization period IP of the first frame 1F, the initialization signal IS may be supplied to all of the initialization lines SNL1 to SNLn. In this case, the pixels PX included in the pixel part 110 may display an image while being in non-emission according to a period.

[0138] The effective period of the second frame 2F may be the same as that of the first frame 1F; therefore, a redundant description thereof will be omitted.

[0139] The blank period of the second frame 2F may include an emission period EP and an initialization period IP. The emission period EP may be the same as the emission period EP of the first frame 1F; therefore, a redundant description thereof will be omitted.

[0140] After the initialization signal IS is supplied to some initialization lines during the initialization period IP of the second frame 2F, switching from the second frame 2F to the third frame 3F may occur. In this case, the initialization signal IS is supplied to some initialization lines, while the initialization signal IS is not supplied to other initialization lines.

[0141] For example, when switching from the second frame 2F to the third frame 3F occurs, the start signal FLM may be supplied, and Figure 8 The stages ST1 to ST3 shown in the figure can be initialized by the start signal FLM. If the stages ST1 to ST3 are initialized, the initialization signal IS does not need to be supplied to other initialization lines. That is, the initialization period IP of the second frame 2F is set to a relatively short time so that the initialization signal IS is supplied to some initialization lines, while the initialization signal IS cannot be supplied to other initialization lines. For example, the initialization period IP of the second frame 2F is set to be shorter than the initialization period IP of the first frame 1F.

[0142] In other words, in the scan driver according to the comparative example, the initialization signal IS cannot be supplied to some initialization lines during the initialization period IP corresponding to the length of the blank period. In other words, a brightness difference may occur in an image displayed on the pixel part 110.

[0143] Fig.10 is a diagram illustrating a scan driver 130 according to an embodiment of the present disclosure. Fig.10 In the figure, for the convenience of explanation, only one scanning clock signal S1_CK and one initialization clock signal S2_CK are shown. Fig.10 In FIG. 1 , a first-stage FST and a second-stage SST are illustrated.

[0144] refer to Fig.10, the scan driver 130 according to an embodiment of the present disclosure may include a first stage FST and a second stage SST. However, the scan driver 130 is not limited to two stages, and may include more than two stages in other embodiments.

[0145] The first stage FST includes a first carry input terminal FCR-, a second carry input terminal FCR+, a scan clock input terminal FCLK, a first reset input terminal FRESET, a first output terminal S1, and a first carry output terminal FCR.

[0146] The first carry input terminal FCR- may receive a carry signal (or a first start signal FLM1) from a first stage in a previous stage set. Accordingly, the scan driver 130 according to an embodiment of the present disclosure may include at least one previous first dummy stage provided in a stage set located before the first stage FST.

[0147] The second carry input terminal FCR+ may receive a carry signal from a first stage in a subsequent stage set. Accordingly, the scan driver 130 according to an embodiment of the present disclosure may further include at least one subsequent first dummy stage provided in a stage set located after the first stage FST.

[0148] The scan clock input terminal FCLK may receive the scan clock signal S1_CK. The first stage FST may output the scan signal SC through the first output terminal S1 in response to the scan clock signal S1_CK. For example, the first stage FST may output an on-duty voltage (e.g., a high voltage) of the scan clock signal S1_CK as the scan signal SC through the first output terminal S1.

[0149] The first reset input terminal FRESET may receive a reset signal. When the reset signal is input, the first stage FST may be initialized. In an embodiment, the first start signal FLM1 may be input to the first reset input terminal FRESET as a reset signal.

[0150] The first output terminal S1 may output the scan signal SC. The first carry output terminal FCR may output a carry signal to a first stage in a previous stage set and a first stage in a subsequent stage set.

[0151] The second stage SST may include a first carry input terminal SCR-, a second carry input terminal SCR+, an initialization clock input terminal SCLK, a second reset input terminal SRESET, a second output terminal S2, and a second carry output terminal SCR.

[0152] The first carry input terminal SCR- may receive a carry signal (or a second start signal FLM2) from a second stage in a previous stage set. Accordingly, the scan driver 130 according to an embodiment of the present disclosure may include at least one previous second dummy stage provided in a stage set located before the second stage SST.

[0153] The second carry input terminal SCR+ may receive a carry signal from a second stage in a subsequent stage set. Accordingly, the scan driver 130 according to an embodiment of the present disclosure may include at least one subsequent second dummy stage provided in a stage set located after the second stage SST.

[0154] The initialization clock input terminal SCLK may receive the initialization clock signal S2_CK. The second stage SST may output the initialization signal IS through the second output terminal S2 in response to the initialization clock signal S2_CK. For example, the second stage SST may output the conduction section voltage (e.g., high voltage) of the initialization clock signal S2_CK through the second output terminal S2 as the initialization signal IS.

[0155] The second reset input terminal SRESET may receive a reset signal RST. When the reset signal RST is input, the second stage SST may be initialized. The reset signal RST may be supplied as a signal different from the start signals FLM1 and FLM2. Accordingly, even when the start signals FLM1 and FLM2 are supplied, the second stage SST may not be initialized.

[0156] The second output terminal S2 may output the initialization signal IS. The second carry output terminal SCR may output a carry signal to the second stage in the previous stage set and the second stage in the subsequent stage set.

[0157] Fig.11 is a diagram illustrating a scan driver 130 according to an embodiment of the present disclosure.

[0158] refer to Fig.11 , the scan clock signal S1_CK may include a plurality of scan clock signals S1_CK1, S1_CK2, S1_CK3, S1_CK4, S1_CK5, and S1_CK6. In an embodiment, the scan clock signals S1_CK1 to S1_CK6 have the same period and are phase-shifted signals. The scan clock signals S1_CK1 to S1_CK6 may be sequentially supplied to the first stage FST.

[0159] The initialization clock signal S2_CK may include a plurality of initialization clock signals S2_CK1, S2_CK2, S2_CK3, S2_CK4, S2_CK5, and S2_CK6. In an embodiment, the initialization clock signals S2_CK1 to S2_CK6 have the same cycle and are phase-shifted signals. The initialization clock signals S2_CK1 to S2_CK6 may be sequentially supplied to the second stage SST.

[0160] During the effective period of one frame, the first scan clock signal S1_CK1 and the first initialization clock signal S2_CK1 may have the same cycle and phase. In addition, the second scan clock signal S1_CK2 may have the same cycle and phase as the second initialization clock signal S2_CK2. The third scan clock signal S1_CK3 may have the same cycle and phase as the third initialization clock signal S2_CK3. Similarly, the fourth scan clock signal S1_CK4 may have the same cycle and phase as the fourth initialization clock signal S2_CK4. The fifth scan clock signal S1_CK5 may have the same cycle and phase as the fifth initialization clock signal S2_CK5. In addition, the sixth scan clock signal S1_CK6 may have the same cycle and phase as the sixth initialization clock signal S2_CK6.

[0161] The scan driver 130 may include a plurality of first stages FST and a plurality of second stages SST. The first stages FST may alternate with the second stages SST.

[0162] Each of the first-stage FSTs may be supplied with any one of the scan clock signals S1_CK1 to S1_CK6 (i.e., any one of S1_CK1 to S1_CK6). For example, the first-stage FST located at the first may be supplied with the first scan clock signal S1_CK1. The first-stage FST located at the second may be supplied with the second scan clock signal S1_CK2. For example, the first-stage FST located at the third may be supplied with the third scan clock signal S1_CK3. The first-stage FST located at the fourth may be supplied with the fourth scan clock signal S1_CK4. For example, the first-stage FST located at the fifth may be supplied with the fifth scan clock signal S1_CK5. The first-stage FST located at the sixth may be supplied with the sixth scan clock signal S1_CK6.

[0163] Each of the second-stage SSTs may be supplied with any one of the initialization clock signals S2_CK1 to S2_CK6 (i.e., any one of S2_CK1 to S2_CK6). For example, the first second-stage SST may be supplied with the first initialization clock signal S2_CK1. The second-stage SST may be supplied with the second initialization clock signal S2_CK2. For example, the third second-stage SST may be supplied with the third initialization clock signal S2_CK3. The fourth second-stage SST may be supplied with the fourth initialization clock signal S2_CK4. For example, the fifth second-stage SST may be supplied with the fifth initialization clock signal S2_CK5. The sixth second-stage SST may be supplied with the sixth initialization clock signal S2_CK6.

[0164] In an embodiment, during the active period, the enable scan signal SC supplied to the first scan line SCL1 and the enable initialization signal IS supplied to the first initialization line SNL1 overlap each other.

[0165] In this embodiment, during the emission period EP in the blank period of one frame, each of the scanning clock signals S1_CK1 to S1_CK6 and the initialization clock signals S2_CK1 to S2_CK6 maintains a constant voltage (eg, a low voltage). In this case, power consumption due to supplying the clock signals S1_CK and S2_CK can be reduced.

[0166] In the present embodiment, during the initialization period IP in the blank period of one frame, each of the scan clock signals S1_CK1 to S1_CK6 maintains a constant voltage (e.g., a low voltage). In the present embodiment, during the initialization period IP in the blank period of one frame, each of the initialization clock signals S2_CK1 to S2_CK6 is supplied in the form of a pulse. Accordingly, during the initialization period IP, the initialization signal IS may be supplied to the initialization lines SNL1 to SNLn.

[0167] Fig.12 The diagram is provided by Fig.10 and Fig.11 Graph of the drive waveform supplied by the stage illustrated in FIG.

[0168] refer to Fig.12 , the effective period of each frame 1F, 2F or 3F includes a data writing period WP.

[0169] During the effective period of each frame 1F, 2F, or 3F, the first start signal FLM1 and the pulse scan clock signal S1_CK are supplied Here, the first stage FST may sequentially supply the enable scan signal SC to the scan lines SCL1 to SCLn.

[0170] During the effective period of each frame 1F, 2F, or 3F, the second start signal FLM2 and the pulsed initialization clock signal S2_CK are supplied Here, the second stage SST may sequentially supply the enable initialization signal IS to the initialization lines SNL1 to SNLn.

[0171] In the embodiment, the enable scan signal SC supplied to the first scan line SCL1 and the enable initialization signal IS supplied to the first initialization line SNL1 overlap each other. In the present embodiment, the enable scan signal SC supplied to the nth scan line SCLn and the enable initialization signal IS supplied to the nth initialization line SNLn overlap each other.

[0172] During the data write period WP, ​​the voltage of the data signal may be stored in the pixel PX in units of horizontal lines. During the emission period EP of each frame 1F, 2F, or 3F, each of the pixels PX may generate light having a brightness corresponding to the data signal stored during the data write period WP. During the emission period EP, each of the scan clock signal S1_CK and the initialization clock signal S2_CK maintains a constant voltage (e.g., a low voltage).

[0173] During the initialization period IP of each frame 1F, 2F or 3F, the second start signal FLM2 and the pulsed initialization clock signal S2_CK are supplied. The second stage SST can sequentially output the initialization signal IS. Thus, the pixels PX can be sequentially set to a non-emission state in units of horizontal lines. During the initialization period IP, the scan clock signal S1_CK maintains a constant voltage (e.g., a low voltage).

[0174] Fig.13A and Fig. 13B It is a detailed diagram Fig.12 FIG. 1 is a diagram of a period between a second frame 2F and a third frame 3F shown in FIG.

[0175] refer to Fig.13A and Fig. 13B , after the initialization signal IS is supplied to some of the initialization lines during the initialization period IP of the second frame 2F, switching from the second frame 2F to the third frame 3F may occur.

[0176] For example, after the initialization signal IS is supplied to the first to i-th initialization lines SNL1 to SNLi during the initialization period IP of the second frame 2F, the holding period HP may follow, and then the third frame 3F may start.

[0177] Here, the holding period HP may be a preparation period for supplying the scan signal SC and the initialization signal IS. Fig.11As shown in , the scan driver 130 may be supplied with a plurality of scan clock signals S1_CK1 to S1_CK6 and a plurality of initialization clock signals S2_CK1 to S2_CK6. Here, it is necessary to control the supply timing of the initialization clock signals S2_CK1 to S2_CK6 to allow the initialization signal IS to be supplied to the first initialization line SNL1 after the third frame 3F starts, and this period may be referred to as a holding period HP. In an embodiment, during the holding period HP, each of the scan clock signal S1_CK and the initialization clock signal S2_CK maintains a constant voltage (e.g., a low voltage).

[0178] During the effective period of the third frame 3F, the first start signal FLM1 and the pulse scan clock signal S1_CK may be supplied. Here, the first stage FST may sequentially output the enable scan signal SC. During the effective period of the third frame 3F, the second start signal FLM2 and the pulse initialization clock signal S2_CK may be supplied. Here, the second stage SST may sequentially output the initialization signal IS.

[0179] In addition, because the second stage SST has not been initialized by the second start signal FLM2, the i-th second stage SST can maintain the carry signal. Therefore, during the effective period of the third frame 3F, the initialization signal IS can be sequentially supplied to the i+1th initialization line SNLi+1 to the nth initialization line SNLn. In other words, during the initialization period IP of the second frame 2F, the initialization signal IS is supplied to at most the i-th initialization line SNLi, and thereafter, during the holding period HP, the supply of the initialization signal IS is interrupted. When the effective period of the third frame 3F begins, the initialization signal IS can be sequentially supplied to the i+1th initialization line SNLi+1 to the nth initialization line SNLn. In an embodiment, during the effective period of the third frame 3F, the enable initialization signal is supplied to the two initialization lines in an overlapping manner. For example, as Fig. 13B As shown in FIG. 3 , during the effective period of the third frame 3F, the enable initialization signal supplied to the initialization line SNL1 overlaps the enable initialization signal supplied to the initialization line SNLi+1.

[0180] In other words, in the embodiment of the present disclosure, even if the frame changes during the initialization period IP, the initialization signal IS can be supplied to the subsequent frame. Fig. 9 Compared with the case where the display quality of the display device 100 can be improved.

[0181] In an embodiment, the initialization signal IS supplied to the i+1th initialization line SNLi+1 corresponding to the initialization period IP overlaps the scan signal SC supplied to the first scan line SCL1 and the initialization signal IS supplied to the first initialization line SNL1 corresponding to the data write period WP. In this case, the voltage of the reference power Vref may be supplied to the pixels located on the first horizontal line and the pixels located on the i+1th horizontal line. In other words, during the period of the third frame 3F, the pixels located in the area where the initialization period IP and the data write period WP overlap with each other (for example, the pixels located on the first horizontal line) may overlap with each other. Fig.13A The pixels in the first region 110a shown in FIG. 1 may each store a voltage of a data signal corresponding to a reference power Vref of a first voltage.

[0182] During the period of the third frame 3F, in the case where the initialization period IP and the data writing period WP do not overlap each other, the voltage of the reference power Vref may be supplied to the pixels located on one horizontal line. Fig.13A The pixels in the second region 110 b shown in FIG. 1 may store the voltage of the data signal corresponding to the reference power Vref of the second voltage different from the first voltage.

[0183] In this case, even when the same data signal is supplied during the period of the third frame 3F, images with different brightness can be displayed in the first area 110a and the second area 110b. For example, in response to the same data signal, a darker image can be displayed in the first area 110a than in the second area 110b.

[0184] Fig.14 It is a graphic Fig.12 FIG. 2F is a diagram showing a period between the second frame 2F and the third frame 3F shown in FIG. Fig.14 In the following description, the Fig.13A and Fig. 13B Description of the overlap.

[0185] refer to Fig.14 During the initialization period IP of the second frame 2F, the initialization signal IS may be sequentially supplied to the initialization lines SNL1 to SNLi. In an embodiment, after the frame is changed (ie, changed to the third frame 3F), the initialization signal IS is supplied to the initialization lines SNLi+1 to SNLn after a specific delay time (eg, a holding period HP).

[0186] In this case, the pixels (for example, located at Fig.14) and the pixels (eg, located in the first region 112a shown in FIG. 1 ) to which the initialization signal IS is supplied after the frame changes (ie, after changing to the third frame 3F). Fig.14 There may be a brightness difference between the pixels in the second region 112b shown in FIG. 2F. For example, even if the same data signal is supplied during the period of the second frame 2F, a darker image may be displayed in the first region 112a compared to the second region 112b.

[0187] Fig.15 It is a graphic with Fig.13A The image of the third frame 3F and Fig.14 FIG. 2 is a diagram showing the brightness of the pixel component 110 corresponding to the image of the second frame 2F.

[0188] refer to Fig.15 , as in Fig.13A As described in , the image displayed during the period of the third frame 3F has a brightness difference between the first area 110a and the second area 110b. Fig.14 As described in , the image displayed in the period of the second frame 2F has a brightness difference between the first area 112a and the second area 112b.

[0189] Here, the image of the second frame 2F and the image of the third frame 3F may be continuously displayed, thereby generating an average brightness difference in the first area 114 a , the second area 114 b , and the third area 114 c of the pixel part 110 .

[0190] The first region 114 a may refer to a region where pixels supplied with the initialization signal IS during the initialization period IP of the second frame 2F (or a previous frame) are located.

[0191] The second region 114 b may refer to a region where pixels to which the initialization signal IS corresponding to the second frame 2F is supplied during the data writing period WP of the third frame 3F (or the current frame) are located.

[0192] The third region 114 c may refer to a region where pixels to which the initialization signal IS corresponding to the second frame 2F is not supplied during the data writing period WP of the third frame 3F are located.

[0193] When the same data signal is supplied, the brightness of the pixel part 110 may be the lowest in the first area 114a and may be the highest in the third area 114c. In an embodiment of the present disclosure, the brightness deviation of the pixel part 110 can be eliminated by controlling the width of the enable scan signal SC and / or the enable initialization signal IS supplied during the period of the third frame 3F.

[0194] Fig.16 It is a graphic Figure 1An embodiment of the timing controller 140 is shown in FIG. Fig.16 , only components necessary for explaining the present disclosure are illustrated.

[0195] refer to Fig.16 According to an embodiment of the present disclosure, the timing controller 140 includes a driver 210 (e.g., a driver circuit), a blank period determination component 212 (e.g., a first logic circuit), an area determination component 215 (e.g., a second logic circuit), a scan clock generator 217, and an output component 224 (e.g., an output circuit).

[0196] The driver 210 may be driven in response to the first data enable signal DE1 and may include various components. For example, the driver 210 may include a component configured to compensate data in response to optical data, a component configured to compensate data in response to temperature, and a component configured to generate various control signals.

[0197] The driver 210 may supply the second data enable signal DE2 to the scan clock generator 217. The second data enable signal DE2 may be a signal delayed by a specific time from the first data enable signal DE1. Here, the specific time may be set to a value that varies according to components included in the driver 210, an operation time of each of the components, and the like. For example, Fig.18 As shown in , the second data enable signal DE2 may be delayed by the first time T1.

[0198] The blank period determination unit 212 can use the first data enable signal DE1 to determine the blank period included in the frame period. For example, the blank period determination unit 212 can count the period during which the first data enable signal DE1 is supplied to determine a frame period, and can determine the blank period in a frame period. For example, the effective period included in this frame period is fixed, so that the blank period corresponding to this frame period can be adjusted as needed. The blank period information (e.g., the width, length, time, etc. of the blank period) determined by the blank period determination unit 212 can be supplied to the area determination unit 215.

[0199] The region determination component 215 may include a first region determination component 214 (eg, a third logic circuit) and a second region determination component 216 (eg, a fourth logic circuit). The region determination component 215 may use the blank period information to determine Fig.15 The first region 114a, the second region 114b and the third region 114c are shown in FIG.

[0200] For example, the region determination unit 215 may use the blank period information to determine the region included in the previous frame PF (reference Fig.18) in the initialization period IP, and the first area 114a, the second area 114b and the third area 114c can be determined corresponding to the position of the initialization period IP.

[0201] The first region determining part 214 may determine a region (ie, the first region 114 a ) where pixels receiving the enable initialization signal IS during the period of the previous frame PF are located, corresponding to the position of the initialization period IP of the previous frame PF.

[0202] The second region determining unit 216 may determine the position of the initialization period IP in the current frame CF (reference period IP) corresponding to the position of the initialization period IP in the previous frame PF. Fig.17 ) is located in an area (ie, the second area 114b) where pixels receiving the enable initialization signal IS corresponding to the previous frame PF during the data writing period WP.

[0203] In the case where the first area 114a and the second area 114b are determined, the third area 114c where the pixels that do not receive the initialization signal IS corresponding to the previous frame PF during the data writing period WP of the current frame CF are located can be determined. Area information corresponding to the first area 114a and the second area 114b determined in the area determination part 215 can be supplied to the scan clock generator 217 and the output part 224.

[0204] The scan clock generator 217 may generate the scan clock signal S1_CK. In an embodiment, the scan clock generator 217 generates the scan clock signal S1_CK having different duty ratios corresponding to the first region 114a, the second region 114b, and the third region 114c, respectively.

[0205] The scan clock generator 217 includes a first scan clock generator 218 , a first lookup table ( LUT1 ) 219 , a second scan clock generator 220 , a second lookup table ( LUT2 ) 221 , and a third scan clock generator 222 .

[0206] The third scan clock generator 222 (or the common clock signal generator) may supply the third clock signal S1_CLK3 (or the common clock signal) having a specific duty cycle to the output part 224. The third clock signal S1_CLK3 may be supplied as the scan clock signal S1_CK to the first stage FST corresponding to the third region 114c. Here, the first stage FST corresponding to the third region 114c may refer to the first stage FST electrically connected to the scan line located in the third region 114c. The pixels located in the third region 114c may each be supplied with an enable scan signal SC having a width corresponding to the conduction section of the third clock signal S1_CLK3.

[0207] In an embodiment, the conduction section of the third clock signal S1_CLK3 has a third width W3 (or a normal width), such as Fig.17 and Fig.18 Here, the conduction section may refer to a width (or time) in which a gate-on voltage is applied to allow a transistor included in a pixel PX to be turned on. In addition, regardless of the number of scan lines (or the number of horizontal lines) included in the third region 114c, the conduction section of the third clock signal S1_CLK3 may maintain a constant width (i.e., a third width W3).

[0208] The first scan clock generator 218 may receive information about the first area 114a from the first area determining part 214. The first scan clock generator 218 having received the information about the first area 114a may extract duty ratio information from the first lookup table 219 corresponding to the number of scan lines (or the number of horizontal lines) included in the first area 114a.

[0209] The first scan clock generator 218 that extracts the duty cycle information from the first lookup table 219 can generate a first clock signal S1_CLK1 having a duty cycle corresponding to the duty cycle information, and supply the generated first clock signal S1_CLK1 to the output part 224. The first clock signal S1_CLK1 can be supplied to the first stage FST corresponding to the first area 114a as the scan clock signal S1_CK. Here, the first stage FST corresponding to the first area 114a can refer to the first stage FST electrically connected to the scan line located in the first area 114a. The pixels located in the first area 114a can each be supplied with an enable scan signal SC having a width corresponding to the conduction section of the first clock signal S1_CLK1.

[0210] In an embodiment, the conduction section of the first clock signal S1_CLK1 has a first width W1. Fig.17 and Fig.18 In an embodiment, the first width W1 is set to be greater than (or longer than) the third width W3. In other words, the pixels located in the first area 114a may be supplied with an enable scan signal SC having a larger width (ie, the first width W1) than the pixels located in the third area 114c.

[0211] The width of the conduction section may be set to different values ​​corresponding to the number of scan lines included in the first region 114 a . Duty ratio (or conduction section) information corresponding to the number of scan lines included in the first region 114 a may be stored in the first lookup table 219 .

[0212] The second scan clock generator 220 may receive information about the second area 114b from the second area determining part 216. The second scan clock generator 220 having received the information about the second area 114b may extract duty ratio information from the second lookup table 221 corresponding to the number of scan lines (or the number of horizontal lines) included in the second area 114b.

[0213] The second scan clock generator 220 that extracts the duty cycle information from the second lookup table 221 can generate a second clock signal S1_CLK2 having a duty cycle corresponding to the duty cycle information, and supplies the generated second clock signal S1_CLK2 to the output part 224. The second clock signal S1_CLK2 can be supplied to the first stage FST corresponding to the second area 114b as the scan clock signal S1_CK. Here, the first stage FST corresponding to the second area 114b can refer to the first stage FST electrically connected to the scan line located in the second area 114b. The pixels located in the second area 114b can each be supplied with an enable scan signal SC having a width corresponding to the conduction section of the second clock signal S1_CLK2.

[0214] In an embodiment, the conduction section of the second clock signal S1_CLK2 is set to a second width W2 that is larger than the third width W3 and smaller than the first width W1. Fig.17 and Fig.18 The pixels located in the second area 114b may be supplied with the enable scan signal SC having the second width W2.

[0215] The width of the conduction section may be set to different values ​​corresponding to the number of scan lines (or the number of horizontal lines) included in the second area 114b. Duty ratio (or conduction section) information corresponding to the number of scan lines included in the second area 114b may be stored in the second lookup table 221.

[0216] The output part 224 may receive a signal corresponding to the region information from the region determination part 215. For example, in the case where the pixel part 110 is divided into a plurality of regions, the region determination part 215 may supply region information signals AIS1 and AIS2. The region information signals AIS1 and AIS2 may include information corresponding to the first region 114a and the second region 114b, respectively. In an embodiment, the region information signals AIS1 and AIS2 may further include information corresponding to the third region 114c.

[0217] For example, in the case where the pixel part 110 is formed of a single area, the area determination part 215 does not need to supply the area information signals AIS1 and AIS2. Here, if the pixel part 110 is formed of a single area, it can be indicated that during the data writing period WP of the current frame, the enable initialization signal IS of the previous frame is not supplied.

[0218] In the case where the area information signals AIS1 and AIS2 are not input from the area determination part 215, the output part 224 may supply the third clock signal S1_CLK3 as the scan clock signal S1_CK to all of the first stage FST included in the scan driver 130. As a result, the scan lines SCL1 to SCLn may each receive the enable scan signal SC having the third width W3. In other words, according to an embodiment of the present disclosure, if the initialization signal IS of the previous frame is not supplied during the data write period WP of the current frame, the enable scan signal SC having the third width W3 may be supplied.

[0219] In the case where the area information signals AIS1 and AIS2 are input from the area determination part 215, the output part 224 can supply the first clock signal S1_CLK1 as the scan clock signal S1_CK to each of the first stages FST corresponding to the first area 114a. As a result, the scan lines located in the first area 114a can each receive the enable scan signal SC having the first width W1.

[0220] In the case where the area information signals AIS1 and AIS2 are input from the area determination part 215, the output part 224 can supply the second clock signal S1_CLK2 as the scan clock signal S1_CK to each of the first stages FST corresponding to the second area 114b. As a result, the scan lines located in the second area 114b can each receive the enable scan signal SC having the second width W2.

[0221] In the case where the area information signals AIS1 and AIS2 are input from the area determination part 215, the output part 224 can supply the third clock signal S1_CLK3 as the scan clock signal S1_CK to each of the first stages FST corresponding to the third area 114c. As a result, the scan lines located in the third area 114c can each receive the enable scan signal SC having the third width W3.

[0222] Fig.17 and Fig.18 is a diagram illustrating a process of supplying a scan signal according to an embodiment of the present disclosure.

[0223] refer to Fig.17 and Fig.18, the scan lines SCL1 , SCL2 , . . . , and SCLi located in the first region 114 a each receive an enable scan signal SC having a first width W1 in response to the first clock signal S1_CLK1 .

[0224] The scan lines SCLi+1, SCLi+2, . . . located in the second region 114 b each receive the enable scan signal SC having the second width W2 in response to the second clock signal S1_CLK2.

[0225] The scan lines SCLn located in the third region 114c each receive the enable scan signal SC having the third width W3 in response to the third clock signal S1_CKL3.

[0226] In an embodiment, the first width W1 is set to be greater than the second width W2. Therefore, the pixels located in the first region 114a can receive the voltage of the data signal for a longer time than the pixels located in the second region 114b. In this case, even if the same data signal is supplied, the first region 114a can generate light with higher brightness than the second region 114b.

[0227] In an embodiment, the second width W2 is set to be greater than the third width W3. Accordingly, the pixels located in the second region 114b can receive the voltage of the data signal for a longer time than the pixels located in the third region 114c. In this case, even if the same data signal is supplied, the second region 114b can generate light with higher brightness than the third region 114c.

[0228] In other words, in an embodiment of the present disclosure, enable scan signals SC having different widths may be supplied to the corresponding regions 114a, 114b, and 114c to reduce the brightness deviation between the regions 114a, 114b, and 114c. Here, the third width W3 may remain fixed, while the first width W1 and the second width W2 may be determined experimentally based on the number of scan lines included in each of the first region 114a and the second region 114b to reduce the brightness deviation.

[0229] In addition, the data write period WP may be referred to as a first mode, and the initialization period IP may be referred to as a second mode. Here, in a case where a period in which the i-th pixel row (where i is a natural number greater than 0) operates in the first mode overlaps with a period in which the i+a-th pixel row (where a is a natural number greater than 0) operates in the second mode, a scan signal having a first width W1 is supplied to the i-th scan line, and a scan signal having a second width W2 is supplied to the i+a-th scan line. In addition, a scan signal having a third width W3 is supplied to the i+a+b-th scan line located on the i+a+b-th pixel row (where b is a natural number greater than 0) that operates only in the first mode. For example, as Fig.17 As shown in FIG. 1 , during the effective period, the enable initialization signal supplied to the initialization line SNL1 overlaps the enable initialization signal supplied to the initialization line SNLi+1.

[0230] Fig.19 It is a graphic Figure 1 An embodiment of the timing controller 140 is shown in FIG. Fig.19 In the figure, only the components necessary for explaining the present disclosure are shown. Fig.19 In the following description, we will briefly mention Fig.16 Redundant descriptions of similar or identical constructions.

[0231] refer to Fig.19 , the timing controller 140 according to an embodiment of the present disclosure may include a driver 210 , a blank period determining part 212 , a region determining part 215 , and an initialization clock generator 317 .

[0232] The driver 210 may be driven in response to the first data enable signal DE1 and may include various components. The driver 210 may supply the second data enable signal DE2 to the initialization clock generator 317. The second data enable signal DE2 may be a signal delayed by a specific time from the first data enable signal DE1. Fig.21 As shown in , the second data enable signal DE2 may be delayed by the first time T1.

[0233] The blank period determination unit 212 may determine a blank period included in a frame period using the first data enable signal DE1 . The blank period information (eg, width, length, time, etc. of the blank period) determined by the blank period determination unit 212 may be supplied to the region determination unit 215 .

[0234] The area determination component 215 may include a first area determination component 214 and a second area determination component 216. The area determination component 215 may use the blank period information to determine Fig.15The first region 114a, the second region 114b and the third region 114c are shown in FIG.

[0235] The first region determining part 214 may determine a region (ie, the first region 114 a ) where pixels receiving the enable initialization signal IS during the period of the previous frame PF are located, corresponding to the position of the initialization period IP of the previous frame PF.

[0236] The second region determining unit 216 may determine a region (ie, the second region 114 b ) where pixels receiving the enable initialization signal IS corresponding to the previous frame PF during the data writing period WP of the current frame CF are located, corresponding to the position of the initialization period IP of the previous frame PF.

[0237] In the case where the first area 114a and the second area 114b are determined, the third area 114c where the pixels that do not receive the enable initialization signal IS corresponding to the previous frame PF during the data write period WP of the current frame CF are located can be determined. The area information corresponding to the first area 114a and the second area 114b determined in the area determination part 215 can be supplied to the initialization clock generator 317 and the output part 324.

[0238] The initialization clock generator 317 may generate the initialization clock signal S2_CK. Here, the initialization clock generator 317 may generate the initialization clock signal S2_CK having different duty ratios corresponding to the first region 114a, the second region 114b, and the third region 114c, respectively.

[0239] In an embodiment, the initialization clock generator 317 includes a first initialization clock generator 318 , a first lookup table ( LUT1 a ) 319 , a second initialization clock generator 320 , a second lookup table ( LUT2 a ) 321 , and a third initialization clock generator 322 .

[0240] The third initialization clock generator 322 (or the general clock signal generator) can supply the third clock signal S2_CLK3 (or the general clock signal) having a specific duty cycle to the output part 324. The third clock signal S2_CLK3 can be supplied as the initialization clock signal S2_CK to the second stage SST corresponding to the third region 114c. Therefore, the pixels located in the third region 114c can each be supplied with an enable initialization signal IS having a width corresponding to the conduction section of the third clock signal S2_CLK3.

[0241] In an embodiment, the conduction section of the third clock signal S2_CLK3 has a third width W3a (or a normal width), such as Fig. 20 and Fig.21Regardless of the number (or size, surface area, etc.) of initialization lines (or the number of horizontal lines) included in the third region 114c, the turn-on section of the third clock signal S2_CLK3 may maintain a constant width (ie, the third width W3a).

[0242] The first initialization clock generator 318 may receive information about the first region 114a from the region determination part 215. The first initialization clock generator 318 having received the information about the first region 114a may extract duty cycle information from the first lookup table 319 corresponding to the number of initialization lines (or the number of horizontal lines) included in the first region 114a.

[0243] The first initialization clock generator 318 that has extracted the duty cycle information from the first lookup table 319 may generate a first clock signal S2_CLK1 having a duty cycle corresponding to the duty cycle information, and supply the generated first clock signal S2_CLK1 to the output part 324. The first clock signal S2_CLK1 may be supplied as an initialization clock signal S2_CK to the second stage SST corresponding to the first region 114a. Therefore, the pixels located in the first region 114a may each be supplied with an enable initialization signal IS having a width corresponding to the conduction section of the first clock signal S2_CLK1.

[0244] In an embodiment, the conduction section of the first clock signal S2_CLK1 has a first width W1a. Fig. 20 and Fig.21 As shown in . In an embodiment, the first width W1a is set to be smaller than (or shorter than) the width of the third width W3a. Therefore, compared with the pixels located in the third area 114c, the pixels located in the first area 114a can be supplied with an enable initialization signal IS having a smaller width (i.e., the first width W1a). The width of the conduction section can be set to different values ​​corresponding to the number of initialization lines included in the first area 114a. The duty cycle (or conduction section) information corresponding to the number of initialization lines included in the first area 114a can be stored in the first lookup table 319.

[0245] The second initialization clock generator 320 may receive information about the second region 114b from the region determination part 215. The second initialization clock generator 320 having received the information about the second region 114b may extract duty ratio information from the second lookup table 321 corresponding to the number of initialization lines included in the second region 114b.

[0246] The second initialization clock generator 320 that has extracted the duty cycle information from the second lookup table 321 can generate a second clock signal S2_CLK2 having a duty cycle corresponding to the duty cycle information, and supply the generated second clock signal S2_CLK2 to the output part 324. The second clock signal S2_CLK2 can be supplied as the initialization clock signal S2_CK to the second stage SST corresponding to the second region 114b. Therefore, the pixels located in the second region 114b can each be supplied with an enable initialization signal IS having a width corresponding to the conduction section of the second clock signal S2_CLK2.

[0247] In an embodiment, the conduction section of the second clock signal S2_CLK2 may have a width smaller than the third width W3a and larger than the first width W1a, such as Fig. 20 and Fig.21 Therefore, the pixels located in the second area 114b may be supplied with the enable initialization signal IS having the second width W2a.

[0248] The width of the conduction section may be set to different values ​​corresponding to the number of initialization lines included in the second region 114 b . Duty ratio (or conduction section) information corresponding to the number of initialization lines included in the second region 114 b may be stored in the second lookup table 321 .

[0249] The output part 324 may receive a signal corresponding to the region information from the region determination part 215. For example, in the case where the pixel part 110 is divided into a plurality of regions, the region determination part 215 may supply region information signals AIS1 and AIS2. The region information signals AIS1 and AIS2 may include information corresponding to the first region 114a and the second region 114b, respectively. In an embodiment, the region information signals AIS1 and AIS2 may further include information corresponding to the third region 114c.

[0250] For example, in the case where the pixel part 110 is formed of a single area, the area determination part 215 does not need to supply the area information signals AIS1 and AIS2. Here, if the pixel part 110 is formed of a single area, it can be indicated that during the data writing period WP of the current frame, the enable initialization signal IS of the previous frame is not supplied.

[0251] In the case where the area information signals AIS1 and AIS2 are not input from the area determination part 215, the output part 324 may supply the third clock signal S2_CLK3 as the initialization clock signal S2_CK to all of the second stage SST included in the scan driver 130. As a result, the initialization lines SNL1 to SNLn may each receive the enable initialization signal IS having the third width W3a. In other words, in an embodiment of the present disclosure, if the enable initialization signal IS of the previous frame PF is not supplied during the data write period WP of the current frame CF, the enable initialization signal IS having the third width W3a may be supplied.

[0252] In the case where the area information signals AIS1 and AIS2 are input from the area determination part 215, the output part 324 may supply the first clock signal S2_CLK1 as the initialization clock signal S2_CK to each of the second stages SST corresponding to the first area 114a. As a result, the initialization lines located in the first area 114a may each receive the enable initialization signal IS having the first width W1a.

[0253] In the case where the area information signals AIS1 and AIS2 are input from the area determination part 215, the output part 324 can supply the second clock signal S2_CLK2 as the initialization clock signal S2_CK to each of the second stages SST corresponding to the second area 114b. As a result, the initialization lines located in the second area 114b can each receive the enable initialization signal IS having the second width W2a.

[0254] In the case where the area information signals AIS1 and AIS2 are input from the area determination part 215, the output part 324 can supply the third clock signal S2_CLK3 as the initialization clock signal S2_CK to each of the second stages SST corresponding to the third area 114c. As a result, the initialization lines located in the third area 114c can each receive the enable initialization signal IS having the third width W3a.

[0255] although Fig.19 The timing controller 140 including only a component for controlling the width of the enable initialization signal IS is illustrated, but the embodiments of the present disclosure are not limited thereto. Fig.19 The timing controller 140 may further include Fig.16 2 and 3. In this case, the width of the enable scan signal SC may also be controlled together with the width of the enable initialization signal IS.

[0256] Fig. 20 and Fig.21is a diagram illustrating a process of supplying an initialization signal according to an embodiment of the present disclosure.

[0257] refer to Fig. 20 and Fig.21 , the initialization lines SNL1 , SNL2 , . . . , and SNLi located in the first region 114 a each receive the enable initialization signal IS having the first width W1 a in response to the first clock signal S2_CLK1 .

[0258] The initialization lines SNLi+1, SNLi+2, . . . located in the second region 114 b each receive the enable initialization signal IS having the second width W2 a in response to the second clock signal S2_CLK2 .

[0259] Each of the initialization lines SNLn, . . . and SNLn located in the third region 114c receives the enable initialization signal IS having the third width W3a in response to the third clock signal S2_CLK3.

[0260] In an embodiment, the first width W1a is set to be smaller than the second width W2a. Therefore, the pixels located in the first region 114a can receive the voltage of the reference power Vref in a shorter time than the pixels located in the second region 114b. In this case, even if the same data signal is supplied, the first region 114a can generate light with higher brightness than the second region 114b.

[0261] In an embodiment, the second width W2a is set to be smaller than the third width W3a. Therefore, compared with the pixels located in the third region 114c, the pixels located in the second region 114b can receive the voltage of the reference power Vref in a shorter time. In this case, even if the same data signal is supplied, the second region 114b can generate light with higher brightness than the third region 114c.

[0262] In other words, in the embodiment of the present disclosure, the enable initialization signal IS having different widths can be supplied to the corresponding regions 114a, 114b, and 114c, thereby reducing the brightness deviation between the regions 114a, 114b, and 114c. Here, the third width W3a can be kept fixed, while the first width W1a and the second width W2a can be determined by experiment based on the number of horizontal lines (or the number of initialization lines) included in each of the first region 114a and the second region 114b to reduce the brightness deviation.

[0263] In addition, the data write period WP may be referred to as the first mode, and the initialization period IP may be referred to as the second mode. Here, in the case where the period in which the i-th pixel row operates in the first mode overlaps with the period in which the i+a-th pixel row (where a is a natural number greater than 0) operates in the second mode, the initialization signal having the first width W1a (or the fourth width) is supplied to the i-th initialization line, and the initialization signal having the second width W2a (or the fifth width) is supplied to the i+a-th initialization line. In addition, the initialization signal having the third width W3a (or the sixth width) is supplied to the i+a+b-th initialization line located on the i+a+b-th pixel row (where b is a natural number greater than 0) that operates only in the first mode.

[0264] In the display device and the method of driving the display device according to the embodiment of the present disclosure, visibility can be improved, whereby images can be displayed at various refresh rates.

[0265] However, the effects of the present disclosure are not limited to the above-described effects, and various modifications are possible without departing from the spirit and scope of the present disclosure.

[0266] Although the embodiments of the present disclosure have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure.

Claims

1. A display device, comprising: A display panel including pixels connected to scan lines and initialization lines; a scan driver including a first stage configured to supply an enable scan signal to the scan line during an effective period of one frame and a second stage configured to supply an enable initialization signal to the initialization line during the effective period and a blank period of the one frame; as well as a timing controller configured to supply a scan clock signal and an initialization clock signal to the scan driver, Wherein, when the enable initialization signal is supplied to two of the initialization lines in an overlapping manner during the effective period of the current frame, the enable scan signals having different widths are supplied to corresponding areas of the display panel.

2. The display device according to claim 1, wherein: In the effective period of the current frame, the area of ​​the display panel includes: a first region where pixels to which the enable initialization signal is supplied during the blank period of the previous frame are located; a second region where pixels to which the enabling initialization signal corresponding to the blank period of the previous frame is supplied are located; and a third region other than the first region and the second region.

3. The display device according to claim 2, wherein: During the effective period of the current frame, the scan driver: supplying an enable scan signal having a first width to a scan line located in the first area; supplying an enable scan signal having a second width different from the first width to a scan line located in the second region; and An enable scan signal having a third width different from the first width and the second width is supplied to the scan line located in the third region.

4. The display device according to claim 3, wherein: The first width is greater than the second width, and the second width is greater than the third width.

5. The display device according to claim 3, wherein: The timing controller comprises: a driver configured to receive a first data enable signal and to operate in response to the first data enable signal; a first logic circuit configured to determine a length of a blank period using the first data enable signal; a second logic circuit configured to determine the first area and the second area based on the length of the blank period determined by the first logic circuit; a scan clock generator configured to receive the second data enable signal output from the driver to generate the scan clock signals corresponding to the first region, the second region, and the third region, respectively; and The output circuit is configured to output the scan clock signal.

6. The display device according to claim 5, wherein: The second data enable signal is the first data enable signal delayed by a preset time.

7. The display device according to claim 5, wherein: The second logic circuit comprises: a third logic circuit configured to determine the first region based on the length of the blank period determined by the first logic circuit; and A fourth logic circuit is configured to determine the second area based on the length of the blank period determined by the first logic circuit.

8. The display device according to claim 5, wherein: The scan clock generator comprises: a first lookup table configured to store duty cycle information corresponding to the number of scan lines included in the first area; a first scan clock generator connected to the first lookup table and configured to generate a first clock signal having a conduction section having the first width corresponding to the number of the scan lines included in the first area; a second lookup table configured to store duty ratio information corresponding to the number of scan lines included in the second area; a second scan clock generator connected to the second lookup table and configured to generate a second clock signal having a conduction section having the second width corresponding to the number of the scan lines included in the second region; and The third scan clock generator is configured to generate a third clock signal having a conduction section having the third width.

9. The display device according to claim 8, in, The first lookup table stores duty ratio information having the first width having different values ​​corresponding to the number of the scan lines included in the first area, and The second lookup table stores duty cycle information having the second width, and the second width has different values ​​corresponding to the number of the scan lines included in the second area.

10. The display device according to claim 8, wherein: The output circuit: supplying the first clock signal as the scan clock signal to the first stage connected to the scan line located in the first area, supplying the second clock signal as the scan clock signal to the first stage connected to the scan line located in the second area, and The third clock signal is supplied as the scan clock signal to the first stage connected to the scan line located in the third area.

Images