Two-bus communication system, method and main module

Abstract

The invention discloses a two-bus communication system, a two-bus communication method and a main module. The main module comprises a high-voltage area and a low-voltage area, wherein the high-voltage area comprises a current-voltage I-V conversion circuit and a voltage division circuit; the I-V conversion circuit is used for converting an uplink real-time current signal in a bus into an uplink real-time voltage signal; the voltage division circuit is used for performing voltage division processing on a downlink voltage signal in the bus to obtain a bus power supply voltage signal; the low-voltage area comprises a coprocessor and is used for performing analog-to-digital (AD) conversion on the uplink real-time voltage signal to obtain uplink real-time current data; converting the bus power supply voltage signal to obtain bus power supply current data; separating uplink data current from the uplink real-time current data based on the bus power supply current data; and converting the uplink data current into serial data to obtain uplink data. The bit error rate of two-bus communication is greatly reduced, the retransmission times of communication between devices are reduced, and the effectiveness of data transmission and the real-time performance of communication are ensured.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a dual-bus communication system, method and main module. Background Art

[0002] Traditional four-wire communication technology uses two power supply lines and two communication lines, while two-bus communication technology combines the power supply line and the signal line into one. Compared with the four-wire communication system, the signal and power supply share one bus. In the two-bus communication technology, the downlink data uses a voltage signal, usually an AC voltage square wave signal, and the control circuit of the AC voltage square wave signal uses an H-bridge circuit; the uplink data uses a current signal, and the current-voltage (IV) conversion in the line is detected by a hardware circuit to directly detect the sudden change of the bus current as the detection method of the uplink data. Summary of the invention

[0003] The inventor of the present application has found that in the existing two-bus communication technology, since the bus voltage signal of the downlink data is an AC voltage square wave signal, it is easily interfered during long-distance transmission, and the anti-interference ability of the downlink data of the AC voltage square wave signal is weak, which greatly increases the bit error rate of the downlink data; using a square wave to drive the H-bridge circuit is likely to cause a single bridge arm to pass directly, causing damage to the circuit and poor stability of the driving circuit. Moreover, since the detection of the uplink data is implemented by hardware, when the current fluctuation of the device on the bus is large, the hardware detection method may not be able to accurately detect the sudden change of the bus current after the current-voltage (IV) conversion, resulting in a high bit error rate of the uplink current data. Therefore, in the existing two-bus communication technology, the bit error rates of both the uplink and downlink data are relatively high, resulting in a large number of retransmissions during communication between devices, and the real-time communication between devices cannot be guaranteed.

[0004] In view of the above problems, the present invention is proposed to provide a two-bus communication system, method and main module that overcome the above problems or at least partially solve the above problems.

[0005] An embodiment of the present invention provides a dual-bus communication main module, including: a high-voltage area and a low-voltage area;

[0006] The high-voltage area includes a current-voltage IV conversion circuit and a voltage divider circuit; the IV conversion circuit is used to convert the uplink real-time current signal in the bus into an uplink real-time voltage signal; the voltage divider circuit is used to divide the downlink voltage signal in the bus to obtain a bus power supply voltage signal;

[0007] The low-voltage area includes a coprocessor, which is used to perform analog-to-digital AD conversion on the uplink real-time voltage signal to obtain uplink real-time current data with bus power supply current and uplink data current superimposed; and convert the bus power supply voltage signal to obtain bus power supply current data; separate the uplink data current from the uplink real-time current data based on the bus power supply current data; and convert the uplink data current into serial data to obtain uplink data.

[0008] In some optional embodiments, the high-voltage region includes a high-voltage interface circuit to communicate with the slave through two buses; the high-voltage region exchanges data with the low-voltage region through the FN_BUS bus, and the low-voltage region includes a low-voltage interface circuit to obtain downlink data sent to the slave from an external processor or to transmit uplink data received from the slave to the external processor.

[0009] In some optional embodiments, the high voltage region further includes: a sending module, a receiving module, an H-bridge control circuit and a driving circuit;

[0010] The receiving module is used to receive the uplink real-time current signal sent by the slave;

[0011] The coprocessor is further used to perform format conversion and waveform modulation on the acquired downlink data to obtain a downlink voltage signal and send it to the high voltage area;

[0012] The H-bridge control circuit is used to perform waveform modulation on the downlink voltage signal modulated by the coprocessor;

[0013] The sending module is used to send the modulated downlink voltage signal to the slave through the second bus;

[0014] The driving circuit is used to drive the H-bridge control circuit to work.

[0015] In some optional embodiments, the high-pressure region further includes:

[0016] A bus short-circuit detection circuit is used to detect whether the bus is in a short-circuit state;

[0017] The power regulating circuit is used to realize the conversion between high voltage and low voltage, and / or the conversion between high current and low current.

[0018] In some optional embodiments, the low voltage area further includes: a micro control unit, a clock circuit and a power supply circuit;

[0019] The micro control unit is arranged between the coprocessor and the serial data interface, provides the downlink data obtained from the external processor to the coprocessor, and transmits the uplink data separated by the coprocessor to the external processor through the transmission serial data interface.

[0020] In some optional embodiments, the coprocessor is further configured to determine whether the current communication state of the bus is downstream communication or upstream communication according to a voltage waveform of a downstream voltage signal in the bus.

[0021] In some optional embodiments, the uplink current signal between the master module and the slave module adopts a pulse current signal, and the downlink voltage signal adopts a trapezoidal voltage signal.

[0022] An embodiment of the present invention provides a two-bus communication system, comprising: a master module and a slave using two-bus communication;

[0023] The main module is the above-mentioned two-bus communication main module;

[0024] The slave module is used to receive a downlink voltage signal sent by the master module and / or send an uplink current signal to the master module.

[0025] In some optional embodiments, the slave includes: a transmitting module, a receiving module and a Dc-Dc power supply module;

[0026] The transmitting module is used to receive the downlink voltage signal sent by the main module;

[0027] The receiving module is used to send an uplink current signal to the main module;

[0028] The Dc-Dc power supply module is used to supply power to the transmitting module and the receiving module.

[0029] An embodiment of the present invention provides a two-bus communication method, including:

[0030] The uplink real-time current signal in the bus received by the high-voltage area in the main module is converted into an uplink real-time voltage signal through a current-voltage IV conversion circuit; and the downlink voltage signal in the bus is divided by a voltage divider circuit to obtain a bus power supply voltage signal;

[0031] The uplink real-time voltage signal is subjected to analog-to-digital AD conversion in a low-voltage area in the main module to obtain uplink real-time current data superimposed with bus power supply current and uplink data current; and the bus power supply voltage signal is converted to obtain bus power supply current data; uplink data current is separated from the uplink real-time current data based on the bus power supply current data; and the uplink data current is converted into serial data to obtain uplink data.

[0032] In some optional embodiments, the above method further includes:

[0033] The acquired downlink data is format converted and waveform modulated in the low-voltage area to obtain a downlink voltage signal which is sent to the high-voltage area;

[0034] The downstream voltage signal is waveform modulated in the high voltage region and then sent to the slave via the second bus.

[0035] In some optional embodiments, the above method further includes: judging whether the current communication state of the bus is downstream communication or upstream communication according to the voltage waveform of the downstream voltage signal in the bus.

[0036] An embodiment of the present invention provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, the above-mentioned two-bus communication method is implemented.

[0037] The beneficial effects of the above technical solution provided by the embodiment of the present invention include at least:

[0038] The two-bus communication main module, communication system and method provided by the embodiment of the present invention convert the uplink real-time current signal in the bus into an uplink real-time voltage signal through an IV conversion circuit in the high-voltage region; perform voltage division processing on the downlink voltage signal in the bus through a voltage divider circuit to obtain a bus power supply voltage signal; perform analog-to-digital AD conversion on the uplink real-time voltage signal through a software algorithm set in a coprocessor in the low-voltage region to obtain uplink real-time current data superimposed with the bus power supply current and the uplink data current, convert the bus power supply voltage signal to obtain the bus power supply current data, so as to separate the uplink data current from the uplink real-time current data based on the bus power supply current data, thereby obtaining the uplink data transmitted by the slave, and combining software and hardware to realize uplink current detection, so as not to cause inaccurate current detection due to large current fluctuations of devices on the bus, effectively improve the accuracy of uplink data transmission, greatly reduce the bit error rate of uplink data transmission, reduce the number of retransmissions caused by bit errors, effectively ensure the real-time nature of communication between devices and the effectiveness of data transmission, and improve the speed and efficiency of data transmission.

[0039] The above-mentioned master module, when transmitting the downlink voltage signal to the slave, modulates it into a trapezoidal waveform for transmission, effectively avoiding the problem of single bridge arm direct pass that is easy to occur when the square wave signal drives the H-bridge circuit, and greatly improves the stability of the driving circuit. At the same time, the trapezoidal signal is not easily interfered with during long-distance transmission, and has strong anti-interference ability, which effectively improves the accuracy of downlink data transmission, reduces the bit error rate, and reduces the number of retransmissions caused by bit errors, effectively ensuring the real-time communication between devices and the effectiveness of data transmission, and improving the speed and efficiency of data transmission.

[0040] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0041] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0043] Figure 1 This is an example diagram of a single bridge arm direct-through in square wave driving in an embodiment of the present invention;

[0044] Figure 2 It is a structural diagram of a second bus communication system in an embodiment of the present invention;

[0045] Figure 3 This is an example diagram of a trapezoidal wave drive without single bridge arm direct conduction in an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of the structure of the second bus communication main module in an embodiment of the present invention;

[0047] Figure 5 Schematic diagram of the implementation process of uplink current detection in an embodiment of the present invention;

[0048] Figure 6 This is a circuit structure example diagram of the second bus communication main module in an embodiment of the present invention;

[0049] Figure 7 It is a schematic diagram of the structure of the second bus communication slave in an embodiment of the present invention;

[0050] Figure 8 Flow chart of the second bus communication method in an embodiment of the present invention;

[0051] Fig. 9 A schematic diagram of the implementation process of downlink data transmission in an embodiment of the present invention;

[0052] Fig.10 This is a flow chart of downlink data processing of the second bus communication in an embodiment of the present invention;

[0053] Fig.11 The figure is a schematic diagram of the implementation process of uplink data transmission in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0055] The existing two-bus communication technology uses AC voltage square wave signals for downlink data transmission, which is easily interfered with during long-distance transmission, has a high bit error rate, and easily causes single bridge arm direct pass when the square wave drives the H-bridge control circuit. Figure 1 The two-bus communication control circuit shown in the figure is the H-bridge circuit. When the H-bridge circuit is driven by a square wave, the current direction of the single bridge arm is as follows: Figure 1 As shown by the dotted line on the left side of the figure. When detecting the current of the uplink data, the hardware circuit is used without the cooperation of the software algorithm, and the bit error rate is high. Therefore, the existing two-bus communication technology has a relatively high bit error rate for uplink and downlink data transmission, resulting in a large number of data retransmissions and poor real-time communication between devices.

[0056] In order to partially or completely solve the problems existing in the prior art, an embodiment of the present invention provides a two-bus communication system, which is a communication system that can realize both power supply and communication on two lines, and its structure is as follows Figure 2 As shown, the system includes a master module and a slave using two bus communications.

[0057] The main module is used to receive the uplink real-time current signal in the bus in the high-voltage area, convert it into the uplink real-time voltage signal through the current-voltage IV conversion circuit; and divide the downlink voltage signal in the bus through the voltage divider circuit to obtain the bus power supply voltage signal; perform analog-to-digital AD conversion on the uplink real-time voltage signal in the low-voltage area to obtain the uplink real-time current data superimposed with the bus power supply current and the uplink data current; and convert the bus power supply voltage signal to obtain the bus power supply current data; separate the uplink data current from the uplink real-time current data based on the bus power supply current data; convert the uplink data current into serial data to obtain the uplink data.

[0058] The slave module is used to receive the downlink voltage signal sent by the master module and / or send the uplink current signal to the master module.

[0059] See also Figure 2 As shown, the master module and the slave communicate through the two-bus communication technology. As shown in the figure, two buses are connected from the master module N1 and N2 interfaces. The slaves are connected to the two buses through two communication lines. One master can connect to multiple slaves. In this system, the downlink signal between the master module and the slave can use a trapezoidal voltage signal, see Figure 2The frequency modulated voltage signal shown in the figure can be a pulse current signal for the uplink signal. Square wave signals can be used between the master module and other devices, and between the slave and other devices. The bus voltage of the system can be between 12V and 48V. When detecting the uplink current, the system can be implemented through software algorithms. The communication pulse current and the bus power supply current are automatically identified through the proprietary algorithm in the module, which improves the accuracy of detection and reduces the bit error rate. The downlink voltage signal is modulated into an AC trapezoidal wave signal, which improves the anti-interference ability and greatly improves the reliability of system communication.

[0060] The above system can use non-polarity wiring, and different topologies can be selected between the master module and the slave as needed, such as tree topology, star topology, bus topology, etc. The above system can achieve a communication distance of 1Km using ordinary RV1.5 two-core cable. The bus power supply voltage can be adaptive in a wide range of 12 to 48V, and the bus power supply current can be greater than 1A.

[0061] The system can adopt half-duplex communication and has a software interrupt reporting and processing function to improve the real-time performance of bus communication. The system also has a bus short-circuit detection and protection function to improve system safety.

[0062] See also Figure 3 As shown in FIG. 1 , when a trapezoidal voltage signal is used to drive the control circuit, the H-bridge circuit, single-bridge arm shoot-through can be avoided. Figure 3 As shown by the middle dotted line, the flow starts from the position V+ on the upper side, first passes through the left circuit and then through the right circuit to the V- position.

[0063] The two-bus communication main module provided in the embodiment of the present invention is a two-bus communication module with wide voltage and current adaptation, and its structure is as follows: Figure 4 As shown, the process of upstream current detection in the main module can be found in Figure 5 As shown; including: a high voltage area and a low voltage area. The high voltage area includes a current-voltage IV conversion circuit and a voltage divider circuit; the IV conversion circuit is used to convert the uplink real-time current signal in the bus into an uplink real-time voltage signal; the voltage divider circuit is used to divide the downlink voltage signal in the bus to obtain a bus power supply voltage signal;

[0064] The low-voltage area includes a coprocessor, which is used to perform analog-to-digital AD conversion on the uplink real-time voltage signal to obtain uplink real-time current data with bus power supply current and uplink data current superimposed; and to convert the bus power supply voltage signal to obtain bus power supply current data; separate the uplink data current from the uplink real-time current data based on the bus power supply current data; and convert the uplink data current into serial data to obtain uplink data.

[0065] The IV conversion circuit can be provided separately, or the IV conversion circuit can be provided in the receiving module.

[0066] In some optional embodiments, the high-voltage region includes a high-voltage interface circuit to communicate with the slave through two buses; the high-voltage region exchanges data with the low-voltage region through the FN_BUS bus, and the low-voltage region includes a low-voltage interface circuit to obtain downlink data sent to the slave from an external processor or transmit uplink data received from the slave to the external processor.

[0067] Optionally, the high voltage area further includes: a transmitting module, a receiving module, an H-bridge control circuit and a driving circuit;

[0068] The receiving module is used to receive the uplink real-time current signal sent by the slave; the received uplink real-time current signal is modulated by the H-bridge control circuit and converted into an uplink real-time voltage signal through the IV conversion circuit. The uplink real-time voltage signal can be sent to the coprocessor via a dedicated bus between the low-voltage area and the high-voltage area. The uplink real-time voltage signal is converted into uplink real-time current data in the coprocessor. The uplink real-time current data is essentially the superposition of the bus power supply current and the uplink data current. The bus power supply current and the uplink data current are separated in the coprocessor, so as to realize the conversion of the bus consumption current and the separated uplink data current into serial data, so as to obtain the uplink data. The detection of the uplink current and the separation of the data are realized through the software algorithm, which is not completely dependent on the hardware, avoiding the inaccurate hardware recognition caused by the current fluctuation, improving the accuracy of the uplink data transmission, and reducing the bit error rate.

[0069] The coprocessor is also used to convert the format and waveform modulate the acquired downlink data to obtain a downlink voltage signal and send it to the high-voltage area; the H-bridge control circuit is used to perform waveform modulation on the downlink voltage signal modulated by the coprocessor; the sending module is used to send the modulated downlink voltage signal to the slave through the second bus; the driving circuit is used to drive the H-bridge control circuit to work.

[0070] For downlink data, in the coprocessor, the downlink data to be sent to the slave machine obtained from the external processor can be converted into the required data format, and then waveform modulated into a square wave voltage signal, which is sent to the high-voltage area via a dedicated bus between the low-voltage area and the high-voltage area; in the high-voltage area, the square wave voltage signal is modulated into a trapezoidal wave voltage signal as a downlink voltage signal through a sending module and an H-bridge control circuit, and the downlink voltage signal is sent to the slave machine through the second bus.

[0071] Optionally, the high pressure area also includes:

[0072] The bus short-circuit detection circuit is used to detect whether the bus is in a short-circuit state; the bus short-circuit fault is discovered in time for reporting and processing, thereby improving the real-time performance of communication.

[0073] The power regulating circuit is used to realize the conversion between high voltage and low voltage, and / or the conversion between high current and low current.

[0074] Optionally, the low voltage area further includes: a micro control unit, a clock circuit and a power supply circuit;

[0075] The micro control unit is arranged between the coprocessor and the serial data interface, provides the downlink data obtained from the external processor to the coprocessor, and transmits the uplink data separated by the coprocessor to the external processor through the transmission serial data interface.

[0076] Optionally, the coprocessor is also used to determine whether the current communication state of the bus is downlink communication or uplink communication according to the voltage waveform of the downlink voltage signal in the bus. Since the voltage and current are time-sequential, the current cannot be processed at the rising and falling edges of the trapezoidal wave voltage, and can only be processed at non-zero points. Therefore, it is necessary to identify the communication state in the bus and process the current when it can be processed.

[0077] Optionally, the uplink current signal between the master module and the slave uses a pulse current signal, and the downlink voltage signal uses an AC frequency-modulated voltage signal, preferably a trapezoidal voltage signal. Downlink data is modulated into an AC voltage signal with a trapezoidal waveform, which can effectively avoid single-arm direct pass and improve the system's anti-interference ability.

[0078] An exemplary circuit structure of the main module can be found in Figure 6 As shown, the IV conversion circuit is set in the receiving module as an example.

[0079] The main module can be made of a circuit board and a customized metal shell filled with epoxy resin. The interior is divided into a low-voltage area (LV area) and a high-voltage area (HV area). The high and low voltage areas are connected by a dedicated FNbus bus for data exchange. The high-voltage area is equipped with two bus interfaces (BUS-N1 and BUS-N2) to realize the sending and receiving of bus data; the low-voltage area is equipped with a sending interface (TXD) and a receiving interface (RXD) to obtain serial data from an external processor and send it to a slave, or to provide serial data received from a slave to an external processor.

[0080] The high-voltage area mainly includes the high-voltage interface circuit (InterfaceCircuit) for data transmission and reception, and also realizes the function of trapezoidal wave modulation. The high-voltage area includes the transmission module (Tx Module), the receiving module (Rx Module), the H-bridge control circuit (H-bridge Circuit) and the drive circuit (H-bridge Drive); the high-voltage area is also equipped with a bus short-circuit detection circuit (Bus Short Check Module) and a power regulation circuit (PowerRegulation). The receiving module (Rx Module) processes the real-time current on the bus into a voltage signal, that is, IV conversion. The real-time current of the slave line includes the superimposed data current and the consumption current of the device. Through software filtering, the voltage change trend and the current fluctuation trend are separated by an algorithm to obtain the current consumed by the bus, and the uplink data current is obtained, so that the uplink data can be analyzed.

[0081] The low-voltage area mainly implements the module's external low-voltage data interface, including microcontroller unit (IF-MCU), data transceiver interface (TXD, RXD) and adaptive algorithm coprocessor (Co-Processor), clock circuit (clk-PLL), power supply circuit (LDO) and other functions. The high-precision current detection circuit and proprietary software algorithm in the Co-Processor module process the real-time changing current on the bus through the proprietary software algorithm, identify the current consumed by the bus device and the current of the uplink communication data, realize the current adaptation, and then convert the uplink pulse current signal into a digital signal and transmit it to the IF-MCU, which is output from the module's TXD pin to the external processor.

[0082] The proprietary software processing flow of the Co-Processor module is shown in Figure 5 shown.

[0083] The real-time bus current, that is, the uplink real-time current signal in the bus includes the bus power supply current and the uplink data current. The uplink data current can be an uplink data pulse current. The uplink real-time current signal is converted into an uplink real-time voltage signal through the IV conversion circuit on the main module. After being sent to the low-voltage area, the voltage signal is converted into the uplink real-time current data Iz through AD through the coprocessor (Co-Processor).

[0084] The bus voltage waveform, that is, the downstream voltage signal in the bus or the downstream data waveform sent by the main module, is converted into the voltage signal required by the co-processor through the voltage divider circuit in the main module. The co-processor determines the current state of the bus communication based on this voltage waveform, whether it is downstream communication or upstream communication, and thus determines whether the current signal can be processed. For the downstream voltage signal, voltage division processing can be performed to process the high voltage into a low voltage, and the downstream voltage signal can be converted into the bus power supply current Is.

[0085] The uplink real-time current signal Iadc on the bus can be processed by a selected filtering method, such as Kalman filtering, to filter out noise data in the current signal and restore the real real-time current data on the bus. The uplink real-time current signal Iadc is converted by IV and AD to obtain the uplink real-time current data Iz.

[0086] The uplink data current detection and separation processing process includes: when the bus state is in downlink communication, the current data at this time is the bus power supply current Is, that is, the device consumption current; when the bus state is in uplink communication, the current data at this time is the sum of the bus power supply current and the uplink data pulse current Iz; therefore, it can be considered that: the uplink data pulse current It = Iz-Is.

[0087] The uplink data pulse current It is converted into ship-shaped data in a co-processor, thereby obtaining the uplink data.

[0088] In some optional embodiments, in the above system, an exemplary circuit structure of the slave is shown in Figure 7 As shown, the slave includes: a transmitting module, a receiving module and a Dc-Dc power supply module;

[0089] Transmitter module (Tx Module), used to receive the downlink voltage signal sent by the main module;

[0090] A receiving module (Rx Module), used to send an upstream current signal to the main module;

[0091] The DC-DC (Direct Current-Direct Current) power module is used to power the transmitter module and the receiver module. The DC-DC power module can be used to convert the voltage of a DC power supply into another voltage.

[0092] The slave is equipped with two bus interfaces (BUS-N1, BUS-N2) to realize the sending and receiving of bus data; it is equipped with a sending interface (TXD) and a receiving interface (RXD) to obtain serial data from the external processor and send it to the master module, or provide the serial data received from the master module to the external processor. The slave transceiver circuit components can adopt the separated component circuit method, which is more convenient for hardware developers to design the bus total circuit.

[0093] Based on the unified inventive concept, the embodiment of the present invention also provides a two-bus communication method, and its uplink data detection processing flow is as follows: Figure 8 For the implementation principle, see Fig. 9 As shown, the method includes:

[0094] S101: converting the uplink real-time current signal in the bus received by the high-voltage area in the main module into an uplink real-time voltage signal through a current-voltage IV conversion circuit.

[0095] S102: Perform voltage division processing on the downstream voltage signal in the bus by means of a voltage division circuit to obtain a bus power supply voltage signal.

[0096] The execution order of the above S101 and S102 is not critical, and the order can be swapped or they can be executed simultaneously.

[0097] S103: performing analog-to-digital conversion on the uplink real-time voltage signal in the low-voltage area of ​​the main module to obtain uplink real-time current data superimposed with the bus power supply current and the uplink data current.

[0098] S104: Convert the bus power supply voltage signal to obtain bus power supply current data.

[0099] The execution order of the above S103 and S104 is not particular, and the order can be swapped or they can be executed simultaneously.

[0100] S105: Separating the uplink data current from the uplink real-time current data based on the bus power supply current data.

[0101] S106: Convert the uplink data current into serial data to obtain uplink data.

[0102] For details of the processing flow of the above uplink data current signal, please refer to Fig. 9 As shown:

[0103] The slave on the bus changes the current consumption on the bus by pulse mode. The slave sends the uplink data to the master module through the second bus in the form of uplink current signal via BUS-N1\N2.

[0104] After the main module receives the uplink real-time current signal, the receiving module (Rx Module circuit module) in the high-voltage area of ​​the main module performs IV conversion on the current on the bus to obtain the uplink real-time voltage signal. At this time, the voltage signal is the conversion of the uplink data current of the device on the bus and the current consumed by the device uploading data.

[0105] The main module transmits this voltage signal to the co-processor in the low-voltage area through the FN bus, and the uplink data current of the data uploaded by the device is identified through the proprietary software algorithm inside the Co-Processor. The uplink data current of the data uploaded by the device is converted into universal serial data through the microcontroller unit (IF-MCU) and output to the external processor through the TXD pin of the main module.

[0106] In some optional embodiments, the above method further includes a processing flow of downlink data. The processing flow of downlink data is shown in Fig.10 For the implementation principle, see Fig.11 Shown include:

[0107] S201: Performing format conversion and waveform modulation on the acquired downlink data in the low voltage area to obtain a downlink voltage signal and sending it to the high voltage area.

[0108] S202: Modulate the waveform of the downlink voltage signal in the high voltage region and send it to the slave through the second bus.

[0109] The processing flow of the above downlink data voltage signal can be found in Fig.11 shown.

[0110] After the main module receives the downlink data through the RXD pin, the IF-MCU in the low-voltage area converts the data into the data format required by the Co-Processor. The Co-Processor modulates the data into a frequency-modulated square wave voltage signal through a dedicated software algorithm.

[0111] The Co-Processor transmits the frequency-modulated square wave voltage signal to the transmitter module (Tx Module circuit module) in the high-voltage area through the FN bus. The Tx Module circuit module modulates the square wave data into a trapezoidal wave voltage signal with a certain slope, amplifies it through the H-bridge circuit, and transmits it to the bus.

[0112] In some optional embodiments, the above method further includes: judging whether the current communication state of the bus is downstream communication or upstream communication according to the voltage waveform of the downstream voltage signal in the bus.

[0113] An embodiment of the present invention further provides a computer storage medium, in which computer executable instructions are stored. When the computer executable instructions are executed by a processor, the above-mentioned two-bus communication method is implemented.

[0114] Regarding the methods and systems in the above embodiments, the relevant contents have been described in detail in one part and will not be elaborated in detail in the other part.

[0115] Due to the different types of devices connected to the two buses, the current of the devices is not constant when they are working, and the bus current consumption fluctuates greatly when the devices are controlling the action. Therefore, a circuit and software algorithm are needed to distinguish the bus current consumption and the uplink data current in real time. The two-bus communication system and method of the embodiment of the present invention can realize a software algorithm that distinguishes the current consumed by the bus devices and the uplink communication data current. Such an algorithm can greatly reduce the communication bit error rate of the two buses, reduce the number of retransmissions of communication between devices, and provide high real-time communication.

[0116] Unless otherwise specifically stated, terms such as processing, computing, calculating, determining, displaying, etc. may refer to the actions and / or processes of one or more processing or computing systems, or similar devices, which operate and convert data represented as physical (e.g., electronic) quantities within registers or memories of a processing system into other data similarly represented as physical quantities within memories, registers, or other such information storage, transmission, or display devices of the processing system. Information and signals may be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0117] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0118] In the above detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are clearly stated in each claim. On the contrary, as reflected in the appended claims, the invention is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the appended claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0119] Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments herein can all be implemented as electronic hardware, computer software, or a combination thereof. In order to clearly illustrate the interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above around their functions. Whether such functions are implemented as hardware or software depends on specific applications and the design constraints imposed on the entire system. A skilled person can implement the described functions in an alternative manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of protection of the present disclosure.

[0120] The steps of the method or algorithm described in conjunction with the embodiments herein may be directly embodied as hardware, a software module executed by a processor, or a combination thereof. The software module may be located in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a mobile disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and the storage medium may be located in an ASIC. The ASIC may be located in a user terminal. Of course, the processor and the storage medium may also be present in a user terminal as discrete components.

[0121] For software implementation, the techniques described in this application can be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described in this application. These software codes can be stored in a memory unit and executed by a processor. The memory unit can be implemented within the processor or outside the processor. In the latter case, it is coupled to the processor in a communication manner via various means, which are well known in the art.

[0122] The above description includes examples of one or more embodiments. Of course, it is impossible to describe all possible combinations of components or methods for the purpose of describing the above embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", just as "including," is explained as a transitional word in the claims. In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

Claims

1. A dual bus communication main module, characterized in that: include: areas of high and low pressure; The high-voltage area includes a current-voltage IV conversion circuit and a voltage divider circuit; the IV conversion circuit is used to convert the uplink real-time current signal in the bus into an uplink real-time voltage signal; the voltage divider circuit is used to divide the downlink voltage signal in the bus to obtain a bus power supply voltage signal; The low voltage area includes a coprocessor, the coprocessor is used to perform analog-to-digital AD conversion on the uplink real-time voltage signal to obtain uplink real-time current data superimposed with bus power supply current and uplink data current; and convert the bus power supply voltage signal to obtain bus power supply current data; Separating an uplink data current from the uplink real-time current data based on the bus power supply current data; The uplink data current is converted into serial data to obtain uplink data.

2. The main module according to claim 1, characterized in that: The high-voltage area includes a high-voltage interface circuit to communicate with the slave through the second bus; the high-voltage area exchanges data with the low-voltage area through the FN_BUS bus, and the low-voltage area includes a low-voltage interface circuit to obtain downlink data sent to the slave from the external processor or transmit uplink data received from the slave to the external processor.

3. The main module according to claim 1, characterized in that: The high voltage area also includes: a sending module, a receiving module, an H-bridge control circuit and a driving circuit; The receiving module is used to receive the uplink real-time current signal sent by the slave; The coprocessor is also used to perform format conversion and waveform modulation on the acquired downlink data to obtain a downlink voltage signal and send it to the high voltage area; The H-bridge control circuit is used to perform waveform modulation on the downlink voltage signal modulated by the coprocessor; The sending module is used to send the modulated downlink voltage signal to the slave through the second bus; The driving circuit is used to drive the H-bridge control circuit to work.

4. The main module according to claim 3, characterized in that: The high-pressure area further includes: A bus short-circuit detection circuit is used to detect whether the bus is in a short-circuit state; The power regulating circuit is used to realize the conversion between high voltage and low voltage, and / or the conversion between high current and low current.

5. The main module according to claim 1, characterized in that: The low voltage area also includes: a micro control unit, a clock circuit and a power supply circuit; The micro control unit is arranged between the coprocessor and the serial data interface, provides the downlink data obtained from the external processor to the coprocessor, and transmits the uplink data separated by the coprocessor to the external processor through the transmission serial data interface.

6. The main module according to claim 1, characterized in that: The coprocessor is further used to determine whether the current communication state of the bus is downlink communication or uplink communication according to the voltage waveform of the downlink voltage signal in the bus.

7. The main module according to any one of claims 1 to 6, characterized in that: The uplink current signal between the master module and the slave module adopts a pulse current signal, and the downlink voltage signal adopts a trapezoidal voltage signal.

8. A two-bus communication system, characterized in that: include: Master and slave modules using two-bus communication; The main module is the dual-bus communication main module described in any one of claims 1-7; The slave module is used to receive a downlink voltage signal sent by the master module and / or send an uplink current signal to the master module.

9. The system according to claim 8, characterized in that The slave includes: a transmitting module, a receiving module and a Dc-Dc power supply module; The transmitting module is used to receive the downlink voltage signal sent by the main module; The receiving module is used to send an uplink current signal to the main module; The Dc-Dc power supply module is used to supply power to the transmitting module and the receiving module.

10. A two-bus communication method, characterized in that: include: The uplink real-time current signal in the bus received by the high-voltage area in the main module is converted into an uplink real-time voltage signal through a current-voltage IV conversion circuit; And performing voltage division processing on the downlink voltage signal in the bus through a voltage division circuit to obtain a bus power supply voltage signal; Performing analog-to-digital conversion on the uplink real-time voltage signal in the low-voltage area of ​​the main module to obtain uplink real-time current data superimposed with bus power supply current and uplink data current; and converting the bus power supply voltage signal to obtain bus power supply current data; Separating an uplink data current from the uplink real-time current data based on the bus power supply current data; The uplink data current is converted into serial data to obtain uplink data.

11. The method according to claim 10, characterized in that Also includes: The acquired downlink data is format converted and waveform modulated in the low-voltage area to obtain a downlink voltage signal which is sent to the high-voltage area; The downstream voltage signal is waveform modulated in the high voltage region and then sent to the slave via the second bus.

12. The method according to any one of claims 10-11, characterized in that: Also includes: The current communication state of the bus is determined to be downstream communication or upstream communication according to the voltage waveform of the downstream voltage signal in the bus.

13. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by the processor, the two-bus communication method described in any one of claims 10-12 is implemented.

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